Patent Application
20240203912
Embodiments of the subject matter described herein relate generally to amplifier modules, and more particularly to amplifier modules that include power transistor dies.
Wireless communication systems employ power amplifier modules for increasing the power of radio frequency (RF) signals. A power amplifier module includes a module substrate and amplifier circuitry coupled to a mounting surface of the module substrate. A typical module substrate also may include input and output (I/O) terminals on a bottom surface of the module (i.e., the surface opposite the module mounting surface), and conductive signal routing structures extending through and across the module substrate between the I/O terminals and bondpads at the mounting surface. Further one or more ground/thermal dissipation structures may extend through the module substrate between the mounting and bottom surfaces.
The amplifier circuitry often includes a power transistor die, which has at least one integrated power transistor with a bottom-side conductive ground layer. The bottom-side conductive ground layer of the power transistor die is directly connected to the surface(s) of the ground/thermal dissipation structure(s) that are exposed at the mounting surface of the module substrate. Along with functioning to remove heat from the power transistor die, the ground/thermal dissipation structure(s) may function to provide a ground reference to the power transistor die.
To convey RF signals between the module substrate and the power transistor die, electrical connections are made between the bondpads at the mounting surface of the module substrate and the I/O bondpads of the power transistor die. When the integrated power transistor is a field effect transistor (FET), the die's input bondpad connects to the gate terminal of the FET, and the die's output bondpad connects to the drain terminal of the FET. The source terminal of the FET is coupled through the die to the bottom-side, conductive ground layer, which in turn is connected to the ground/thermal dissipation structure(s) of the module substrate, as described above.
To integrate the above-described power amplifier module into a communication system, the module typically is coupled to a mounting surface of a system printed circuit board (PCB). More specifically, the module substrate bottom surface is connected to the top surface of the system PCB so that bottom-side module signal I/O terminals align with corresponding signal I/O pads on the PCB mounting surface. In addition, the module substrate is connected to the system PCB so that the module ground/thermal dissipation structure(s) contact a PCB heat spreader that extends through the system PCB. Accordingly, the combination of the module ground/thermal dissipation structure and the system PCB heat spreader may perform the dual function of providing a thermal pathway to remove heat generated by the power transistor die, and providing a ground reference to the power transistor die.
During operation, the power transistor amplifies input RF signals received through the transistor die input bondpad, and conveys the amplified RF signal to the transistor die output bondpad. All the while, heat generated by the power transistor die is dissipated through the ground/thermal dissipation structure(s) embedded in the module substrate and through the system PCB heat spreader, and a ground reference also is provided through the ground/thermal dissipation structure(s) and the system PCB heat spreader.
The above-described configuration works well for many applications. However, other applications may require a different configuration in which a thermal path for the heat produced by the power transistor die extends in a direction away from the system PCB, rather than through the system PCB. Such different configurations generate new challenges, however, including challenges associated with providing an adequate ground reference for the power transistor dic.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
Embodiments of the inventive subject matter described herein include amplifier systems with a system substrate (e.g., a printed circuit board (PCB)) and a power amplifier module coupled to the system substrate. The power amplifier module includes a module substrate with an embedded heat dissipation structure, and a power amplifier die connected to the embedded heat dissipation structure. The power amplifier module is mounted to the system substrate in a “flipped orientation” with the embedded heat dissipation structure facing away from the system substrate, in contrast with conventional systems in which the embedded heat dissipation structure is coupled to a heat spreader in the system substrate. Accordingly, in an embodiment, a heat sink may be connected directly to the exposed surface of the embedded heat dissipation structure of the power amplifier module.
In such a system, proper grounding of the power amplifier die to the system substrate is important to achieve good performance. It is known that current (DC or RF) must travel in a closed loop. “Return current” is defined as the current flowing through a ground plane back to the source of the current. Current always takes the path that has the lowest “hurdle”. For pure DC current, for example, that hurdle is resistance. In contrast, RF current tends to take the least inductive path. At higher frequencies, RF return current path optimization plays a significant role in power amplifier performance. More specifically, the return current path for the power amplifier die should be relatively short (in electrical length) to avoid significant reductions in efficiency, gain, stability or other performance metrics. As will be described in detail below, various embodiments of power amplifier modules are disclosed herein, which have grounding structures that provide a suitable ground/return current path for a power amplifier die of a power amplifier module that is mounted to a system PCB in a flipped orientation, as described above.
The power amplifier module embodiments described herein may be utilized to implement any of a variety of different types of power amplifiers. To provide a concrete example that will help to convey the details of the inventive subject matter, an example of a Doherty power amplifier module is utilized herein. However, those of skill in the art will understand, based on the description herein, that the inventive subject matter may be utilized in power amplifier modules that implement other types of amplifiers, as well. Accordingly, the use of a Doherty power amplifier in the example embodiments below is not meant to limit application of the inventive subject matter only to Doherty power amplifier modules, as the inventive subject matter may be used in other types of power amplifier modules, as well.
Prior to describing various physical implementations of power amplifier modules, reference is made to
When incorporated into a larger RF system, the RF input node 112 is coupled to an RF signal source, and the RF output node 114 is coupled to a load 190 (e.g., an antenna or other load). The RF signal source provides an input RF signal, which is an analog signal that includes spectral energy that typically is centered around one or more carrier frequencies. Fundamentally, the Doherty amplifier 110 is configured to amplify the input RF signal, and to produce an amplified RF signal at the RF output node 114.
The power splitter 120 has an input 122 and two outputs 124, 126, in an embodiment. The power splitter input 122 is coupled to the RF input node 112 to receive the input RF signal. The power splitter 120 is configured to divide the RF input signal received at input 122 into first and second RF signals (or carrier and peaking signals), which are provided to the carrier and peaking amplifier paths 130, 150 through outputs 124, 126. According to an embodiment, the power splitter 120 includes a first phase shift element, which is configured to impart a first phase shift (e.g., about a 90 degree phase shift) to the peaking signal before it is provided to output 126. Accordingly, at outputs 124 and 126, the carrier and peaking signals may be about 90 degrees out of phase from each other.
When Doherty amplifier 110 has a symmetrical configuration (i.e., a configuration in which the carrier and peaking amplifier power transistors are substantially identical in size), the power splitter 120 may divide or split the input RF signal received at the input 122 into two signals that are very similar with, in some embodiments, equal power. Conversely, when Doherty amplifier 110 has an asymmetrical configuration (i.e., a configuration in which one of the amplifier power transistors, typically the peaking amplifier transistor, is significantly larger), the power splitter 120 may output carrier and peaking signals having unequal power.
The outputs 124, 126 of the power splitter 120 are connected to the carrier and peaking amplifier paths 130, 150, respectively. The carrier amplifier path 130 is configured to amplify the carrier signal from the power splitter 120, and to provide the amplified carrier signal to the power combining node 172. Similarly, the peaking amplifier path 150 is configured to amplify the peaking signal from the power splitter 120, and to provide the amplified peaking signal to the power combining node 172. The paths 130, 150 are designed so that the amplified carrier and peaking signals arrive in phase with each other at the power combining node 172.
According to an embodiment, the carrier amplifier path 130 includes an input circuit 131 (e.g., including an impedance matching circuit), a carrier amplifier 132 implemented using one or more carrier amplifier dies (e.g., dies 233, 234,
The carrier amplifier 132 includes an RF input terminal 135, an RF output terminal 138, and one or more amplification stages coupled between the input and output terminals 135, 138, in various embodiments. The RF input terminal 135 is coupled through input circuit 131 to the first output 124 of the power splitter 120, and thus the RF input terminal 135 receives the carrier signal produced by the power splitter 120.
Each amplification stage of the carrier amplifier 132 includes a power transistor. In a single-stage carrier amplifier 132, a single power transistor may be implemented on a single power amplifier die. In a two-stage carrier amplifier 132, two power transistors may be implemented on a single power amplifier die, or each power amplifier may be implemented on a separate die (e.g., dies 233, 234,
Either way, each power transistor includes a control terminal (e.g., a gate terminal) and first and second current-carrying terminals (e.g., a drain terminal and a source terminal). In a single-stage device, which would include a single power transistor, the control terminal is electrically connected to the RF input terminal 135, one of the current-carrying terminals (e.g., the drain terminal) is electrically connected to the RF output terminal 138, and the other current-carrying terminal (e.g., the source terminal) is electrically connected to a ground reference (or another voltage reference). Conversely, a two-stage amplifier would include two power transistors coupled in series, where a first transistor functions as a driver amplifier transistor that has a relatively low gain, and a second transistor functions as a final-stage amplifier transistor that has a relatively high gain. In such an embodiment, the control terminal of the driver amplifier transistor is electrically connected to the RF input terminal 135, one of the current-carrying terminals of the driver amplifier transistor (e.g., the drain terminal) may be electrically connected to the control terminal of the final-stage amplifier transistor, and the other current-carrying terminal of the driver amplifier transistor (e.g., the source terminal) is electrically connected through an embodiment of a specialized ground terminal 148 to the ground reference (or another voltage reference). Additionally, one of the current-carrying terminals of the final-stage amplifier transistor (e.g., the drain terminal) is electrically connected to the RF output terminal 138, and the other current-carrying terminal of the final-stage amplifier transistor (e.g., the source terminal) may be electrically connected through an embodiment of a specialized ground terminal 148 to the ground reference (or another voltage reference). As will be explained in more detail in conjunction with
In addition to the power transistor(s), portions of input and output impedance matching networks and bias circuitry (not illustrated in
The RF output terminal 138 of the carrier amplifier 132 is coupled to the power combining node 172 through phase shift and impedance inversion element 170, in an embodiment. According to an embodiment, the impedance inversion element is a lambda/4 (λ/4) transmission line phase shift element (e.g., a microstrip line), which imparts about a 90 degree relative phase shift to the carrier signal after amplification by the carrier amplifier 132. A first end of the impedance inversion element 170 is coupled to the RF output terminal 138 of the carrier amplifier 132, and a second end of the phase shift element 170 is coupled to the power combining node 172.
Reference is now made to the peaking amplifier path 150, which includes a peaking amplifier 152 and an input circuit 151 (e.g., including an impedance matching circuit), in an embodiment. The peaking amplifier 152 includes an RF input terminal 155, an RF output terminal 158, and one or more amplification stages coupled between the input and output terminals 155, 158, in various embodiments. The RF input terminal 155 is coupled to the second output 126 of the power splitter 120, and thus the RF input terminal 155 receives the peaking signal produced by the power splitter 120.
As with the carrier amplifier 132, each amplification stage of the peaking amplifier 152 includes a power transistor with a control terminal and first and second current-carrying terminals. The power transistor(s) of the peaking amplifier 152 may be electrically coupled between the RF input and output terminals 155, 158 in a manner similar to that described above in conjunction with the description of the carrier amplifier 132. Additional other details discussed with in conjunction with the description of the carrier amplifier 132 also apply to the peaking amplifier 152, and those additional details are not reiterated here for brevity. However, one important point to reiterate is that a current-carrying terminal of each peaking amplifier transistor (e.g., the source terminal of a driver and/or final-stage peaking amplifier transistor) may be electrically connected through an embodiment of a specialized ground terminal 148 to the ground reference (or another voltage reference), as described above in conjunction with the description of the carrier amplifier 132. As will be explained in more detail in conjunction with
The RF output terminal 158 of the peaking amplifier 152 is coupled to the power combining node 172. According to an embodiment, the RF output terminal 158 of the peaking amplifier 152 and the combining node 172 are implemented with a common element. More specifically, in an embodiment, the RF output terminal 158 of the peaking amplifier 152 is configured to function both as the combining node 172 and as the output terminal 158 of the peaking amplifier 152. To facilitate combination of the amplified carrier and peaking signals, and as mentioned above, the RF output terminal 158 (and thus the combining node 172) is connected to the second end of the phase shift and impedance inversion element 170. In other embodiments, the combining node 172 may be a separate element from the RF output terminal 158.
Either way, the amplified carrier and peaking RF signals combine in phase at the combining node 172. The combining node 172 is electrically coupled to the RF output node 114 to provide the amplified and combined RF output signal to the RF output node 114. In an embodiment, an output impedance matching network 174 between the combining node 172 and the RF output node 114 functions to present proper load impedances to each of the carrier and peaking amplifier 132, 152. The resulting amplified RF output signal is produced at RF output node 114, to which an output load 190 (e.g., an antenna) is connected.
Amplifier 110 is configured so that the carrier amplifier path 130 provides amplification for relatively low level input signals, and both amplification paths 130, 150 operate in combination to provide amplification for relatively high level input signals. This may be accomplished, for example, by biasing the carrier amplifier 132 so that the carrier amplifier 132 operates in a class AB mode, and biasing the peaking amplifier 152 so that the peaking amplifier 152 operates in a class C mode.
In the embodiment illustrated in
Power amplifier module 200 includes a module substrate 210 in the form of a multiple-layer printed circuit board (PCB) or other suitable substrate. The module substrate 210 has a top surface 209 (also referred to as a “mounting surface”) and a bottom surface 211 (also referred to as a “heat sink attachment surface”). As will be described in more detail below, a plurality of components and terminals are coupled to the mounting surface 209 of the module substrate 210, and non-conductive encapsulant material 380 (e.g., a plastic encapsulant) is disposed on the mounting surface 209 and over the components and terminals to define a top surface 382 (also referred to as a “contact surface”) of the module 200. As shown in
As depicted in
Each of the various conductive layers 301-304 may have a primary purpose, and also may include conductive features that facilitate signal and/or voltage/ground routing between other layers. Although the description below indicates a primary purpose for each of the conductive layers 301-304, it should be understood that the layers (or their functionality) may be arranged differently from the particular arrangement best illustrated in
For example, in an embodiment, the patterned conductive layer 301 at the mounting surface 209 of the module substrate 210 may primarily function as a signal conducting layer. More specifically, layer 301 includes a plurality of conductive features (e.g., conductive pads and traces) which serve as attachment points for various discrete components, and also provide electrical connectivity between the dies 233, 234, 253, 254 and the other discrete components. In addition, as will be discussed below, layer 301 may include a plurality of conductive pads that are specifically designated for attachment of electrically conductive signal and/or ground terminals, which will be described in more detail later.
A second patterned conductive layer 302 functions as an RF ground layer. The RF ground layer 302 also includes a plurality of conductive features (e.g., conductive traces), which may be electrically coupled to conductive features of the signal conducting layer 301 and to a system ground layer 304 (described below) with conductive vias (e.g., vias 311, 313) that extend through the dielectric layers 305-307. In addition, the RF ground layer 302 may contact thermal dissipation structures 316, described below.
A third patterned conductive layer 303 functions to convey bias voltages to power transistors 236, 237, 256, 257 within the dies 233, 234, 253, 254, and also may function as a routing layer, as mentioned above. Finally, a fourth conductive layer 304 functions as a system ground layer and also as a heat sink attachment layer, as will be explained in more detail in conjunction with
According to an embodiment, module substrate 210 also includes one or more thermal dissipation structures 316, which extend between the top and bottom surfaces 209, 211 of the module substrate 210. The dies 233, 234, 253, 254 are physically and electrically coupled to surfaces 317 of the thermal dissipation structures 316 that are exposed at the top surface 209 of the module substrate 210. The bottom surfaces 318 of the thermal dissipation structures 316 may be exposed at the bottom surface 211 of the module substrate 210, as shown in
In various embodiments, the thermal dissipation structures 316 may include electrically and thermally conductive metallic coins that are press-fit and/or attached into through-holes that extend between the surfaces 209, 211 of the module substrate 210. As will be described in more detail in conjunction with
According to various embodiments, electrically-conductive interior ground terminals 247 are connected directly to the upper surfaces 317 of the thermal dissipation structures 316. More specifically, lower or proximal surfaces of the interior ground terminals 247 are connected to the thermal dissipation structures 316, and upper or distal surfaces of the interior ground terminals 247 are exposed at the contact surface 382 of the module 200. The proximal surfaces of the interior ground terminals 247 may be attached to the thermal dissipation structures 316 using solder, conductive adhesive, sintering, brazing, or other suitable materials and methods.
Desirably, the interior ground terminals 247 are connected to the thermal dissipation structures 316 “in close proximity” to one or more sides of one or more of the power transistor dies 233, 234, 253, 254 (e.g., in close proximity to sides 334, 335, 354, 355 of dies 234, 254, as shown in
Although
According to a further embodiment, each of the interior ground terminals 247 may be embedded within a ground terminal interposer 248. Referring briefly to
When the via 495 has a square or circular cross-section, the via 495 may have a width 486 (or diameter) in a range of about 200 microns to about 800 microns (e.g., about 500 microns), although the width 486 may be smaller or larger, as well. The height 485 of the ground terminal interposer 248 may be in a range of about 500 microns to about 1500 microns (e.g., about 1000 microns), for example, although the ground terminal interposer 248 may be shorter or taller, as well. According to an embodiment, the height 485 of the ground terminal interposer 248 may be approximately equal to the thickness 384 of the encapsulant material 380 (
Referring again to
The RF signal input and output terminals 212, 214, along with additional peripheral ground terminals 262 and bias terminals (not numbered), are embedded within multi-terminal interposers 241, 242, 243, 244, 245, 246, in an embodiment. Each of the multi-terminal interposers 241-246 is similarly constructed to the example ground terminal interposer 248 shown in
As mentioned previously, the interior ground terminals 247 provide first electrically conductive paths (e.g., dashed-line path 387,
Including the interior ground terminals 247, in accordance with various embodiments, may provide several advantages, in comparison with modules that do not include such terminals. For example, the interior ground terminals 247 may enable a more even distribution of the ground currents from the transistors 233, 234, 253, 254. Further, the interior ground terminals 247 may eliminate electromagnetic (EM) feedback loops at certain frequencies. Directly coupling the interior ground terminals 247 to the thermal dissipation structures 316 also may reduce source inductance and allow for better EM isolation between the output, input, and interstages of the Doherty amplifier with little or no increase in layout space, since the interior ground terminals 247 may be placed in otherwise unused spaces on the thermal dissipation structures 316. Further still, reducing the length of the return current path may improve the small signal stability margin. This may be particularly beneficial during operation in low temperature environments in which the stability margin tends to worsen as the ambient temperature drops (e.g., below −40 degrees Celsius).
In the embodiment illustrated in
Terminal 212 functions as the RF signal input terminal for the module 200, and is coupled to an RF signal input pad at the top surface 209 of the module substrate 210 (e.g., a conductive pad formed from a portion of conductive layer 301). Through one or more conductive structures (e.g., traces and/or wirebonds, as shown), the RF signal input pad is electrically coupled to an input 222 to the power splitter 220. According to an embodiment, terminal 212 is embedded within terminal interposer 241, and additional ground terminals 262, 262 on either side of terminal 212 also are embedded within terminal interposer 241 in order to provide a GSG (ground-signal-ground) terminal structure 260.
The power splitter 220, which is coupled to the mounting surface 209 of the system substrate 210, may include one or more discrete die and/or components, although it is represented in
The power splitter 220 is configured to split the power of the input RF signal received through the RF input terminal 212 into first and second RF signals, which are produced at the output terminals of the power splitter 220. In addition, the power splitter 220 may include one or more phase shift elements configured to impart about a 90 degree phase difference between the RF signals provided at the splitter output terminals. The first and second RF signals produced at the outputs of the power splitter 220 may have equal or unequal power, as described previously.
The first output of the power splitter is electrically coupled to a carrier amplifier path (i.e., to the carrier amplifier 232), and the second output of the power splitter is electrically coupled to a peaking amplifier path (i.e., to the peaking amplifier 252). The RF signal produced at the second power splitter output may be delayed by about 90 degrees from the RF signal produced at the first power splitter output. In other words, the RF signal provided to the peaking amplifier path may be delayed by about 90 degrees from the RF signal provided to the carrier amplifier path. In any event, the first RF signal produced by the power splitter 220 is amplified through the carrier amplifier path 232, and the second RF signal produced by the power splitter 220 is amplified through the peaking amplifier path 252.
In the specific embodiment of
The carrier amplifier 232 more specifically includes a silicon driver stage die 233 and a gallium nitride (GaN) final-stage die 234, and the peaking amplifier 252 also includes a silicon driver stage die 253 and a GaN final-stage die 254, in accordance with an example embodiment. In other embodiments, each of the carrier and peaking amplifiers 232, 252 may include a two-stage power amplifier implemented on a single die, or each of the carrier and peaking amplifiers 232, 252 may include a single-stage power amplifier implemented on a single die. In still other embodiments, each of the carrier and peaking amplifiers may include a two-stage power amplifier implemented on separate driver and final-stage dies, but the driver and final-stage dies may be formed using the same semiconductor technology (e.g., both the driver and final-stage dies are silicon dies or GaN dies), or the driver and/or final-stage dies may be formed using different semiconductor technologies than those described above (e.g., the driver and/or final-stage dies may be formed from silicon germanium (SiGe) and/or gallium arsenide (GaAs)).
The carrier amplifier path includes the above-mentioned driver stage die 233, the final-stage die 234, and a phase shift and impedance inversion element 270 (e.g., element 170,
The driver stage die 233 includes a plurality of integrated circuits. In an embodiment, the integrated circuitry of die 233 includes a series-coupled arrangement of the input terminal 235 (e.g., input terminal 135,
The output terminal of the driver stage die 233 is electrically coupled to the input terminal of the final-stage die 234 through a wirebond array (not numbered) or another type of electrical connection. The final-stage die 234 also includes a plurality of integrated circuits. In an embodiment, the integrated circuitry of die 234 includes a series-coupled arrangement of an input terminal (not numbered), a GaN power transistor 237, and an output terminal 238 (e.g., output terminal 138,
The peaking amplifier path includes the above-mentioned driver stage die 253 and the final-stage die 254. The driver stage die 253 and the final-stage die 254 of the peaking amplifier path 252 are electrically coupled together in a cascade arrangement between an input terminal 255 of the driver stage die 253 (corresponding to a peaking amplifier input) and an output terminal 258 of the final-stage die 254 (corresponding to a peaking amplifier output).
The driver stage die 253 includes a plurality of integrated circuits. In an embodiment, the integrated circuitry of die 253 includes a series-coupled arrangement of the input terminal 255 (e.g., input terminal 155,
The output terminal of the driver stage die 253 is electrically coupled to the input terminal of the final-stage die 254 through a wirebond array (not numbered) or another type of electrical connection. The final-stage die 254 also includes a plurality of integrated circuits. In an embodiment, the integrated circuitry of die 254 includes a series-coupled arrangement of an input terminal (not numbered), a GaN power transistor 257, and an output terminal 258 (e.g., output terminal 158,
An amplified carrier signal is produced at the output terminal 238 of the final-stage die 234, and an amplified peaking signal is produced at the output terminal 258 of the final-stage die 254, which also functions as the combining node 272 (e.g., node 172,
According to an embodiment, the phase shift and impedance inversion element 270 may be implemented with a quarter-wavelength or lambda/4 (λ/4) or shorter transmission line (e.g., a microstrip transmission line with an electrical length up to about 90 degrees) that is formed from a portion of the conductive layer 301. As used herein, lambda is the wavelength of an RF signal at the fundamental frequency of operation of the amplifier (e.g., a frequency in a range of about 600 megahertz (MHz) to about 10 gigahertz (GHz) or higher). The combination of the phase shift and impedance inversion element 270 and the wirebond (or other) connections to the output terminals 238, 258 of dies 234, 254 may impart about a 90 degree relative phase shift to the amplified carrier signal as the signal travels from output terminal 238 to output terminal 258/combining node 272. When the various phase shifts imparted separately on the carrier and peaking RF signals through the carrier and peaking paths, respectively, are substantially equal, the amplified carrier and peaking RF signals combine substantially in phase at output terminal 258/combining node 272.
The output terminal 258/combining node 272 is electrically coupled (e.g., through wirebonds or another type of electrical connection) through an output impedance matching network 274 (e.g., network 174,
To incorporate embodiments of power amplifier module 200 into a larger electrical system, the terminals at the contact surface 382 of the power amplifier module 200 are physically and electrically coupled to a system substrate, and a heat sink is attached to the opposite surface of the power amplifier module 200. To illustrate the integration of power amplifier module 200 into such a system, reference is now made to
The RF system 700 generally includes a system substrate 710, power amplifier module 200 (or module 200′), and a heat sink 716. According to an embodiment, the system substrate 710 includes a multi-layer printed circuit board (PCB) or other suitable substrate. The system substrate 710 has a top surface 709 (also referred to as a “mounting surface”), an opposed bottom surface 711. As depicted in
Each of the various conductive layers 701-704 may have a primary purpose, and also may include conductive features that facilitate signal and/or voltage/ground routing between other layers. Although the description below indicates a primary purpose for some of the conductive layers 701-704, it should be understood that the layers (or their functionality) may be arranged differently from the particular arrangement best illustrated in
For example, in an embodiment, the patterned conductive layer 701 at the mounting surface 709 of the system substrate 710 may primarily function as a signal conducting layer and an attachment layer for the interior and peripheral ground terminals 247, 262. More specifically, layer 701 includes a plurality of conductive features (e.g., conductive pads and traces) which serve as attachment points for module 200, an input RF connector 791, and an output RF connector 792. Each of RF connectors 791, 792 may, for example, be coaxial connectors with a central signal conductor 793 and an outer ground shield 794. According to an embodiment, the signal conductor 793 of RF input connector 791 is electrically coupled to a first conductive trace 712 of layer 701, which in turn is coupled to input terminal 212 of module 200. In addition, the signal conductor 793 of RF output connector 792 is electrically coupled to a second conductive trace 714 of layer 701, which in turn is coupled to an output terminal (e.g., terminal 214,
As just indicated, conductive layer 704 functions as a system ground layer. In addition to being electrically coupled to the ground shields 794 of connectors 791, 792, the system ground layer 704 also is electrically coupled through additional conductive vias 796 to an additional ground pad 741 on the mounting surface 709. As will be described in more detail below, the additional ground pad 741 is physically and electrically coupled to the various ground terminals (e.g., terminals 247, 262) of module 200. System substrate 710 configures system 700 as a “closed ground” system, in that the ground pad 741 and the system ground layer 704 each comprises a continuous, solid conductive layer. The ground pad 741 is a solid conductive layer with a rectangular perimeter that encompasses all of the interior ground terminals 247. The ground pad 741 also may have extensions, as shown in
Module 200 (or module 200′) is coupled to the mounting surface 709 of system substrate 710 in an inverted (or “flipped”) orientation from the orientations depicted in
According to an embodiment, a heat sink 716 is physically and thermally coupled to the heat sink attachment surface 211 of the power amplifier module 200, and more specifically to conductive layer 304 and/or the surfaces 318 of the embedded heat dissipation structures 316 of module 200. The heat sink 716 is formed from a thermally-conductive material, which also may be electrically-conductive. For example, the heat sink 716 may be formed from copper or another bulk conductive material. To couple the heat sink 716 to the power amplifier module 200, a thermally conductive material 798 (e.g., thermal grease) may be dispensed on the heat sink attachment surface 211 of the module 200 (and/or on the surfaces 318 of the heat dissipation structures 316) and/or the heat sink 716, and the heat sink 716 may be brought into contact with the heat sink attachment surface 211. The heat sink 716 may then be clamped, screwed, or otherwise secured in place.
During operation of RF system 700, input RF signals are provided through the RF input terminal 791 and trace/pad 712 to an RF input terminal 212 (
According to an embodiment, a ground path is provided between each of the power transistor dies 233, 234, 253, 254 and the system ground layer 704. For example, for dies 234, 254 shown in
As discussed in detail previously, the interior ground terminals 247 (or 247′) of the module 200 (or module 200′) are connected to the thermal dissipation structures 316 in close proximity to the power transistor dies 233, 234, 253, 254, which results in a relatively short ground return path for the module 200. Desirably, the entire electrical length of the ground path between the ground contact 336 for each die 233, 234, 253, 254 and the system ground layer 704 is less than about lambda/5 (λ/5), in some embodiments, or less than about lambda/16 (λ/16), in other embodiments.
During operation, significant thermal energy (heat) may be produced by the power transistor(s) within the power transistor dies 233, 234, 253, 254. As indicated by arrows 799, the thermal energy produced by the power transistor(s) is conveyed through the thermal dissipation structures 316 to the heat sink 716, which effectively dissipates the heat to the ambient atmosphere. Accordingly, the thermal dissipation structures 316 provides two functions: 1) the function of conveying heat produced by the power transistor dies 233, 234, 253, 254 to the heat sink 716; and 2) the function of electrically coupling the ground contacts 336 of the dies 233, 234, 253, 254 to system ground.
In block 906, the module substrate, terminals, dies, and other components are encapsulated (e.g., with encapsulant material 380,
Finally, in block 910, a heat sink (e.g., heat sink 716,
An embodiment of an amplifier module includes a module substrate, a thermal dissipation structure, a power transistor die, encapsulant material, and an interior ground terminal. The thermal dissipation structure extends through the module substrate. The thermal dissipation structure has a first surface and a second surface, and the first surface is exposed at a mounting surface of the module substrate. The power transistor die has a ground contact, which is coupled to the first surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. The interior ground terminal is embedded within the encapsulant material, and the interior ground terminal has a proximal end connected to the thermal dissipation structure, and a distal end exposed at the contact surface. The interior ground terminal is electrically coupled to the ground contact of the power transistor die through the thermal dissipation structure.
An embodiment of an amplifier system includes a system substrate and an amplifier module. The system substrate has a mounting surface, a first signal conducting layer, a first ground layer, and a ground pad at the first mounting surface. The ground pad is electrically coupled to the first ground layer. The amplifier module has a contact surface and a heat sink attachment surface, and the amplifier module is coupled to the system substrate with the mounting surface of the system substrate facing the contact surface of the amplifier module. The amplifier module further includes a module substrate, a thermal dissipation structure, a power transistor die, encapsulant material, and an interior ground terminal. The thermal dissipation structure extends through the module substrate. The thermal dissipation structure has a first surface and a second surface, and the first surface is exposed at the mounting surface of the module substrate. The power transistor die has a ground contact, which is coupled to the first surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines the contact surface of the amplifier module. The interior ground terminal is embedded within the encapsulant material, and the interior ground terminal has a proximal end connected to the thermal dissipation structure, and a distal end exposed at the contact surface. The interior ground terminal is electrically coupled to the ground contact of the power transistor die through the thermal dissipation structure.
An embodiment of a method of fabricating a power amplifier includes coupling a power transistor die to a thermal dissipation structure that extends through a module substrate, where the module substrate has a mounting surface, a first surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate, and the power transistor die has a ground contact that is connected to the first surface of the thermal dissipation structure. The method further includes coupling a proximal end of an interior ground terminal to the thermal dissipation structure, and covering the mounting surface of the module substrate and the power transistor die with an encapsulant material to form an amplifier module. A surface of the encapsulant material defines a contact surface of the amplifier module, a distal end of the interior ground terminal is exposed at the contact surface, and the interior ground terminal is electrically coupled to the ground contact of the power transistor die through the thermal dissipation structure.
The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.
The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).
The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
