Patent Grant
7915718
This application is related to U.S. patent application Ser. No. 09/944,465 filed Aug. 30, 2001, now U.S. Pat. No. 6,756,251, issued Jun. 29, 2004, and entitled MICROELECTRONIC DEVICES AND METHODS OF MANUFACTURE, and to the following U.S. patent applications filed on even date herewith: Ser. No. 10/150,893, now U.S. Pat. No. 7,145,225, issued Dec. 5, 2006, entitled INTERPOSER CONFIGURED TO REDUCE THE PROFILES OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING THE SAME AND METHODS; Ser. No. 10/150,516, now U.S. Pat. No. 7,112,520, issued Sep. 26, 2006, entitled SEMICONDUCTOR DIE PACKAGES WITH RECESSED INTERCONNECTING STRUCTURES AND METHODS FOR ASSEMBLING THE SAME; Ser. No. 10/150,653, now U.S. Pat. No. 7,161,237, issued Jan. 9, 2007, entitled FLIP CHIP PACKAGING USING RECESSED INTERPOSER TERMINALS; Ser. No. 10/150,902, now U.S. Pat. No. 6,975,035, issued Dec. 13, 2005, entitled METHOD AND APPARATUS FOR DIELECTRIC FILLING OF FLIP CHIP ON INTERPOSER ASSEMBLY; and Ser. No. 10/150,901, now U.S. Pat. No. 7,348,215, issued Mar. 25, 2008, entitled METHODS FOR ASSEMBLY AND PACKAGING OF FLIP CHIP CONFIGURED DICE WITH INTERPOSER. This application is also related to U.S. patent application Ser. No. 10/710,229, filed Jun. 28, 2004, now U.S. Pat. No. 7,087,994, issued Aug. 8, 2006; U.S. patent application Ser. No. 11/501,600, filed Aug. 8, 2006, now abandoned; U.S. patent application Ser. No. 11/398,912, filed Apr. 6, 2006, pending; U.S. patent application Ser. No. 10/933,060, filed Sep. 1, 2004, now U.S. Pat. No. 7,230,330, issued Jun. 12, 2007; U.S. patent application Ser. No. 11/760,458, filed Jun. 8, 2007; now U.S. Pat. No. 7,569,473, issued Aug. 4, 2009; U.S. patent application Ser. No. 11/505,759, filed Aug. 16, 2006, now U.S. Pat. No. 7,531,906, issued May 12, 2009; U.S. patent application Ser. No. 10/782,270, filed Feb. 18, 2004, now U.S. Pat. No. 7,122,907, issued Oct. 17, 2006; U.S. patent application Ser. No. 10/829,647, filed Apr. 22, 2004, now U.S. Pat. No. 7,534,660, issued May 19, 2009 and U.S. patent application Ser. No. 10/829,603, filed Apr. 22, 2004, now U.S. Pat. No. 7,087,460, issued Aug. 8, 2006.
1. Field of the Invention
The present invention relates generally to packaging of semiconductor dice and, more specifically, to packaging of flip-chip configured semiconductor dice employing an interposer substrate having recesses in one or both sides thereof for receiving discrete conductive elements projecting from the semiconductor dice.
2. State of the Art
Chip-On-Board (“COB”) or Board-On-Chip (“BOC”) technology is used to attach a semiconductor die directly to a carrier substrate such as a printed circuit board (“PCB”), or an interposer may be employed and attachment may be effected using flip-chip attachment, wire bonding, or tape automated bonding (“TAB”).
Flip-chip attachment generally includes electrically and mechanically attaching a semiconductor die by its active surface to an interposer or other carrier substrate using a pattern of discrete conductive elements therebetween. The discrete conductive elements are generally disposed on the active surface of the die during fabrication thereof, but may instead be disposed on the carrier substrate. The discrete conductive elements may comprise minute conductive bumps, balls or columns of various configurations. Each discrete conductive element is placed corresponding to mutually aligned locations of bond pads (or other I/O locations) on the semiconductor die and terminals on the carrier substrate when the two components are superimposed. The semiconductor die is thus electrically and mechanically connected to the carrier substrate by, for example, reflowing conductive bumps of solder or curing conductive or conductor-filled epoxy bumps. A dielectric underfill may then be disposed between the die and the carrier substrate for environmental protection and to enhance the mechanical attachment of the die to the carrier substrate.
Wire bonding and TAB attachment techniques generally begin with attaching a semiconductor die by its back side to the surface of a carrier substrate with an appropriate adhesive, such as an epoxy or silver solder. In wire bonding, a plurality of fine wires is discretely attached to bond pads on the semiconductor die and then extended and bonded to corresponding terminal pads on the carrier substrate. A dielectric encapsulant such as a silicone or epoxy may then be applied to protect the fine wires and bond sites. In TAB, ends of metal traces carried on a flexible insulating tape such as a polyimide are attached, as by thermocompression bonding, directly to the bond pads on the semiconductor die and corresponding terminal pads on the carrier substrate.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of components used to fabricate them tends to decrease due to advances in technology even though the functionality of the products increase. For example, on the average, there is approximately a ten percent decrease in components for every product generation over the previous generation having equivalent functionality.
Recent trends in packaging are moving with increasing rapidity toward flip-chip attachment due to improved electrical performance and greater packaging density. However, flip-chip attachment is not without problems, such as the high cost for a third metal reroute of bond pads from the middle or periphery of a die to a two-dimensional array which, in turn, may result in overlong and unequal length electrical paths. In addition, many conventional flip-chip techniques exhibit a lack of consistent reliability of the interconnections between the chip and the interposer or other carrier substrate as a result of the increased miniaturization as well as difficulties in mutual alignment of the die and carrier substrate to effect such interconnections. Effective rerouting of bond pads may also be limited by die size. Another hindrance to flip-chip packaging has been difficulty in electrically testing completed flip-chip semiconductor device assemblies using existing test probe equipment. Thus, even if a semiconductor die in the assembly is a so-called “known good die,” the assembly itself may exhibit defects that are not easily detected and that may, even if detected, be at a stage in the fabrication process subsequent to encapsulation, rendering rework of the assembly difficult if not impossible.
Further, flip-chip packages for a bumped semiconductor die employing an interposer may be undesirably thick due to the combined height of the die and interposer. This is due to the use in conventional packaging techniques of relatively costly interposers comprising dual conductive layers having a dielectric member sandwiched therebetween, the bumped semiconductor die resting on and connected to traces of the conductive layer on one side of the interposer and electrically connected to traces of the conductive layer on the opposing side, conductive vias extending therebetween. Finally, underfilling a flip-chip-attached semiconductor die to a carrier substrate with dielectric filler material can be a lengthy and often unreliable process, and the presence of the underfill makes reworking of defective assemblies difficult if not impossible.
Other difficulties with conventional packages include an inability to accommodate die size reductions, or “shrinks,” as a given design progresses through several generations without developing new interposer designs and tooling. As more functionality is included in dice, necessitating a greater number of inputs and outputs (I/Os), decreased spacing or pitch between the I/Os places severe limitations on the use of conventional interposers. In addition, with conventional packages, a die is not tested until package assembly is complete, resulting in excess cost since a defective die or die and interposer assembly is not detected until the package is finished.
For example, U.S. Pat. No. 5,710,071 to Beddingfield et al. discloses a fairly typical flip-chip attachment of a semiconductor die to a substrate and a method of underfilling a gap between the semiconductor die and substrate. In particular, the semiconductor die is attached face down to the substrate, wherein conductive bumps on the die are directly bonded to bond pads on the upper surface of the substrate, which provides the gap between the die and substrate. The underfill material flows through the gap between the semiconductor die and the substrate via capillary action toward an aperture in the substrate, thereby expelling air in the gap through the aperture in the substrate in an effort to minimize voids in the underfill material. However, such an underfilling method still is unnecessarily time consuming due to having to underfill the entire semiconductor die. Further, the flip-chip attachment technique disclosed in U.S. Pat. No. 5,710,071 exhibits difficulties in aligning the conductive bumps with the bond pads on the substrate and requires the expense of having a third metal reroute in the substrate.
Therefore, it would be advantageous to improve the reliability of interconnections between a chip and a carrier substrate such as an interposer by achieving accurate alignment of the interconnections, an improved underfill process, and the elimination of the necessity for a third metal reroute, while reducing total assembly height in combination with the ability to employ commercially available, widely practiced semiconductor device fabrication techniques and materials as well as existing test equipment.
The present invention relates to methods and apparatus for assembling, testing and packaging individual and multiple semiconductor dice with an interposer substrate in a flip-chip-type arrangement and, further, the present invention relates to an interposer substrate having multiple recess patterns for mounting semiconductor dice with differently spaced and sized conductive bump configurations. The present invention provides a flip-chip semiconductor device assembly substantially reduced in height or thickness and with improved mechanical and electrical reliability of the interconnections between a semiconductor die and a carrier substrate in comparison to conventional flip-chip assemblies, while also improving the alignment capability of attaching the semiconductor die to the interposer substrate. The present invention also eliminates the requirement of a third metal reroute necessitated in most flip-chip assemblies and eliminates the need for underfilling or reduces the time for underfilling if optionally effected. In addition, the present invention facilitates relatively simple and efficient testing of the semiconductor assembly.
The flip-chip semiconductor device assembly of the present invention includes an interposer substrate having a first surface and a second surface, wherein at least one of the first surface and the second surface includes multiple recesses formed therein and arranged in at least two different recess patterns for attaching one or more conductively bumped semiconductor dice thereto. The one or more conductively bumped semiconductor dice may be assembled face (or active surface) down to the interposer substrate in a flip-chip-type arrangement so that the conductive bumps of the semiconductor die or dice are disposed in a corresponding recess pattern. Conductive elements in the recesses are interconnected by traces to test pads that are exposed proximate a periphery on at least one of the first and second surfaces of the interposer substrate. Such test pads allow easy access for probe testing the electrical integrity of the one or more semiconductor dice mounted to the interposer substrate.
In this manner, the recesses of the at least two different recess patterns are spaced, sized and configured to substantially receive the conductive bumps on the conductively bumped semiconductor die or dice to an extent so that an active surface of each semiconductor die lies immediately adjacent a surface of the interposer substrate. An adhesive element in the form of a liquid or gel adhesive or an adhesive-coated tape may optionally be disposed between the semiconductor die and adjacent interposer substrate surface. As such, there is a reduction in the height of the flip-chip assembly due to the conductive bumps being substantially or even completely received in the recesses, which allows for the conductive bumps on the die to be formed larger for increased reliability without increasing the height of the flip-chip assembly while also removing the need for a third metal reroute on the semiconductor die. Furthermore, such a flip-chip semiconductor device assembly may eliminate the need for underfilling between a semiconductor die and the interposer substrate. If underfilling is employed, the present invention reduces the time for underfilling the assembly and amount of dielectric filler required, since any space in a recess proximate a conductive bump is minimal and vertical space, or standoff, between the semiconductor die and adjacent interposer substrate surface is at least reduced and, in some instances, greatly reduced due to the presence of the adhesive element.
In a first embodiment, the interposer substrate includes multiple recesses formed in a first recess pattern on the first surface thereof and a second recess pattern on the second surface thereof. The first and second recess patterns are configured such that semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized semiconductor dice) may each be mounted to the interposer substrate. In this manner, the interposer substrate of the first embodiment may facilitate mounting two semiconductor dice thereto by mounting a first die on the first surface of the interposer substrate and mounting a second die on the second surface of the interposer substrate.
In a second embodiment, the interposer substrate includes multiple recesses formed in a first recess pattern and a second, different recess pattern in the first surface thereof. Such first and second recess patterns enable semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized dice) to be alternatively mounted to a first surface of the interposer substrate. In this manner, the interposer substrate of the second embodiment facilitates the option of mounting differently sized dice and/or semiconductor dice having differently spaced conductive bump configurations.
In a third embodiment, the interposer substrate includes multiple recesses formed in a first recess pattern and a second, different recess pattern on the first surface of the interposer substrate and a third recess pattern and a fourth, different recess pattern on the second surface of the interposer substrate. The first and second recess patterns are configured so that semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized semiconductor dice) may be optionally mounted to a first surface of the interposer substrate and the third and fourth recess patterns are configured so that semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized semiconductor dice) may be optionally mounted to a second surface of the interposer substrate. In this manner, the interposer substrate of the third embodiment facilitates the option of mounting differently sized dice and/or semiconductor dice having differently spaced conductive bump configurations on both the first surface and the second surface of the interposer substrate.
In a fourth embodiment, the interposer substrate includes multiple recesses formed in first, second, third and fourth different recess patterns in the first surface of the interposer substrate. Such recess patterns each are configured and sized so that semiconductor dice having differently spaced conductive bump configurations thereon (including differently sized semiconductor dice) may be optionally mounted to a first surface of the interposer substrate. Thus, the interposer substrate of the fourth embodiment facilitates the option of mounting differently sized dice and/or semiconductor dice having differently spaced conductive bump configurations on the first surface of the interposer substrate.
The recess patterns referred to in the interposer substrate of the previous embodiments may be staggered and/or aligned with respect to each other. Also, the recess patterns may include some recess patterns that are staggered with respect to each other and some recess patterns that are aligned with respect to each other.
Turning to another aspect of the present invention, the conductive bumps utilized for interconnecting the semiconductor die and the interposer substrate may be bonded to conductive elements in the recesses by reflowing the conductive bumps, curing the conductive bumps, ultrasonic bonding, or thermal compression, depending upon the bump material employed. In addition, nonsolid conductive material such as a conductive paste may be provided on the conductive bumps or within the recesses prior to disposing the conductive bumps in the recesses. Alternatively, unattached conductive bumps may be provided in the conductive paste in the recesses, after which, the die may be aligned and attached to the conductive bumps. As such, in addition to providing a more reliable electrical connection between the conductive bumps and the conductive interconnect, the conductive paste compensates for any noncoplanarity due to various conductive bump sizes, recess depths and planarity variation in the surfaces of the semiconductor die and interposer substrate. The adhesive element, as previously mentioned, on the first surface and/or the second surface of the interposer substrate may also compensate and act as a height controller for any irregularities in the coplanarity between a semiconductor die and the interposer substrate.
The flip-chip semiconductor device assembly of the present invention may also include relatively large solder balls or other conductive elements attached to a surface of the interposer substrate, interconnecting with the conductive elements and the conductive bumps of the semiconductor die. The solder balls act as interconnects to another substrate, such as a printed circuit board. The flip-chip semiconductor device assembly may also be fully or partially encapsulated by an encapsulation material or the semiconductor die or dice may be left exposed.
The flip-chip semiconductor device assembly of the present invention may also be assembled at a wafer level, wherein a wafer scale interposer substrate includes at least two different recess patterns. As such, the wafer scale interposer substrate may facilitate assembly with different wafers having different conductive bump configurations, which correspond with the at least two different recess patterns in the wafer scale interposer substrate. In this manner, optional wafers with different conductive bump configurations may be attached face down to the interposer substrate with conductive bumps on the wafer disposed and submerged in recesses formed in the wafer scale interposer substrate. The wafer and wafer scale interposer substrate may then be singulated or diced into individual flip-chip semiconductor device assemblies. Partial encapsulation of these assemblies may be performed at the wafer level and optionally completed subsequent to being diced into individual flip-chip semiconductor device assemblies.
The interposer substrate may be fabricated from a flexible, tape-like material including at least one flexible dielectric member and at least one conductive member laminated thereto. The at least one flexible dielectric member may include a polyimide layer. The at least one conductive member is patterned into traces by etching or printing conductive ink and may include conductive elements at recess locations in the form of conductive pads linked by the conductive traces to test pads and other conductive pads for external connection of the assembly to other like assemblies or to higher-level packaging. The multiple recesses are formed in at least one of the first and second surfaces of the at least one flexible dielectric member by etching, mechanical drilling or punching or laser ablation, wherein each of the recesses extends at least to a portion of a conductive element and is sized and configured to receive the conductive bumps on the semiconductor die. The interposer substrate of the present invention may also be formed of other interposer substrate materials, including nonflexible materials, such as a BT resin, FR4, FR5 and ceramics.
The interposer substrate may comprise a single flexible dielectric member having conductive layers comprising conductive traces on opposing sides thereof or may comprise a single conductive layer laminated between two dielectric members. In either instance, recesses may extend from either side of the interposer substrate through a dielectric member to expose portions of conductive elements.
In another aspect of the present invention, the flip-chip semiconductor device assembly is mounted to a circuit board in a computer or a computer system. In the computer system, the circuit board is electrically connected to a processor device that electrically communicates with an input device and an output device.
Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings and the appended claims.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention may be ascertained from the following description of the invention when read in conjunction with the accompanying drawings, wherein:
Embodiments of the present invention will be hereinafter described with reference to the accompanying drawings. It would be understood that these illustrations are not to be taken as actual views of any specific apparatus or method of the present invention, but are merely exemplary, idealized representations employed to more clearly and fully depict the present invention than might otherwise be possible. Additionally, elements and features common between the drawing figures retain the same numerical designation.
Interposer substrate 110 is preferably, but not limited to, a flexible substrate, wherein interposer substrate 110 may include a dielectric member 136 disposed between conductive layers, each comprising a plurality of conductive elements configured as traces 130. The dielectric member 136 may be formed from any known substrate material and is preferably formed of, by way of example, a flexible laminated polymer or polyimide layer, such as UPILEX®, produced by Ube Industries, Ltd., or any other polymer-type layer. The interposer substrate 110 may also be made of a bismaleimide triazine (BT) resin, FR 4, FR 5 or any type of substantially flexible material or nonflexible material, such as a ceramic or epoxy resin.
The conductive layers are preferably formed of copper, or a copper alloy, but may be any suitable electrically conductive material. The conductive layers may include traces 130 extending to conductive pads 132 for connection to conductive bumps of a semiconductor die and conductive pads 133 for use in externally connecting the interposer substrate 110 and test pads 134 for electrical testing of the interposer substrate 110 with one or more semiconductor dice connected thereto. Such traces 130 may be formed subtractively as by masking and etching a conductive layer, additively by printing with conductive ink, or by utilizing any suitable method known in the art. Once the traces 130 are patterned, a protective solder mask 138 may be formed and patterned over the traces 130, leaving conductive pads 133 exposed for formation of conductive bumps such as solder balls thereon. As implied above, the conductive traces, which may, for example, comprise copper or a copper alloy, may be adhered to the dielectric substrate member of UPILEX®, BT resin, FR 4 or, FR 5 laminate material, or other substrate materials, using adhesives as known in the art.
According to the first embodiment of the present invention, the first surface 112 and the second surface 114 of interposer substrate 110 each include multiple recesses 120 or vias formed therein in a preselected pattern and a predetermined sizing. Such recesses 120 may be formed by patterning, utilizing a chemical wet etch or dry etch, mechanical drilling or punching, laser ablation, or any method known in the art and suitable with the type of materials employed for the interposer substrate 110. Optionally, the recesses 120 are preferably formed to expose at least portions of conductive pads 132 of the traces 130, which may, in some instances, comprise the trace ends. It is also contemplated that electroless plating may, optionally, be formed on walls of the recesses 120.
In this manner, each of the multiple recesses 120 extends to a conductive layer, or more specifically, to the traces 130 or conductive pads 132 defining the conductive layer. The conductive traces 130, conductive pads 132 and conductive pads 133 of a conductive layer on the first surface 112 may be interconnected through dielectric member 136 of interposer substrate 110 to other conductive traces 130, conductive pads 132 or conductive pads 133 on the second surface 114 of interposer substrate 110 by conductively plated vias 135, as known in the art. Such conductive pads 133 may be located substantially directly below conductive pads 132 or, optionally, the conductive pads 133 may be at various predetermined locations remote from conductive pads 132 and connected thereto by the conductive traces 130. The conductive traces 130 also extend to test pads 134 proximate the periphery 116 of the interposer substrate 110, test pads 134 being located on one or both surfaces 112 and 114 of interposer substrate 110, as desired. It will be understood that elements of the conductive layer on one side of dielectric member 136 will be offset from those on the other side thereof in the areas wherein recesses 120 are formed through dielectric member 136.
Each plurality of recesses 120 in the first surface 112 and the second surface 114 of interposer substrate 110 is formed in a preselected pattern to correspond with a particular bond pad configuration formed on an active surface of a semiconductor die for attaching thereto. In particular, the recesses 120 in
Referring to
Conductive bumps 166 and 176 preferably comprise, but are not limited to, conductive balls, pillars or columns. The material of conductive bumps 166 and 176 may include, but is not limited to, any known suitable metals or alloys thereof, such as lead, tin, copper, silver or gold. Conductive or conductor-filled polymers may also be employed, although gold and PbSn solder bumps are currently preferred. The conductive bumps 166 and 176 may be of uniform characteristics throughout or include, for example, a core of a first material (including a nonconductive material) having one or more conductive layers of other materials thereon. Conductive bumps 166 and 176 are preferably formed on the active surface of each semiconductor die at a wafer level, but such is not required. Conductive bumps 166 and 176 may be formed by metal evaporation, electroplating, stencil printing, gold stud bumping by wire bonders, solder reflow or any suitable method known in the art depending, of course, on the material or materials selected for formation thereof.
As depicted in
To assist in mounting and bonding the first and second semiconductor dice 160 and 170 to the interposer substrate 110, a nonsolid conductive material in the form of a conductive paste 156 may be provided in the recesses 120 as depicted in
In another method, the conductive paste 156 may first be disposed on the conductive bumps 166 and 176 prior to assembling the respective first and second semiconductor dice 160 and 170 to the interposer substrate 110 by dipping the conductive bumps 166 and 176 in a pool of conductive paste 156 or by depositing, dispensing or otherwise transferring the conductive paste to the conductive bumps 166 and 176. In still another approach, conductive bumps such as bumps 166 or 176, unattached to a semiconductor die, may be disposed in the conductive paste 156, which is in the recesses 120 corresponding to a particular recess pattern. A semiconductor die having a bond pad configuration with a substantially mirror image of the particular recess pattern may then be aligned with and bonded to the conductive bumps.
If employed, the conductive paste 156 supplements the conductive bumps 166 and 176 in electrical and mechanical interconnection between both the first and second semiconductor dice 160 and 170 and the traces 130 of interposer substrate 110. Further, the conductive paste 156 ensures mechanical and electrical interconnection even if some of the conductive bumps 166 and 176 are inconsistent in height or the recesses 120 are inconsistent in depth, i.e., noncoplanar, wherein the conductive paste 156 is disposed in the recesses 120 between the conductive pads 132 and the conductive bumps 166 and 176. The conductive bumps 166 and 176 and the conductive paste 156 may then be bonded to the conductive pads 132 or trace ends in the recesses 120 of interposer substrate 110 as previously described.
It will be well appreciated by one skilled in the art that, since the conductive bumps 166 and 176 are substantially received within the recesses 120 of the interposer substrate 110 itself when bonded to conductive pads 132, the height of the semiconductor device assembly 180 is minimized. Therefore, the conductive bumps 166 and 176 may be formed of a larger size than in conventional flip-chip assemblies without increasing the height of the flip-chip semiconductor device assembly 180, resulting in an increase of the electrical and mechanical reliability and performance of the interconnections between the interposer substrate 110 and the first and second semiconductor dice 160 and 170. In addition, the first and second adhesive elements 152 and 154 (if used) on the respective first and second surfaces 112 and 114 of the interposer substrate 110 as well as the conductive paste 156 in the recesses 120 (if used) may compensate for any irregularities due to various conductive bump sizes, recess depths and planarity variation in the surfaces of the interposer substrate 110 and the first semiconductor die 160 and second semiconductor die 170.
Further, the recesses 120 in the interposer substrate 110 provide an inherent improved alignment capability in comparison to a conventional flip-chip-type semiconductor device assembly because the conductive bumps 166 and 176 easily slide into their respective corresponding recesses 120 to ensure proper alignment with conductive pads 132 and proper attachment of first and second semiconductor dice 160 and 170 to interposer substrate 110. For example, the recesses 120 may be formed in the interposer substrate 110 to be approximately 125 μm in diameter or width and the conductive bumps 166 formed on the semiconductor die 160 may be about 75 μm in diameter or width. Thus, the dimensions of the recesses 120 accommodate inconsistencies in dimensions and locations of the conductive bumps 166 therein, facilitating die alignment.
As shown in
Once the conductive elements 192 are bonded to the interposer substrate 110 and the encapsulation material 182 has been provided thereto, complete encapsulation of the flip-chip semiconductor device assembly 180 may be effected, as depicted in
As depicted in
According to the present invention, the first and second recess patterns 222 and 224 in the first surface 212 of the interposer substrate 210 provide versatility in that semiconductor dice of different sizes and/or different bumped configurations may optionally be mounted to the first surface of the interposer substrate. Such versatility provides that the first recess pattern 222 and the second recess pattern 224 share a common die attach site, namely, die attach site 242, optionally bearing an adhesive element 252. Further, as in the first embodiment, the recesses 220 are sized and configured to substantially completely receive the conductive bumps 266 of the semiconductor die 260 so that the active surface 262 of the die 260 lies immediately adjacent the first surface 212 of the interposer substrate 210. As such, the semiconductor device assembly 280 of the present invention provides a reduced height compared to conventional flip-chip assemblies.
As in the first embodiment, the semiconductor device assembly 280 attached by conductive elements 292 to the terminal pads 294 of substrate 290, either stacked with other assemblies 280 or individually on the substrate 290, may then be either fully encapsulated or partially encapsulated by an encapsulation member 186 and/or by a dispenser 184, as previously described in
As depicted in
Further, as in the previous embodiments and as noted above, interposer substrate 310 includes test pads 334 fanned out from recesses 320 proximate a periphery 316 of interposer substrate 310 and exposed on the first surface 312 and/or the second surface 314 of interposer substrate 310. As such, subsequent to mounting semiconductor dice to interposer substrate 310 on the first surface 312 and/or the second surface 314 thereof, the resulting flip-chip semiconductor device assembly may be tested to determine the mechanical and electrical integrity of the interconnections between the semiconductor dice and the interposer substrate 310.
As depicted in
Further, as in the previous embodiments, interposer substrate 410 includes test pads 434 fanned out from recesses 420 proximate a periphery 416 of interposer substrate 410 and exposed on the first surface 412 of interposer substrate 410. Test pads 434 are each common to two recess patterns, as shown in
Similar to that described in each of the previous embodiments, the interposer substrate of the present invention may also be assembled at a wafer level, wherein the interposer substrate is a wafer scale interposer substrate including at least two different recess patterns. As such, the wafer scale interposer substrate may facilitate assembly with different wafers having different bumped configurations that correspond with the at least two different recess patterns in the wafer scale interposer substrate. In this manner, optional wafers with different bumped configurations may be attached face (active surface) down to the wafer scale interposer substrate with conductive bumps on the wafer disposed and substantially received in recesses formed in the interposer substrate. The wafer and interposer substrate may then be singulated or diced into individual semiconductor assemblies. Partial encapsulation of the semiconductor dice on the wafer or wafers may be performed at the wafer level and completed subsequent to being diced into individual flip-chip semiconductor device assemblies according to the present invention.
As illustrated in block diagram form in
Yet another embodiment of the present invention is depicted in
As also depicted in
In lieu of stacking semiconductor packages 680, however, it is contemplated that either approach to the present invention, comprising a flexible interposer substrate using dual conductive layers having a dielectric member interposed therebetween or a single conductive layer interposed between two dielectric members, may be employed to implement a folded interposer substrate package according to the present invention. An exemplary embodiment of a dual-sided folded interposer substrate package is disclosed in
While the present invention has been disclosed in terms of certain exemplary embodiments and variations thereof, those of ordinary skill in the art will recognize and appreciate that the invention is not so limited. Additions, deletions and modifications to the disclosed embodiments may be effected without departing from the scope of the invention as claimed herein. Similarly, features from one embodiment may be combined with those of another while remaining within the scope of the invention. For example, features of the fourth embodiment may be combined with the second embodiment, wherein the first surface of the interposer substrate may include four recess patterns and the second surface of the interposer substrate may include two recess patterns. Further, any number of recess patterns may be provided on the first surface and/or the second surface of the interposer substrate for optional semiconductor die attachment thereto.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200201289-6 | Mar 2002 | SG | national |
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