Patent Application
20140273525
Related fields include thin-film semiconductor device manufacture, particularly atomic layer deposition of oxide films.
As integrated circuit feature sizes decrease, other device dimensions also decrease to maintain the proper device operation. For example, as gate conductor widths decrease, the thickness of the gate dielectric needs to decrease to provide proper capacitance to control the transistor.
Silicon dioxide (SiO2), a gate dielectric used in larger scale devices, would need to be <1.5 nm thick to be used in a sub-100 nm MOSFET device. Unfortunately, SiO2 is subject to high tunneling leakage in thicknesses <2 nm. The tunneling leakage increases power consumption and reduces device reliability. Materials with dielectric constants, k, greater than the SiO2 's value of 3.9 (“high-k materials”) have been studied as replacements for SiO2. For example, a ˜5 nm-thick layer of material with k=20 (e.g., a transition metal oxide such as hafnium oxide), has the same capacitance as a SiO2 layer that is only 1 nm thick; thus, its “equivalent oxide thickness” (EOT) would be 1 nm. Tunneling leakage current decreases rapidly with physical thickness, and is very low through a 5 nm gate.
Tunneling, however, is not the only source of unwanted leakage current that inhibits progress in fabricating reliable smaller-scale transistors (and other components, such as memory cells). Material properties, such as mobile charge-carrying defects and metallic nanoclusters that can form in metal-oxide layers subjected to sufficiently strong electric fields, facilitate leakage by other mechanisms that cannot be mitigated by simply thickening the layer. These material properties are often highly dependent on process conditions and methods of forming the high-k layers, but the variables can be challenging to measure and correct. In particular, films of aluminum oxide (Al2O3) and other metal oxides such as hafnium oxide (HfOx) and zirconium oxide (ZrOx) are prone to high or inconsistent leakage current at thicknesses of 2-10 Å.
Therefore, a need exists for a method of forming metal-oxide films with consistently low leakage current from all leakage mechanisms.
The following summary presents some concepts in a simplified form as an introduction to the detailed description that follows. It does not necessarily identify key or critical elements and is not intended to reflect a scope of invention.
Metal-oxide films made by atomic layer deposition (ALD) are formed by alternating cycles of metal deposition and oxidation (“A-B cycling”). Each cycle deposits a monolayer of metal oxide. Each cycle includes exposing the substrate to a metal precursor; purging the chamber to remove unreacted precursors and by-products; exposing the substrate to an oxygen precursor; and purging the chamber a second time. A typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
In some embodiments, the second purge has a duration longer than 60 seconds; for example, 60-120 seconds or 65-80 seconds. The first purge can be kept short, less than 15 seconds or 5-15 seconds. Each of the monolayers may have an effective thickness between about 0.6 Å and about 1.2 Å, and the A-B cycle may be repeated until the metal oxide film is between about 2 Å and about 50 Åthick. The resulting film may have a leakage current density less than about 0.1 microamps per square centimeter (μA/cm2); sometimes it may be less than about 0.05 μA/cm2 or 0.01-0.05 μA/cm2.
The metal precursor may include a precursor for aluminum, zirconium, or hafnium. An aluminum precursor may include trimethylaluminum (TMA). The oxygen precursor may include water or ozone. Either the first (post-metal) or the second (post-oxygen) purge may include flooding the chamber with an inert gas such as argon, nitrogen, or helium.
A gate stack fabricated on substrate 101 includes high-k gate dielectric layer 104, gate electrode layer 105, and gate conductor layer 106. Spacers 107 are formed between the gate stack {104, 105, 106} and the surrounding interlayer dielectric (ILD) 108. High-k dielectric layer 104 may include a metal oxide such as Al2O3, HfOx, or ZrOx. High-k dielectric layer 104 provides a sufficient equivalent oxide thickness (EOT) to prevent leakage current through the gate due to tunneling.
Gate electrode layer 105 is formed on high-k dielectric layer 104 and may include aluminum, polysilicon, or other suitable conductive materials (e.g., TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, TiSiN, etc.). Spacers 107 (made of SiO2, Si3N4, tetraethyl Orthosilicate (TEOS) or other suitable dielectric materials) isolate gate electrode 105 and high-k dielectric layer 104 from source region 102 and drain region 103.
Various processes exist for creating the MOSFET structure. For example, in a “gate-first” process, high-k dielectric layer 104, gate electrode layer 105, and gate conductor layer 106 may be initially formed as blanket layers on substrate 101. Then the layers may be patterned (e.g., by dry or wet etching or lithography) to remove everything except the gate stack. Afterward, the surrounding structures are fabricated; source 102 and drain 103 dopants are implanted, spacers 107 are formed, and the ILD 108 is added.
In an alternative “gate-last,” “dummy gate,” or “replacement gate” process, high-k dielectric layer 104 is also initially formed as a blanket layer on substrate 101. However, a sacrificial material (e.g., polysilicon) temporarily takes the place of gate electrode layer 105 and gate conductor layer 106; it is deposited on top of high-k dielectric layer 104 and patterned along with it to form a dummy gate stack. The surrounding structures are fabricated around the dummy gate stack. Afterward, the sacrificial material is removed by etching or another suitable process, to be replaced by gate electrode layer 105 and gate conductor layer 106. The dummy gate approach can be advantageous if the materials of gate electrode layer 105 and gate conductor layer 106 can be damaged by some of the processes for making the surrounding structure (e.g., high temperature).
In part “B” of the cycle, an oxygen precursor such as water (H2O) or ozone (O3) is introduced 204 into the chamber, as a pulse or as a continuous flow, then the chamber is purged 205 a second time. The purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition. The purge gas may be an inert gas such as argon, nitrogen, or helium. Post-oxygen purge 205 has a duration longer than 60 seconds, which may be between 60 and 120 seconds or between 65 and 80 seconds. This completes one ALD cycle, depositing a layer of metal oxide about 0.6 Å-1.2 Åthick. ALD layer thickness is typically expressed as an average thickness. A contiguous monolayer is one molecule thick. However, a non-contiguous monolayer, where there are empty spaces left between the deposited atoms, can be less than 1 molecule thick on average.
If the film is determined 206 to have reached a desired thickness after the most recent cycle, the process is complete; if not, another A-B cycle is performed. Thickness determination 206 can be made by monitoring the film thickness or, when the thickness per cycle is known, simply by counting cycles. For example, the desired thickness may be in a range of 2-50 Å, or 2-10 Å, or 25-35 Å.
A conductive layer is then added 306 above the metal oxide. The conductive layer may operate as an electrode and may also cap the metal-oxide layer to protect it from the environment outside the process chamber. The conductive layer may have its process parameters kept constant for each variation of the metal oxide, or its process parameters may also be selected for variation. Optionally, the conductive layer may also be annealed or otherwise treated after deposition.
One or more capacitors are formed 307 from the resulting test stack of Si/SiOx/metal oxide/conductor. A test voltage is applied 308 and the leakage current is measured 309. Other tests may also be performed. The results from different sets of process parameters are compared to select the best metal-oxide process. Each set of selected process parameters may be implemented and tested on a separate substrate, or, with equipment and methods such as the High Productivity Combinatorial system described in U.S. Pat. No. 7,947,531 (incorporated herein by reference for all purposes), multiple sets of process parameters may be implemented and tested on a single substrate.
Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the description and drawings. The examples are illustrative, not restrictive. There are many alternative ways of implementing the invention. Various aspects or components of the described embodiments may be used singly or in any combination. The scope is limited only by the claims, which encompass numerous alternatives, modifications, and equivalents.
This application claims priority to U.S. Prov. Pat. App. No. 61/779,740, filed 13 Mar. 2013, the entirety of which is incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61779740 | Mar 2013 | US |
