Board on chip package and manufacturing method thereof

Abstract

An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

FIG. 1 is a sectional view of a board on chip package according to the prior art;

FIG. 2 is a sectional view of a board on chip package according to an embodiment of the present invention;

FIGS. 3 and 4 illustrate a manufacturing process of a board on chip package according to a first embodiment of the present invention;

FIGS. 5 and 6 illustrate a manufacturing process of a board on chip package according to a second embodiment of the present invention; and

FIGS. 7 and 8 illustrate a manufacturing process of a board on chip package according to a third embodiment of the present invention.

Claims

1. A method for manufacturing a board on chip package, the method comprising: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film;(b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire;(c) removing the dry film;(d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed;(e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated;(f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding;(g) molding the semiconductor chip with a passivation material;(h) removing the carrier film and the thin metal film; and(i) laminating a lower photo solder resist under the solder ball pad.

2. The method of claim 1 further comprising ( ) surface-treating the solder ball pad by applying tin (Sn).

3. A method for manufacturing a board on chip package, the method comprising: (a) laminating a first dry film on a carrier film, one side of which is laminated by a thin metal film;(b) patterning the first dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and the circuit wire;(c) removing the first dry film;(d) laminating a second dry film excluding a portion where the solder ball pad is formed;(e) etching the thin metal film formed on a portion where the second dry film is not laminated;(f) surface-treating the solder ball pad by applying tin (Sn);(g) removing the second dry film;(h) mounting a semiconductor chip on the solder ball pad by a flip chip bonding;(i) molding the semiconductor chip with a passivation material;(j) removing the carrier film and the thin metal film; and(k) laminating a photo solder resist under the solder ball pad.

4. The method of claim 1, further comprising laminating an organic compound on the circuit wire.

5. The method of claim 3, further comprising laminating an organic compound on the circuit wire.

6. The method of claim 1, wherein the carrier film is an insulation layer, and the thin metal film is formed of copper.

7. The method of claim 3, wherein the carrier film is an insulation layer, and the thin metal film is formed of copper.

8. The method of claim 1, wherein the carrier film is formed of copper (Cu), and the thin metal film is formed of nickel (Ni).

9. The method of claim 3, wherein the carrier film is formed of copper (Cu), and the thin metal film is formed of nickel (Ni).

10. The method of claim 8, wherein the thickness of the carrier film is between 30 μm and 40 μm.

11. The method of claim 9, wherein the thickness of the carrier film is between 30 μm and 40 μm.

12. A board on chip package comprising: a photo solder resist having a cavity and a pattern on one side, the pattern being corresponding to a circuit wire;a solder ball pad accommodated in the cavity;a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist;a semiconductor chip mounted on the solder ball pad by a flip chip bonding; anda passivation material for molding the semiconductor chip.

13. A board on chip package comprising: a photo solder resist having an area and a pattern, a semiconductor chip being mounted on the area, the pattern being formed in accordance with a circuit wire;a circuit wire formed in one side of the photo solder resist, and having a pattern;a solder ball pad formed on one side of the photo solder resist, and electrically connected with the circuit wire;a semiconductor chip mounted on the solder ball pad by a flip chip bonding; anda passivation material molding the semiconductor chip.