The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture.
Radio frequency (RF) devices are used in many different types of communication applications. For example, RF devices can be used in cellular telephones with wireless communication components such as switches, MOSFETs, transistors and diodes.
RF devices are typically manufactured on high resistivity silicon wafers or substrates to achieve the needed RF linearity. State-of-the-art trap rich silicon on insulator (SOI) high resistivity substrates offer excellent vertical isolation and linearity, but the SOI wafer can be up to 50% of the total manufacturing cost because they can be 5 to 10 times the cost of high resistivity non-SOI substrates, i.e., a RF device formed on a SOI wafer could have a total normalized manufacturing cost of 1.0 while a similar device formed on a high resistivity non-SOI bulk wafer could have a total normalized manufacturing cost of 0.6. Devices built on bulk Si substrates have been known to suffer from degraded linearity, harmonics, noise and leakage currents, any of which will degrade device performance thus necessitating the higher cost of SOI wafers.
In an aspect of the disclosure, a structure comprises: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.
In an aspect of the disclosure, a structure comprises: one or more cavity structures provided in a substrate material and sealed with an epitaxial material having an oxidized upper surface; a shallow trench isolation region directly above the one or more cavity structures and contacting the oxidized upper surface; and at least one passive device positioned over the shallow trench isolation region and directly above the one or more cavity structures.
In an aspect of the disclosure, a method comprises: forming one or more cavity structures in a substrate material; sealing the one or more cavity structures with epitaxial material; forming a trench structure over the one more cavity structures which exposes the epitaxial material; oxidizing the epitaxial material; filling in the trench structure over the oxidizing epitaxial material to form a shallow trench isolation region directly above the one or more cavity structures; and forming a device on the shallow trench isolation region.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. More specifically, the present disclosure includes localized cavity structures which are positioned under shallow trench isolation regions, and more particularly under passive devices, e.g., inductors, polySi pn pin diodes, Efuses, etc. Advantageously, the cavity structures disclosed herein improve performance of the passive devices, e.g., inductors, by reducing the eddy currents flowing through the silicon substrate, hence enhancing the quality factor of inductors above the cavity region. Moreover, the cavity structures can provide improved decoupling of the inductor and substrate. The cavity structures also increase the distance between the substrate and the passive devices (inductors, polySi pn diodes, pin diodes, electrostatic discharge (ESD) devices, MIMs, Efuses, etc.), which lower coupling to the substrate and, hence lower substrate capacitance loss.
In embodiments, the cavity structures are located under the shallow trench isolation regions below inductors (or polySi pn diodes, pin diodes, ESD devices, MIMs, Efuses, etc.). The cavity structures can be filled with air and can be used for any Bulk Si wafer technologies where passive devices are present to improve the Q-factor. The cavity structures can be sealed with epi-SiGe and oxidized before shallow trench isolation regions are filled on top of an oxidized Si and the oxidized SiGe. The cavity structures can also be used to avoid expensive SOI wafers and/or high resistivity wafers. For example, the cavity structures can be formed in bulk silicon wafers with standard resistivity of about 0.01 to 100 ohm-cm; although the cavity structures can also be used in high resistivity silicon wafers, e.g., a resistivity of about >1 Kohm−cm to about 10 Kohm-cm or higher. In addition, the cavity structures can be filled with air underneath the shallow trench isolation region below inductors to reduce eddy currents and improve decoupling between inductor (or polySi pn pin diodes, MIMs, ESD devices, Efuses, etc.) and substrate.
The structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
Still referring to
Referring still to
Referring still to
The sidewall liner should robustly coat the sidewalls of the trenches 22 in order to protect the underlying substrate material 12 from subsequent etching processes (for cavity formation). To achieve this robust sidewall coverage, the dielectric material needs to be thick enough to leave a thick film on the sidewalls of the trenches 22 but not too thick that it pinches off the top opening of the trenches 22, which would prevent cavity formation during the successive cavity etch. For example, 40 nm of nitride can be deposited on a 100 nm wide trench. In another embodiment, for example, the sidewall of trenches 22 are thermally oxidized to form a SiO2 layer.
As shown further in
Following the formation of the sidewall liner or spacer and optional clean(s), exposed substrate material at the bottom of the trench 22 can be removed to form the cavity structures 24. In embodiments, the exposed substrate material 12 can be removed by a wet etching process or dry etching process. For example, dry etchants can include plasma-based CF4, plasma-based SF6, or gas XeF4 silicon etch, etc., and wet etching processes can include KOH and NH4OH. In embodiments, the cavity structures 24 can be formed under what will be the shallow trench isolation structures below a passive device, e.g., inductor. In embodiments, the upper surface of the cavity structure 24 can be about 300 nm in depth below the top surface of the substrate 12; although other dimensions are also contemplated herein. In addition, the cavity structures 24 can have a diameter of about 200 nm to about 800 nm as an example; although other dimensions are contemplated herein.
After formation of the cavity structures 24, the sidewall liner and pad dielectrics are removed, exposing the upper surface of the substrate 12 and the sidewalls of the trenches 22. In embodiments, the sidewall liner and pad dielectrics can be removed by a conventional etching process selective to such materials, e.g., only or a combination of hot phosphorous followed by an HF chemistry or vice-versa.
Following the removal of the sidewall liner and pad dielectrics, the trenches 22 are subjected to an optional annealing process to soften or round (curve) the edges of the trenches, as shown representatively at reference numeral 26. By way of one example, following a HF preclean process, the structure can undergo an annealing process at a temperature range of about 600° C. to about 1100° C., for up to about 60 seconds. In more specific embodiments, the annealing process can be at a temperature of about 650° C. for 60 seconds. In embodiments, the annealing process can be performed in an H2 atmosphere; although other hydrogen atmospheres are also contemplated herein, e.g., NH3, B2H6, Phi, AsH2 or other gases bonded to hydrogen. In embodiments, the annealing in an H2 or other hydrogen atmosphere may remove any native or other oxide from the silicon substrate surface. This annealing process may smooth or reflow the walls of the cavity structures 24.
In embodiments, a material 28 is deposited or epitaxially grown on the surface of the substrate 12 including, e.g., the curvature 26, sidewalls of the trenches 22 and sidewalls of the cavity 24. In embodiments, the material 28 can be epitaxial SiGe deposited or grown using ultra high vacuum CVD (UHVCVD); although other semiconductor materials, poly or epi films, and deposition processes are also contemplated herein. By way of example, SiGe material can be deposited or grown at a temperature of about 500° C. to 850° C., resulting in a thickness of about 5 nm to about 50 nm. In embodiments, 15 nm of SiGe is deposited or grown at 650° C. and the trench width 22 is 120 nm. It should be understood that other thicknesses of the material 28 can be applied, depending on the critical dimension of the trenches 22. In general, as the width of the trench 22 increases, the thickness of material 28 to fill in the top of the trench 22 during the subsequent reflow anneal increases.
As further shown in
In embodiments, the reflow temperature of the material 28 is about 700° C. to 1050° C. and the reflow time is anywhere up to about 600 seconds. It should also be noted that application of temperature during the reflow process will affect the size and shape of the cavity structures 24. In particular, the cavity structures 24 become a different shape, e.g., oval shape, slightly shrinking its volume compared to its original shape.
By way of example, a layer of substrate material 30 is formed over the sealed cavity structures 24, followed by a deposition of a pad material 32. In embodiments, the substrate material 30 is a same material as the substrate 12. For example, the substrate 30 can be epitaxially grown Si. The pad material 32 can be a nitride material or an oxide material or a combination of oxide and nitride. A resist (not shown) formed over the pad material 32 is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., RIE, will be used to form one or more trenches 34a, 34b in the semiconductor material 30 and substrate pad material 32, through the openings of the resist. The resist can then be removed by a conventional oxygen ashing process or other known stripants. As shown in
As shown in
At this stage, the wafers are ready for CMOS fabrication processes, e.g., formation of passive devices 38 and active devices 40. In embodiments, the passive devices 38 can be inductors, capacitors, diodes, Si photonics, e.g., waveguides, photodetectors, MEMs devices, etc., each of which are formed over the shallow trench isolation structures, directly over top of the cavity structures 24. Similarly, the active devices 40, e.g., transistors, can be fabricated above active regions of the structure, e.g., adjacent or to the sides of the shallow trench isolation structures.
In embodiments, the passive devices 38 can be inductors fabricated using conventional deposition and CMOS patterning processes. In embodiments, the inductors can be metal lines having the following non-limiting, illustrative parameters:
(i) Outside diameter=200 μm;
(ii) Number of turns=3;
(iii) Turn width=5 μm;
(iv) Space width=5 μm;
(v) Underpath width=15 μm; and
(vi) Inductor underpath levels: thick metal.
By implementing the features described herein, e.g., cavity structures below the inductors, the Q-factor of the inductor can be increased by 50% compared to conventional integrated inductors.
The remaining features of
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Number | Name | Date | Kind |
---|---|---|---|
4710794 | Koshino et al. | Dec 1987 | A |
4888300 | Burton | Dec 1989 | A |
5427975 | Sparks et al. | Jun 1995 | A |
5844299 | Merrill | Dec 1998 | A |
5869374 | Wu | Feb 1999 | A |
5943581 | Lu et al. | Aug 1999 | A |
5949144 | Delgado et al. | Sep 1999 | A |
5972758 | Liang | Oct 1999 | A |
6093330 | Chong et al. | Jul 2000 | A |
6093599 | Lee et al. | Jul 2000 | A |
6057202 | Chen et al. | Sep 2000 | A |
6140197 | Chu et al. | Oct 2000 | A |
6255704 | Iwata et al. | Jul 2001 | B1 |
6258688 | Tsai | Jul 2001 | B1 |
6274920 | Park | Aug 2001 | B1 |
6307247 | Davies | Oct 2001 | B1 |
6337499 | Werner | Jan 2002 | B1 |
6376291 | Barlocchi et al. | Apr 2002 | B1 |
6518144 | Nitta et al. | Feb 2003 | B2 |
6518147 | Villa et al. | Feb 2003 | B1 |
6551944 | Fallica et al. | Apr 2003 | B1 |
6570217 | Sato et al. | May 2003 | B1 |
6670257 | Barlocchi et al. | Dec 2003 | B1 |
6720229 | Norström et al. | Apr 2004 | B2 |
6833079 | Giordani | Dec 2004 | B1 |
6835631 | Zhen et al. | Dec 2004 | B1 |
6928879 | Partridge et al. | Aug 2005 | B2 |
6992367 | Erratico et al. | Jan 2006 | B2 |
7009273 | Inoh et al. | Mar 2006 | B2 |
7053747 | Joodaki | May 2006 | B2 |
7279377 | Rueger et al. | Oct 2007 | B2 |
7294536 | Villa et al. | Nov 2007 | B2 |
7326625 | Jeong et al. | Feb 2008 | B2 |
7354786 | Benzel | Apr 2008 | B2 |
7427803 | Chao et al. | Sep 2008 | B2 |
7662722 | Stamper et al. | Feb 2010 | B2 |
7678600 | Villa et al. | Mar 2010 | B2 |
7906388 | Sonsky | Mar 2011 | B2 |
8203137 | Cho et al. | Jun 2012 | B2 |
8319278 | Zeng et al. | Nov 2012 | B1 |
8575690 | Hsieh | Nov 2013 | B1 |
8652951 | Huang et al. | Feb 2014 | B2 |
8674472 | Botula et al. | Mar 2014 | B2 |
8907408 | Sedlmaier et al. | Dec 2014 | B2 |
8927386 | Wu et al. | Jan 2015 | B2 |
9029229 | Adkisson et al. | May 2015 | B2 |
9048284 | McPartlin et al. | Jun 2015 | B2 |
9059252 | Liu et al. | Jun 2015 | B1 |
9159817 | Camillo-Castillo et al. | Oct 2015 | B2 |
9177866 | Davies | Nov 2015 | B2 |
9224858 | Camillo-Castillo et al. | Dec 2015 | B1 |
9324846 | Camillo-Castillo et al. | Apr 2016 | B1 |
9349793 | Jaffe et al. | May 2016 | B2 |
9355972 | Dunn et al. | May 2016 | B2 |
9570564 | Alperstein et al. | Feb 2017 | B2 |
9640538 | Liu et al. | May 2017 | B2 |
9711392 | Dehe et al. | Jul 2017 | B2 |
9722057 | Camillo-Castillo et al. | Aug 2017 | B2 |
9726547 | Liu et al. | Aug 2017 | B2 |
9917186 | Laven et al. | Mar 2018 | B2 |
9922973 | Shank et al. | Mar 2018 | B1 |
10062757 | Toia et al. | Aug 2018 | B2 |
10109490 | Lin et al. | Oct 2018 | B1 |
10446643 | Adusumilli et al. | Oct 2019 | B2 |
10461152 | Stamper et al. | Oct 2019 | B2 |
20020043686 | Bolam et al. | Apr 2002 | A1 |
20020195681 | Melendez et al. | Dec 2002 | A1 |
20030067014 | Tsuruta | Apr 2003 | A1 |
20040180510 | Ranade et al. | Sep 2004 | A1 |
20040217434 | Lee et al. | Nov 2004 | A1 |
20040217443 | Davies | Nov 2004 | A1 |
20050176222 | Ogura | Aug 2005 | A1 |
20060091453 | Matsuda et al. | May 2006 | A1 |
20060138541 | Nakamura et al. | Jun 2006 | A1 |
20060214258 | Kiyotoshi | Sep 2006 | A1 |
20060228864 | Chen et al. | Oct 2006 | A1 |
20070181920 | Renna et al. | Aug 2007 | A1 |
20070238250 | Zhang et al. | Oct 2007 | A1 |
20080044979 | Wells et al. | Feb 2008 | A1 |
20080073747 | Chao et al. | Mar 2008 | A1 |
20090072351 | Meunier-Beillard et al. | Mar 2009 | A1 |
20090101997 | Lammel et al. | Apr 2009 | A1 |
20090127648 | Chen et al. | May 2009 | A1 |
20090191687 | Hong et al. | Jul 2009 | A1 |
20100035403 | Brown et al. | Feb 2010 | A1 |
20100059854 | Lin et al. | Mar 2010 | A1 |
20100109120 | Fucsko et al. | May 2010 | A1 |
20100117136 | Yasuda | May 2010 | A1 |
20120028401 | De Munck et al. | Feb 2012 | A1 |
20120038024 | Botula et al. | Feb 2012 | A1 |
20120211805 | Winkler | Aug 2012 | A1 |
20120292700 | Khakifirooz et al. | Nov 2012 | A1 |
20130043490 | Sorada | Feb 2013 | A1 |
20130320459 | Shue et al. | Dec 2013 | A1 |
20140042595 | Schulze et al. | Feb 2014 | A1 |
20140097402 | Wang et al. | Apr 2014 | A1 |
20140151852 | Adkisson et al. | Jun 2014 | A1 |
20140252481 | Flachowsky et al. | Sep 2014 | A1 |
20140353725 | Adkisson et al. | Dec 2014 | A1 |
20150179755 | Rooyackers et al. | Jun 2015 | A1 |
20150179791 | Kudou | Jun 2015 | A1 |
20150194416 | Cheng et al. | Jul 2015 | A1 |
20150318665 | Liang | Nov 2015 | A1 |
20150348825 | Hebert | Dec 2015 | A1 |
20160372592 | Cho | Dec 2016 | A1 |
20170110574 | LaVen et al. | Apr 2017 | A1 |
20170117224 | Adusumilli et al. | Apr 2017 | A1 |
20170170056 | Jaffe et al. | Jun 2017 | A1 |
20180083098 | Goktepeli | Mar 2018 | A1 |
20190013382 | Stamper et al. | Jan 2019 | A1 |
Number | Date | Country |
---|---|---|
2009099841 | May 2009 | JP |
201711190 | Mar 2017 | TW |
Entry |
---|
Notice of Allowance in related TW Application No. 107112403 dated Mar. 27, 2019, 4 pages. |
Response to Office Action in related U.S. Appl. No. 15/876,727 dated Apr. 11, 2019, 7 pages. |
Final Office Action in related U.S. Appl. No. 15/703,220 dated Mar. 19, 2019, 17 pages. |
Response to Final Office Action in related U.S. Appl. No. 15/645,655 dated Mar. 20, 2019, 11 pages. |
Final Office Action in related U.S. Appl. No. 15/645,655 dated Jan. 31, 2019, 16 pages. |
Office Action in U.S. Appl. No. 15/703,220 dated Oct. 18, 2019, 18 pages. |
Response to Office Action in U.S. Appl. No. 15/703,220 dated Jan. 17, 2020, 12 pages. |
Office Action in related U.S. Appl. No. 15/876,727 dated Jan. 11, 2019, 10 pages. |
Taiwanese Office Action and Search Report in related TW Application No. 106132441 dated Dec. 7, 2018, 14 pages. |
Final Office Action in U.S. Appl. No. 15/703,220 dated Mar. 16, 2020, 21 pages. |
Response to Final Office Action in U.S. Appl. No. 15/703,220 dated Apr. 20, 2020, 16 pages. |
Taiwanese Office Action and Search Report in related TW Application No. 106132441 dated Mar. 3, 2020, 10 pages. |
Hashimoto et al., “A Study on Suppressing Crosstalk Through a Thick SOI Substrate and Deep Trench Isolation”, IEEE, Jul. 2013, vol. 1, No. 7, 7 pages. |
Ohguro et al., “High performance digital-analog mixed device on a Si substrate with resistivity beyond 1 kΩ cm”, IEEE, 2000, 4 pages. |
Response to Office Action in related U.S. Appl. No. 15/645,655, filed Oct. 18, 2018, 12 pages. |
Office Action in related U.S. Appl. No. 15/645,655 dated Jul. 19, 2018, 17 pages. |
Taiwanese Office Action in related U.S. Appl. No. 106132441 dated Jul. 16, 2018, 10 pages. |
Office Action in related U.S. Appl. No. 15/703,220 dated Sep. 5, 2018, 27 pages. |
Response to Office Action in related U.S. Appl. No. 15/703,220, filed Dec. 5, 2018, 12 pages. |
Taiwanese Office Action in related U.S. Appl. No. 107112403 dated Oct. 18, 2018, 9 pages. |
Taiwanese Office Action in TW Application No. 106132441 dated Jun. 4, 2019, 10 pages. |
Response to Final Office Action in U.S. Appl. No. 15/703,220, filed Apr. 25, 2019, 13 pages. |
Second Response to Final Office Action in U.S. Appl. No. 15/703,220, filed Jun. 5, 2019, 13 pages. |
Notice of Allowance in U.S. Appl. No. 15/876,727 dated Jun. 12, 2019, 9 pages. |
Notice of Allowance in U.S. Appl. No. 15/645,655 dated Jul. 19, 2019, 9 pages. |
DE Office Action in DE Application No. 102018222690.3 dated May 28, 2020, 9 pages. |
Office Action in U.S. Appl. No. 16/575,675 dated Jun. 30, 2020, 11 pages. |
Notice of Allowance in U.S. Appl. No. 15/703,220 dated Jun. 15, 2020, 8 pages. |
Notice of Allowance in U.S. Appl. No. 16/575,675 dated Oct. 15, 2020, 8 pages. |
Response to Office Action in U.S. Appl. No. 16/575,675, filed Sep. 14, 2020, 8 pages. |
Office Action in U.S. Appl. No. 16/206,375 dated Oct. 19, 2020, 12 pages. |
Office Action in U.S. Appl. No. 16/538,062 dated Oct. 6, 2020, 7 pages. |
Taiwanese Office Action in TW Application No. 108139071 dated Aug. 21, 2020, 9 pages. |
Taiwanese Notice of Allowance in TW Application No. 106132441 dated Sep. 8, 2020, 4 pages. |
Number | Date | Country | |
---|---|---|---|
20200219760 A1 | Jul 2020 | US |