Patent Application
20170170108
Embodiments described herein generally relate to the field of integrated circuit packages and, in particular, chip carriers having solder pads sized to match impedance of a signal line.
Integrated circuit packages are used for protecting an integrated circuit chip or die, and also to provide the chip or die with a physical and electrical interface to external circuitry. An integrated circuit packages may incorporate a chip carrier, such as a ball grid array (BGA) component, for the chip or die. The BGA component usually includes solder pads having identical sizes across an entire package surface. Typically, the size of the solder pads are selected to ensure mechanical integrity of the integrated circuit package when the BGA component is mounted on an external substrate, e.g., a printed circuit board (PCB).
Chip carriers, such as ball grid array (BGA) components, having solder pads of different sizes, and integrated circuit packages incorporating such chip carriers, are described. In the following description, numerous specific details are set forth, such as packaging and interconnect architectures, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as specific semiconductor fabrication processes, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
Existing chip carriers of integrated circuit packages may include a multi-layered package substrate, and electrical interconnects may transfer electrical signals through the package substrate between an integrated circuit chip or die and solder pads of the chip carrier. Parasitic capacitance can form between the solder pads and a ground plane of the multi-layered package substrate, causing an impedance mismatch between the fixed-size solder pads of the chip carrier and an interconnect, e.g., a plated-through hole, in the package substrate. Furthermore, as signal speeds of a chip or die of an integrated circuit package increase, e.g., to provide serializer/deserializer (SerDes) functionality, the impedance mismatch may cause reflection losses and degrade the high speed signal performance. To compensate for the parasitic capacitance and improve the impedance matching of the interface, an opening may be formed between the ground plane and the solder pads. That is, voids may be formed in the package substrate around the solder pads. Such structural modifications to the package substrate may, however, lead to warpage and delamination issues that negatively affect the physical and electrical interface between the integrated circuit package and external circuitry.
In an aspect, a chip carrier having variably-sized solder pads improves impedance matching of solder pads used for high speed signals, and thus, the chip carrier meets high speed signal requirements. In an embodiment, a chip carrier includes two or more sets of solder pads having respective pad dimensions, i.e., distances across pad surfaces. For example, a first set of solder pads may include a pad diameter of 630 microns and a second set of solder pads may include a pad diameter of 470 microns. The smaller pads of the second set may reduce parasitic capacitance, and thus, may improve impedance matching for their respective signal lines. The larger pads may be used to maintain mechanical integrity of the package, e.g., the larger pads may be located along an outer column and/or outer row of a ball field of the chip carrier where mechanical stress tends to localize. Thus, chip carriers having solder pads of different sizes, and integrated circuit packages incorporating such chip carriers, may improve high speed signal routing without negatively affecting the physical and electrical interface between the integrated circuit package and external circuitry. From a manufacturing perspective, such a solution may be easier to implement than forming openings in the package substrate, and thus, the solution can also lead to cost savings over existing solutions.
Referring to
Each solder ball 110 may be electrically connected to integrated circuit 102 to provide an electrical function. For example, solder balls 110 near a center of package substrate 108 may be electrically connected to a pin 114, e.g., a signal pin used for I/O, of integrated circuit 102, and solder balls 110 near a periphery of package substrate 108 may be electrically connected to another pin 114 of integrated circuit 102 used as power and/or ground pins. Furthermore, solder balls 110 may be mounted and attached to a circuit board 116, e.g., a motherboard or another printed circuit board of a computer system, to provide a physical and electrical interface between integrated circuit 102 and circuit board 116.
The electrical connection between solder balls 110 of BGA component 104 and pins 114 of integrated circuit 102 may be through an interconnect 118 and/or a lead 120. More particularly, lead 120 may electrically connect pins 114 of integrated circuit 102 to one or more bonding pads 122 mounted on a second surface 124 of package substrate 108. Second surface 124 may be a surface opposite from first surface 112 on a same side of package substrate 108 as integrated circuit 102. Thus, lead 120 include a wire having ends soldered to a respective pin 114 on integrated circuit 102 and to a respective bonding pad 122 on second surface 124. Accordingly, several pins 114 of integrated circuit 102 may be electrically connected to several corresponding bonding pads 122 on second surface 124.
Bonding pads 122 mounted on second surface 124 may be electrically connected to corresponding solder pads 126 on first surface 112. More particularly, a solder pad 126 may be mounted on first surface 112 of package substrate 108, and solder pad 126 may be electrically connected to bonding pad 122 through interconnect 118. As described below, solder pads 126 may include flat surfaces etched into a layer of package substrate 108, and corresponding solder balls 110 may be attached to the flat surfaces. Thus, pins 114 of integrated circuit 102 may be electrically connected to solder balls 110 through a signal line that includes interconnect 118 extending from bonding pad 122 on second surface 124 through package substrate 108 to solder pad 126 on first surface 112.
Referring to
Referring to
In an embodiment, second solder pad 214 includes a second pad surface 306 having a shape or size that differs from first pad dimension 304. For example, although second pad surface 306 and first pad surface 302 are illustrated as being octagonal in
Referring to
As described below, solder pad 126 placement on first surface 112 may be selected based on an intended physical and/or electrical function of the solder pad 126. For example, first solder pads 212 having larger solder pad 126 dimensions may be dedicated to low speed signals, e.g., power/ground signals or I/O signals below a threshold frequency, and second solder pads 214 having smaller solder pad 126 dimensions may be dedicated to high speed signals, e.g., I/O signals above the threshold frequency. More particularly, the size of each solder pad 126 may be varied to match the impedance of a corresponding signal line carrying a signal that the solder pad 126 is intended to transmit and/or receive. Accordingly, solder pads 126 may be individually sized to improve the overall high speed performance of integrated circuit package 100.
Referring to
Solder pads 126 arranged in grid pattern 502 may be grouped into one or more grid blocks, i.e., sections of grid pattern 502 having a predetermined arrangement of solder pads 126. In an embodiment, a first grid block 504 refers to a region of grid pattern 502 that only incorporates solder pads 126 of a predetermined size. For example, first grid block 504 may only include first solder pads 212 having first pad dimensions 304, e.g., 630 microns. First solder pads 212 within first grid block 504 may not be separated from each other by a solder pad 126 having a different pad dimension. Grid pattern 502 may include a second grid block 506 that is distinguishable from first grid block 504. For example, second grid block 506 may refer to a region of grid pattern 502 that incorporates solder pads 126 having a different size than solder pads 126 that are repeatedly distributed within first grid block 504. Having differentiated between first grid block 504 and second grid block 506, various embodiments of grid blocks within grid pattern 502 are described below. It is noted that the following embodiments are provided by way of example to illustrate BGA component 104 having variably-sized solder pads 126, and are not limiting. For example, in each of the following approaches, second grid block 506 having second solder pads 214 for high speed signals is located in a bottom region of grid pattern 502, however, second grid block 506 may be located elsewhere in other embodiments.
Referring to
In an embodiment, one of the second solder pads 214 in second grid block 506 is located between a pair of first solder pads 602 in second grid block 506. For example, grid pattern 502 may include a row 604 of solder pads 126 sequentially aligned between an outer column 606 on a left side of BGA component 104 and an outer column on a right side of BGA component 104. At least two first solder pads 212 may be separated by one or more second solder pads 214 in row 604. In an embodiment, at least two first solder pads 212 or at least two second solder pads 214 may be separated by one or more third solder pads 408 in row 604. Thus, second grid block 506 may include any combination of variably-sized solder pads 126 located according to the I/O signals that the solder pads 126 are intended to carry. For example, in an embodiment, only solder pads 126 intended to carry high speed I/O signals may have pad dimensions less than 600 microns.
Referring to
In an embodiment, second grid block 506 having a set of second solder pads 214 may be located between pair of first solder pads 602 in row 604. More particularly, second grid block 506 may separate a first portion of first grid block 504 having outer column 606 on a left side of BGA component 104 from a second portion of first grid block 504 having an outer column on a right side of BGA component 104. Thus, second grid block 506 may be located one or more rows (or columns) inward from outer column 606. Accordingly, outer column 606 of grid pattern 502 having variably-sized solder pads may incorporate solder pads 126 having larger dimensions along an outer row or outer column 606 to contribute to mechanical integrity of BGA component 104.
Referring to
In addition to locating solder pads 126 based on an intended signal speed function, solder pads 126 may be placed to ensure mechanical integrity of integrated circuit package 100. In an embodiment, solder joint stress in solder balls 110 attached to circuit board 116 is highest at the corners of integrated circuit package 100. More particularly, stresses in the solder joints tend to decrease exponentially from a corner-most solder ball 110, e.g., a solder ball 110 in an outer row and an outer column of grid pattern 502, toward a center of grid pattern 502. The localized high stress at the package corner may result from localized bending of circuit board 116. Thus, in an embodiment, solder pads 126 having smaller dimensions, such as second solder pads 214, may be located in a region of grid pattern 502 away from an outer row or an outer column. More particularly, first solder pads 212 having larger first pad dimension 304 may be located at the corners of grid pattern 502 and/or within an outer row or an outer column of grid pattern 502. Thus, first solder pads 212 having a larger dimension may be employed to maintain the mechanical integrity of integrated circuit package 100. Furthermore, appropriately located (i.e., not located at the package corner or the die shadow) second solder pads 214 having a smaller dimension may be employed to improve high speed signal performance of integrated circuit package 100 without negatively affecting mechanical integrity of integrated circuit package 100.
High speed signal performance of an embodiment of integrated circuit package 100 having BGA component 104 with variably-sized solder pads 126 has been characterized. By way of example, integrated circuit 102 may include a first signal pin 114 electrically connected to first solder pad 212. For example, the first signal pin 114 may be electrically connected to first bonding pad 402 in
Referring to
Referring to
Simulation of integrated circuit packages 100 and BGA components 104 having variably-sized solder pads 126 confirms that the improvement in signal loss described above is related to improved impedance matching. For example, Time Domain Reflectometry (TDR) results for signals delivered from first bonding pad 402 to first solder pad 212 having first pad dimension 304 of 630 microns, and signals delivered from second bonding pad 404 to second solder pad 214 having second pad dimension 308 of 470 microns, has shown an improvement in eye width of 2%, an improvement in eye height of 5%, and an improvement in jitter of 19%. One skilled in the art will recognize that these numbers confirm that the smaller second solder pad 214 is better matched to the impedance of the signal line 200 than the larger first solder pad 212. More particularly, such results confirm that the smaller solder pad 126 reduces the capacitive debt and provides a smoother impedance profile supportive of higher-speed signals.
Referring to
At operation 906, solder balls 110 may be attached to the sets of solder pads 126. For example, a solder ball 110 may be attached to each of the first pad surfaces 302 and the second pad surfaces 306. Solder balls 110 may be uniformly sized and arranged in grid pattern 502 across first surface 112. Solder balls 110 may cover the variably-sized solder pads 126 of BGA component 104.
At operation 908, bonding pads 122 may be formed on second surface 124 of package substrate 108. Like solder pads 126, bonding pads 122 may be formed using known processing techniques. Furthermore, bonding pads 122 may be electrically connected to solder pads 126 on first surface 112 through interconnects 118, and processing techniques known for forming electrical interconnects 118 through package substrate 108 may be used to achieve such electrical connection. Specific description of the processing techniques are omitted here in the interest of brevity.
At operation 910, pins 114 of integrated circuit 102 may be connected to corresponding bonding pads 122 to electrically connect the pins 114 to solder balls 110 attached to corresponding solder pads 126. For example, pins 114 may be electrically connected to bonding pads 122 through the leads 120 using known wire bonding techniques. In an embodiment, a first pin 114 of integrated circuit 102 is electrically connected to first solder pad 212 through first bonding pad 402, and a second pin 114 of integrated circuit 102 is electrically connected to second solder pad 214 through second bonding pad 404.
Having fabricated integrated circuit package 100 incorporating BGA component 104 using the operations described above, integrated circuit package 100 may be used to provide various processing functions. For example, integrated circuit 102 may deliver a first electrical signal 702 through the first signal pin 114 electrically connected to first solder pad 212. More particularly, the first electrical signal 702 may be a low speed I/O signal, e.g., an I/O signal having a frequency below 16 GHz. similarly, integrated circuit 102 may deliver a second electrical signal 704 through the second signal pin 114 electrically connected to second solder pad 214. More particularly, the second electrical signal 704 may have a higher frequency than the first electrical signal 702. For example, the second electrical signal 704 may be a high speed I/O signal, e.g., an I/O signal having a frequency above 16 GHz. Thus, integrated circuit package 100 may be used to support high speed signal performance with improved signal loss characteristics as described above. For example, integrated circuit package 100 may be used to provide serializer/deserializer (SerDes) functionality for a computer system.
In an embodiment, the electronic system 1000 is a computer system that includes a system bus 1020 to electrically couple the various components of the electronic system 1000. The system bus 1020 is a single bus or any combination of busses according to various embodiments. The electronic system 1000 includes a voltage source 1030 that provides power to the integrated circuit 1010. In some embodiments, the voltage source 1030 supplies current to the integrated circuit 1010 through the system bus 1020.
The integrated circuit 1010 is electrically coupled to the system bus 1020 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 1010 includes a processor 1012 that can be of any type. As used herein, the processor 1012 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 1012 includes, or is coupled with, a BGA component 104 having solder pads 126 of different sizes, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 1010 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 1014 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 1010 includes on-die memory 1016 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 1010 includes embedded on-die memory 1016 such as embedded dynamic random-access memory (eDRAM).
In an embodiment, the integrated circuit 1010 is complemented with a subsequent integrated circuit 1011. Useful embodiments include a dual processor 1013 and a dual communications circuit 1015 and dual on-die memory 1017 such as SRAM. In an embodiment, the dual integrated circuit 1010 includes embedded on-die memory 1017 such as eDRAM.
In an embodiment, the electronic system 1000 also includes an external memory 1040 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 1042 in the form of RAM, one or more hard drives 1044, and/or one or more drives that handle removable media 1046, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 1040 may also be embedded memory 1048 such as the first die in a die stack, according to an embodiment.
In an embodiment, the electronic system 1000 also includes a display device 1050, an audio output 1060. In an embodiment, the electronic system 1000 includes an input device such as a controller 1070 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 1000. In an embodiment, an input device 1070 is a camera. In an embodiment, an input device 1070 is a digital sound recorder. In an embodiment, an input device 1070 is a camera and a digital sound recorder.
As shown herein, the integrated circuit 1010 can be implemented in a number of different embodiments, including a package substrate having a BGA component 104 having solder pads 126 of different sizes, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate having a BGA component 104 having solder pads 126 of different sizes, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates having a BGA component 104 having solder pads 126 of different sizes embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of
Embodiments of a chip carrier, such as a BGA component, having solder pads of different sizes are described above. In an embodiment, a chip carrier includes a package substrate having a first surface and a second surface, and several solder pads mounted on the first surface in a pattern. The several solder pads may include a set of first solder pads and a set of second solder pads. Each first solder pad may have a first pad dimension across a first pad surface, and each second solder pad may have a second pad dimension across a second pad surface. The second pad dimension may be less than the first pad dimension. Furthermore, the chip carrier may include several bonding pads mounted on the second surface and electrically connected to the several solder pads through the package substrate.
In one embodiment, the pattern includes a grid pattern, and one or more of the second solder pads are between a pair of first solder pads in a row of the grid pattern.
In one embodiment, the set of second solder pads are arranged in a grid block, and the grid block is between the pair of first solder pads in the row of the grid pattern.
In one embodiment, the grid pattern includes an outer column of solder pads, and the grid block is one or more rows inward from the outer column.
In one embodiment, the first pad dimension is greater than 600 microns, and the second pad dimension is less than 500 microns.
In one embodiment, the several solder pads further include a set of third solder pads. Each third solder pad may have a third pad dimension across a third pad surface, and the third pad dimension may be less than the first pad dimension and greater than the second pad dimension.
In one embodiment, the pattern includes a grid pattern, and one or more third solder pads are between a first solder pad and a second solder pad in a row of the grid pattern.
In one embodiment, the one or more third solder pads are arranged in a grid block, and the grid block is between the first solder pad and the second solder pad in the row of the grid pattern.
In one embodiment, the grid block includes one or more columns of third solder pads. The one or more columns of third solder pads may be between a column of first solder pads having the first solder pad and a column of second solder pads having the second solder pad.
In an embodiment, an integrated circuit package includes a chip carrier and an integrated circuit. The chip carrier may include a package substrate having a first surface and a second surface, and several solder pads mounted on the first surface in a pattern. The several solder pads may include a set of first solder pads and a set of second solder pads. Each first solder pad may have a first pad dimension across a first pad surface, and each second solder pad may have a second pad dimension across a second pad surface. The second pad dimension may be less than the first pad dimension. The chip carrier may include several bonding pads mounted on the second surface and electrically connected to the several solder pads through the package substrate. The integrated circuit may have several pins electrically connected to the several bonding pads, and the pins may be electrically connected to the several solder pads through the several bonding pads.
In one embodiment, the pattern includes a grid pattern, and one or more second solder pads are between a pair of first solder pads in a row of the grid pattern.
In one embodiment, the first pad dimension is greater than 600 microns, and the second pad dimension is less than 500 microns.
In one embodiment, the integrated circuit includes a first signal pin electrically connected to a first solder pad and a second signal pin electrically connected to a second solder pad. The integrated circuit may be configured to deliver a first electrical signal having a first frequency through the first signal pin and a second electrical signal having a second frequency through the second signal pin. The second frequency may be higher than the first frequency.
In one embodiment, a return loss of the second electrical signal delivered to the second solder pad from the second signal pin is more than 15 dB when the second frequency is in a range of 20 GHz to 40 GHz.
In one embodiment, a first insertion loss of the first electrical signal delivered to the first solder pad from the first signal pin is 0.4 dB more than a second insertion loss of the second electrical signal delivered to the second solder pad from the second signal pin when the first electrical signal and the second electrical signal both have a frequency of 16 GHz.
In an embodiment, a method includes forming a set of first solder pads on a first surface of a package substrate, and forming a set of second solder pads on the first surface of the package substrate. Each first solder pad may have a first pad dimension across a first pad surface, and each second solder pad may have a second pad dimension across a second pad surface. The second pad dimension may be less than the first pad dimension. The method may further include attaching a solder ball to each of the first pad surfaces and the second pad surfaces.
In one embodiment, the first pad dimension is greater than 600 microns, and the second pad dimension is less than 500 microns.
In one embodiment, the method includes forming a set of third solder pads on the first surface of the package substrate. Each third solder pad may have a third pad dimension across a third pad surface. The third pad dimension may be less than the first pad dimension and greater than the second pad dimension.
In one embodiment, the method includes forming a plurality of bonding pads on a second surface of the package substrate. The bonding pads may be electrically connected to the first solder pads and the second solder pads. The method may further include coupling several pins of an integrated circuit to the bonding pads to electrically connect the pins to the solder balls through the first solder pads and the second solder pads.
In one embodiment, the method includes delivering a first electrical signal through a first signal pin of the integrated circuit electrically connected to a first solder pad, and delivering a second electrical signal through a second signal pin of the integrated circuit electrically connected to a second solder pad. The second electrical signal may have a higher frequency than the first electrical signal.
