Chip having a metal pillar structure

Information

  • Patent Grant
  • 8334594
  • Patent Number
    8,334,594
  • Date Filed
    Friday, August 13, 2010
    14 years ago
  • Date Issued
    Tuesday, December 18, 2012
    12 years ago
Abstract
The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention


The present invention relates to a chip, and more particularly to a chip having a metal pillar structure.


2. Description of the Related Art



FIG. 1 shows a cross-sectional view of a conventional chip having a metal pillar structure. The conventional chip 1 having a metal pillar structure comprises a chip body 11, at least one chip pad 12, a first passivation layer 13, an under ball metal layer (UBM) 14 and at least one metal pillar structure 15. The chip body 11 has an active surface 111. The chip pad 12 is disposed on the active surface 111. The first passivation layer 13 is disposed on the active surface 111, and has at least one first opening 131 so as to expose part of the chip pad 12. The under ball metal layer (UBM) 14 is disposed on the chip pad 12. The metal pillar structure 15 is disposed on the under ball metal layer (UBM) 14, and comprises a metal pillar 16 and a solder 17. The metal pillar 16 is disposed on the under ball metal layer (UBM) 14, and has a peripheral surface 161. The solder 17 is disposed on the metal pillar 16, and the maximum diameter formed by the solder 17 is greater than the diameter of the metal pillar 16, so that the solder 17 protrudes outside of a phantom zone extending upward from the peripheral surface 161 of the metal pillar 16.


The conventional chip 1 has the following disadvantages. When the pitch between two adjacent metal pillar structures 15 of the chip 1 is a fine pitch, and the maximum diameter formed by the solder 17 is greater than the diameter of the metal pillar 16, a solder bridge easily happens, which leads to a short circuit.


Therefore, it is necessary to provide a chip having a metal pillar structure to solve the above-mentioned problems.


SUMMARY OF THE INVENTION

The present invention is directed to a chip having a metal pillar structure. The chip comprises a chip body, at least one chip pad, a first passivation layer, an under ball metal layer (UBM) and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer (UBM) is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer (UBM), and comprises a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer (UBM). The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar.


The present invention is further directed to a chip having a metal pillar structure. The chip comprises a chip body, at least one chip pad, a first passivation layer, an under ball metal layer (UBM) and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer (UBM) is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer (UBM), and comprises a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer (UBM), and has a metal pillar. The solder is disposed in a phantom zone extending upward from the peripheral surface of the metal pillar.


Whereby, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a cross-sectional view of a conventional chip having a metal pillar structure;



FIGS. 2 to 8 are schematic views of a method for making a chip having a metal pillar structure according to a first embodiment of the present invention;



FIG. 9 is a cross-sectional view of a chip having a metal pillar structure according to a second embodiment of the present invention;



FIG. 10 is a cross-sectional view of a chip having a metal pillar structure according to a third embodiment of the present invention; and



FIGS. 11 to 17 are schematic views of a method for making a chip having a metal pillar structure according to a fourth embodiment of the present invention.





DETAILED DESCRIPTION OF THE INVENTION


FIGS. 2 to 8 show schematic views of a method for making a chip having a metal pillar structure according to a first embodiment of the present invention. As shown in FIG. 2, a chip body 21, at least one chip pad 22, a first passivation layer 23 and a sputtering layer 24 are provided. The chip body 21 has an active surface 211. The chip pad 22 is disposed on the active surface 211. The first passivation layer 23 is disposed on the active surface 211, and has at least one first opening 231 so as to expose part of the chip pad 22. The sputtering layer 24 covers the first passivation layer 23 and part of the chip pad 22. As shown in FIG. 3, a photoresist 25 is formed on the sputtering layer 24. The photoresist 25 has at least one photoresist opening 251. The photoresist opening 251 exposes part of the sputtering layer 24, and the position of the photoresist opening 251 corresponds to the chip pad 22.


As shown in FIG. 4, a metal pillar 26 is formed in the photoresist opening 251. The metal pillar 26 is disposed on the sputtering layer 24, the material of the metal pillar 26 is preferably copper (Cu), and the height of the metal pillar 26 has no limitation. As shown in FIG. 5, a solder 27 is formed in the photoresist opening 251. The solder 27 is disposed on the metal pillar 26, and therefore, the metal pillar 26 and the solder 27 form a metal pillar structure 28.


As shown in FIG. 6, the photoresist 25 (FIG. 5) is removed by a photoresist stripper, and part of the sputtering layer 24 (FIG. 5) is removed by etching, so as to form an under ball metal layer (UBM) 29. The metal pillar 26 is disposed on the under ball metal layer (UBM) 29, and the under ball metal layer (UBM) 29 is disposed on the chip pad 22. In the embodiment, the under ball metal layer (UBM) 29 is a multi-layered structure, the material of the under ball metal layer (UBM) 29 includes aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V) or copper (Cu), and the peripheral surface 261 of the metal pillar 26 is aligned with the peripheral surface 291 of the under ball metal layer (UBM) 29. As shown in FIG. 7, the solder 27 is heated, so that the solder 27 is melted and becomes a hemisphere due to the cohesion force. The maximum diameter formed by the solder 27 is shorter than or equal to the diameter of the metal pillar 26. Preferably, the height of the solder 27 is shorter than or equal to the radius of the metal pillar 26.



FIG. 7 shows a cross-sectional view of a chip having a metal pillar structure according to the first embodiment of the present invention. The chip 2 having a metal pillar structure comprises a chip body 21, at least one chip pad 22, a first passivation layer 23, an under ball metal layer (UBM) 29 and at least one metal pillar structure 28. The chip body 21 has an active surface 211. The chip pad 22 is disposed on the active surface 211. The first passivation layer 23 is disposed on the active surface 211, and has at least one first opening 231 so as to expose part of the chip pad 22. The under ball metal layer (UBM) 29 is disposed on the chip pad 22, and the under ball metal layer (UBM) 29 has a peripheral surface 291. In the embodiment, the under ball metal layer (UBM) 29 is a multi-layered structure, and the material of the under ball metal layer (UBM) 29 includes aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V) or copper (Cu).


The metal pillar structure 28 is disposed on the under ball metal layer (UBM) 29, and comprises a metal pillar 26 and a solder 27. The metal pillar 26 is disposed on the under ball metal layer (UBM) 29, and has a peripheral surface 261. In the embodiment, the material of the metal pillar 26 is copper (Cu), the height of the metal pillar 26 has no limitation, and the peripheral surface 261 of the metal pillar 26 is aligned with the peripheral surface 291 of the under ball metal layer (UBM) 29. The solder 27 is disposed on the metal pillar 26, and the maximum diameter formed by the solder 27 is shorter than or equal to the diameter of the metal pillar 26. Therefore, the solder 27 is disposed in a phantom zone extending upward from the peripheral surface 261 of the metal pillar 26. Preferably, the solder 27 is a hemisphere, and the height of the solder 27 is shorter than or equal to the radius of the metal pillar 26. In the present invention, the distance between the central axes of two adjacent metal pillar structures 28 is defined as a pitch D (FIG. 8), and the pitch D is less than or equal to 150 μm, that is, the pitch between two adjacent metal pillar structures 28 of the chip 2 is a fine pitch.



FIG. 9 shows a cross-sectional view of a chip having a metal pillar structure according to a second embodiment of the present invention. The chip 3 having a metal pillar structure according to the second embodiment is substantially the same as the chip 2 (FIG. 2) having a metal pillar structure according to the first embodiment, and the same elements are designated by the same reference numbers. The difference between the chip 3 and the chip 2 is that the chip 3 further comprises a second passivation layer 30. The second passivation layer 30 is disposed on the first passivation layer 23, and has at least one second opening 301 so as to expose part of the chip pad 22. In the embodiment, the material of the second passivation layer 30 is polyimide (PI), and the second opening 301 of the second passivation layer 30 is smaller than the first opening 231 of the first passivation layer 23. The under ball metal layer (UBM) 29 is disposed on the chip pad 22, and covers part of the second passivation layer 30.



FIG. 10 shows a cross-sectional view of a chip having a metal pillar structure according to a third embodiment of the present invention. The chip 4 having a metal pillar structure according to the third embodiment is substantially the same as the chip 3 (FIG. 9) having a metal pillar structure according to the second embodiment, and the same elements are designated by the same reference numbers. The difference between the chip 4 and the chip 3 is that the second opening 301 of the second passivation layer 30 is larger than the first opening 231 of the first passivation layer 23, so as to expose part of the chip pad 22 and part of the first passivation layer 23. The under ball metal layer (UBM) 29 is disposed on the chip pad 22, and covers part of the first passivation layer 23 and part of the second passivation layer 30.


In the present invention, when the pitch between two adjacent metal pillar structures 28 of the chips 2, 3, 4 is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.



FIGS. 11 to 17 show schematic views of a method for making a chip having a metal pillar structure according to a fourth embodiment of the present invention. The method according to the fourth embodiment is substantially the same as the method (FIGS. 2 to 8) according to the first embodiment, and the same elements are designated by the same reference numbers. The difference between the method according to the fourth embodiment and the method according to the first embodiment is that after a metal pillar 26 is formed, a barrier layer 31 is further formed on the metal pillar 26, and the material of the barrier layer 31 is nickel (Ni). Then, a solder 27 is formed on the barrier layer 31. The metal pillar 26, the barrier layer 31 and the solder 27 form a metal pillar structure 28.



FIG. 17 shows a cross-sectional view of a chip having a metal pillar structure according to a fourth embodiment of the present invention. The chip 5 having a metal pillar structure is substantially the same as the chip 2 (FIG. 7) having a metal pillar structure according to the first embodiment, and the same elements are designated by the same reference numbers, as shown in FIGS. 2 to 7. The difference between the chip 5 and the chip 2 is that the metal pillar structure 28 further comprises a barrier layer 31 disposed on the metal pillar 26. The solder 27 is disposed on the barrier layer 31, and a preferably material of the barrier layer 31 is nickel (Ni). Whereby, the barrier layer 31 prevents the solder 27 from penetrating the upper part of the metal pillar 26 and forming an intermetallic layer having weak strength. Therefore, the reliability of the metal pillar structure 28 is increased.


While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined by the appended claims.

Claims
  • 1. A chip having a metal pillar structure, comprising: a chip body, having an active surface;at least one chip pad, disposed on the active surface;a first passivation layer, disposed on the active surface, and having at least one first opening so as to expose part of the chip pad;an under ball metal layer (UBM), disposed on the chip pad; andat least one metal pillar structure, disposed on the under ball metal layer (UBM), comprising: a metal pillar, disposed on the under ball metal layer (UBM); anda solder, disposed on the metal pillar, wherein the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar,further comprising a second passivation layer, wherein the second passivation layer is disposed on the first passivation layer and has at least one second opening so as to expose part of the chip pad.
  • 2. The chip as claimed in claim 1, wherein the distance between the central axes of two adjacent metal pillar structures is defined as a pitch, and the pitch is less than or equal to 150 μm.
  • 3. The chip as claimed in claim 1, wherein the metal pillar structure further comprises a barrier layer disposed on the metal pillar, and the solder is disposed on the barrier layer.
  • 4. The chip as claimed in claim 1, wherein the peripheral surface of the metal pillar is aligned with the peripheral surface of the under ball metal layer (UBM).
  • 5. The chip as claimed in claim 1, wherein the height of the solder is shorter than or equal to the radius of the metal pillar.
  • 6. The chip as claimed in claim 1, wherein the second opening of the second passivation layer is smaller than the first opening of the first passivation layer.
  • 7. The chip as claimed in claim 1, wherein the second opening of the second passivation layer is larger than the first opening of the first passivation layer, and the second opening further exposes part of the first passivation layer.
  • 8. A chip having a metal pillar structure, comprising: a chip body, having an active surface;at least one chip pad, disposed on the active surface;a first passivation layer, disposed on the active surface, and having at least one first opening so as to expose part of the chip pad;a second passivation layer, disposed on the first passivation layer, and having at least one second opening so as to expose part of the chip pad;an under ball metal layer (UBM), disposed on the chip pad and extending along a sidewall defined by the second opening of the second passivation layer; andat least one metal pillar structure, disposed on the under ball metal layer (UBM), comprising: a metal pillar, disposed on the under ball metal layer (UBM); anda solder, extending upwardly from the metal pillar, wherein the height of the solder is smaller than or equal to the radius of the metal pillar.
  • 9. The chip as claimed in claim 8, wherein the maximum diameter of the solder is smaller than or equal to the diameter of the metal pillar.
  • 10. The chip as claimed in claim 8, wherein the distance between the central axes of two adjacent metal pillar structures is defined as a pitch, and the pitch is less than or equal to 150 μm.
  • 11. The chip as claimed in claim 8, wherein the metal pillar structure further comprises a barrier layer disposed between the solder and the metal pillar, and the barrier layer comprises nickel (Ni).
  • 12. The chip as claimed in claim 8, wherein a portion of the under ball metal layer (UBM) is disposed on an upper surface of the second passivation layer.
  • 13. The chip as claimed in claim 8, wherein the solder has a hemispherical shape.
  • 14. The chip as claimed in claim 8, wherein the second opening of the second passivation layer is smaller than the first opening of the first passivation layer.
  • 15. A semiconductor device, comprising: a chip comprising a pad disposed on an active surface of the chip;a first passivation layer disposed on the active surface, and having a first opening exposing the pad;a second passivation layer disposed over the first passivation layer, and having a second opening exposing the pad;a metal pillar disposed at least partially within the first opening and the second opening, and electrically connected to the pad; anda solder disposed over an upper surface of the metal pillar.
  • 16. The chip as claimed in claim 15, wherein a diameter of the first opening is greater than a diameter of the second opening.
  • 17. The chip as claimed in claim 15, further comprising a metal layer disposed between the pad and the metal pillar, wherein the metal layer has a different composition than the pad and the metal pillar.
  • 18. The chip as claimed in claim 15, further comprising a metal layer disposed between the metal pillar and the solder, wherein the metal layer has a different composition than the metal pillar and the solder.
  • 19. The chip as claimed in claim 18, wherein outer perimeters of the metal pillar, the metal layer, and the solder are substantially aligned.
  • 20. The chip as claimed in claim 15, wherein the solder has a hemispherical shape, and the height of the solder is less than the height of the metal pillar.
Priority Claims (1)
Number Date Country Kind
98134806 A Oct 2009 TW national
US Referenced Citations (70)
Number Name Date Kind
3761309 Schmitter et al. Sep 1973 A
4341594 Carlson et al. Jul 1982 A
4845542 Bezuk et al. Jul 1989 A
5466635 Lynch et al. Nov 1995 A
5629564 Nye, III et al. May 1997 A
5640052 Tsukamoto Jun 1997 A
5656858 Kondo et al. Aug 1997 A
5698465 Lynch et al. Dec 1997 A
5790377 Schreiber et al. Aug 1998 A
5872404 Lynch et al. Feb 1999 A
5914536 Shizuki et al. Jun 1999 A
5943597 Kleffner et al. Aug 1999 A
6013571 Morrell Jan 2000 A
6028357 Moriyama Feb 2000 A
6051450 Ohsawa et al. Apr 2000 A
6077765 Naya Jun 2000 A
6107164 Ohuchi Aug 2000 A
6159837 Yamaji et al. Dec 2000 A
6229220 Saitoh et al. May 2001 B1
6281106 Higdon et al. Aug 2001 B1
6350705 Lin Feb 2002 B1
6362087 Wang et al. Mar 2002 B1
6362090 Paik et al. Mar 2002 B1
6378759 Ho et al. Apr 2002 B1
6501185 Chow et al. Dec 2002 B1
6510976 Hwee et al. Jan 2003 B2
6550666 Chew et al. Apr 2003 B2
6573598 Ohuchi et al. Jun 2003 B2
6578754 Tung Jun 2003 B1
6592019 Tung Jul 2003 B2
6599775 Tie et al. Jul 2003 B2
6600234 Kuwabara et al. Jul 2003 B2
6639299 Aoki Oct 2003 B2
6642136 Lee et al. Nov 2003 B1
6664128 Tong et al. Dec 2003 B2
6681982 Tung Jan 2004 B2
6683375 Joshi et al. Jan 2004 B2
6731003 Joshi et al. May 2004 B2
6732913 Alvarez May 2004 B2
6734039 Hwee et al. May 2004 B2
6740577 Jin et al. May 2004 B2
6750082 Briar et al. Jun 2004 B2
6756671 Lee et al. Jun 2004 B2
6784087 Lee et al. Aug 2004 B2
6818545 Lee et al. Nov 2004 B2
6888209 Jobetto May 2005 B2
6917119 Lee et al. Jul 2005 B2
6929981 Hwee et al. Aug 2005 B2
6940168 Garrity et al. Sep 2005 B2
7008867 Lei Mar 2006 B2
7022548 Joshi et al. Apr 2006 B2
7087458 Wang et al. Aug 2006 B2
7122403 Chandran et al. Oct 2006 B2
7135770 Nishiyama et al. Nov 2006 B2
7268438 Nishiyama et al. Sep 2007 B2
7276801 Dubin et al. Oct 2007 B2
7391112 Li et al. Jun 2008 B2
7449406 Nishiyama et al. Nov 2008 B2
7456496 Hwee et al. Nov 2008 B2
7476564 Chen et al. Jan 2009 B2
7550375 Wang et al. Jun 2009 B2
20020011664 Tanaka Jan 2002 A1
20030127734 Lee et al. Jul 2003 A1
20030219966 Jin et al. Nov 2003 A1
20060006544 Farrar Jan 2006 A1
20080296761 Lee et al. Dec 2008 A1
20090072385 Alley et al. Mar 2009 A1
20090155955 Liang Jun 2009 A1
20090289360 Takahashi et al. Nov 2009 A1
20110084389 Lo et al. Apr 2011 A1
Foreign Referenced Citations (19)
Number Date Country
54128669 Oct 1979 JP
60217646 Oct 1985 JP
62160744 Jul 1987 JP
1123440 May 1989 JP
4144143 May 1992 JP
5109820 Apr 1993 JP
5152376 Jun 1993 JP
5315339 Nov 1993 JP
2711722 Aug 1995 JP
7335648 Dec 1995 JP
8008259 Jan 1996 JP
8013166 Jan 1996 JP
9266230 Oct 1997 JP
9045691 Dec 1997 JP
2000091371 Mar 2000 JP
2000269387 Sep 2000 JP
2002043352 Feb 2002 JP
2006279062 Oct 2006 JP
2008047667 Feb 2008 JP
Related Publications (1)
Number Date Country
20110084381 A1 Apr 2011 US