Chip package and stacked structure of chip packages

Abstract

A chip package is provided, which includes a dielectric layer, at least a conductive layer, a chip, a wiring layer and at least a conductive via. The dielectric layer has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces joined between the first surface and the second surface. One of the lateral surfaces has at least a groove, wherein the groove is extended from the first surface to the second surface. The conductive layer is disposed on the wall of the groove. The chip is inserted in the dielectric layer. The wiring layer is located on the first surface and electrically connected to the conductive layer. The conductive via is located in the dielectric layer to electrically connect the chip to the wiring layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve for explaining the principles of the invention.

FIG. 1 is a cross-sectional view of a conventional stacked structure of chip packages.

FIG. 2 is a top view of a chip package according to an embodiment of the present invention.

FIG. 3 is the side view of the chip package in FIG. 2.

FIG. 4 is a cross-sectional view along line A-A in FIG. 2.

FIG. 5 is a cross-sectional view along line B-B in FIG. 2.

FIG. 6 is a top view of a chip package according to another embodiment of the present invention.

FIG. 7 is a top view of a stacked structure of chip packages according to yet another embodiment of the present invention.

FIG. 8 is the side view of the stacked structure of chip packages in FIG. 7.

FIG. 9 is a diagram showing the stacked structure of chip packages in FIG. 7 assembled with a circuit board.

Claims

1. A chip package, comprising: a dielectric layer, having a first surface, a second surface, and a plurality of lateral surfaces joined between the first surface and the second surface, wherein one of the lateral surfaces has at least a groove;at least a conductive layer, disposed in the groove;a first chip, inserted in the dielectric layer;a first wiring layer, located on the first surface and electrically connected to the conductive layer; andat least a first conductive via, located in the dielectric layer for electrically connecting the first chip to the first wiring layer.

2. The chip package as recited in claim 1, further comprising a solder mask layer disposed on the first surface and the first wiring layer.

3. The chip package as recited in claim 1, wherein the first chip has an active surface and a back surface, wherein the back surface is exposed from the dielectric layer, and the first conductive via electrically connects the active surface to the first wiring layer.

4. The chip package as recited in claim 1, wherein the first chip has an active surface and a back surface, wherein the dielectric layer covers the back surface of the first chip, and the first conductive via connects the active surface to the first wiring layer.

5. The chip package as recited in claim 1, further comprising a second wiring layer and at least a second conductive via, wherein the second wiring layer is located on the second surface, and the second conductive via is located in the dielectric layer.

6. The chip package as recited in claim 1, further comprising a solder mask layer disposed on the second surface and the second wiring layer.

7. The chip package as recited in claim 1, further comprising at least a second chip and at least a third conductive via, wherein the second chip and the third conductive via are located in the dielectric layer, wherein the third conductive via electrically connects the first wiring layer to the second chip.

8. The chip package as recited in claim 1, wherein the material of the dielectric layer is epoxy, bismaleimide-triazine (BT), prepreg, or ceramic.

9. The chip package as recited in claim 1, wherein the first wiring layer is a patterned metal layer.

10. The chip package as recited in claim 1, wherein the first wiring layer is formed by a plurality of patterned metal layers and a plurality of dielectric layers.

11. The chip package as recited in claim 1, wherein the groove is extended from the first surface to the second surface.

12. A stacked structure of chip packages, comprising: a plurality of chip packages, stacked together, wherein each of the chip packages comprises: a dielectric layer, having a first surface, a second surface, and a plurality of lateral surfaces joined between the first surface and the second surface, wherein one of the lateral surfaces has at least a first groove;at least a conductive layer, disposed in the groove;a first chip, inserted in the dielectric layer;a first wiring layer, located on the first surface; andat least a first conductive via, located in the dielectric layer for electrically connecting the first chip to the first wiring layer; andat least a conductive post, disposed in the first groove and connected to the first conductive layer.

13. The stacked structure of chip packages as recited in claim 12, wherein the first chip of one of the chip packages has an active surface and a back surface, wherein the back surface is exposed from the corresponding dielectric layer, and the corresponding first conductive via electrically connects the active surface to the corresponding first wiring layer.

14. The stacked structure of chip packages as recited in claim 12, wherein one of the chip packages further comprises a second wiring layer and at least a second conductive via, wherein the second wiring layer is located on the corresponding second surface, and the second conductive via is located in the corresponding dielectric layer.

15. The stacked structure of chip packages as recited in claim 12, wherein one of the chip packages further comprises at least a second chip and at least a third conductive via, wherein the second chip and the third conductive via are located in the corresponding dielectric layer, wherein the third conductive via electrically connects the first wiring layer to the second chip.

16. The stacked structure of chip packages as recited in claim 12, wherein the material of the dielectric layer is epoxy, bismaleimide-triazine (BT), prepreg, or ceramic.

17. The stacked structure of chip packages as recited in claim 12, further comprising a plurality of bonding pads disposed on at least one of the conductive posts.

18. The stacked structure of chip packages as recited in claim 16, further comprising at least one solder ball disposed on the bonding pad.

19. The stacked structure of chip packages as recited in claim 12, wherein the first grooves of the chip packages correspond to one another.

20. The stacked structure of chip packages as recited in claim 12, the first groove is extended from the first surface to the second surface.