Claims
- 1. A power semiconductor package, comprising
a substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the source metalized surface to one or more of the plurality of conductive pads, at least one of the wire bonds extending from the gate metalized surface to one of the conductive pads.
- 2. The power semiconductor package of claim 1, wherein the plurality of wire bonds have respective lengths, the lengths being one of a plurality of discrete values.
- 3. The power semiconductor package of claim 2, wherein the number of discrete values is three.
- 4. The power semiconductor package of claim 2, wherein the plurality of wire bonds are disposed adjacent to one another, immediately adjacent wire bonds being of different lengths.
- 5. The power semiconductor package of claim 1, wherein the MOSFET die includes a lateral width spanning between the first and second spaced apart side edges, the respective wire bonds terminating at one of a plurality of discrete lateral positions.
- 6. The power semiconductor package of claim 5, wherein the number of discrete lateral positions is three.
- 7. The power semiconductor package of claim 5, wherein the plurality of wire bonds are disposed adjacent to one another, immediately adjacent wire bonds terminating at different lateral positions.
- 8. The power semiconductor package of claim 1, wherein the substrate includes a plurality of vias extending between the upper and lower surfaces.
- 9. The power semiconductor package of claim 8, wherein some of the vias provide electrical connection from the drain of the semiconductor die through the substrate.
- 10. The power semiconductor package of claim 9, wherein the vias are substantially filled with conductive material such that they are solid.
- 11. The power semiconductor package of claim 10, wherein the conductive material is tungsten.
- 12. The power semiconductor package of claim 8, further including a plurality of conductive balls forming a ball grid array disposed at the lower surface of the substrate, at least some of the balls of the array for providing electrical connection from the conductive material of the vias to an external circuit.
- 13. A power semiconductor package, comprising
a substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a first power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a second power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a plurality of conductive pads disposed only at the second side edge of the substrate; a first set of wire bonds extending from the source metalized surface of the first MOSFET die to one or more of the plurality of conductive pads, at least one of the wire bonds extending from the gate metalized surface of the first MOSFET die to one of the conductive pads; and a second set of wire bonds extending from the source metalized surface of the second MOSFET die to one or more of the plurality of conductive pads, at least one of the wire bonds extending from the gate metalized surface of the second MOSFET die to one of the conductive pads.
- 14. The power semiconductor package of claim 13, wherein the plurality of wire bonds extend in substantially the same direction.
- 15. The power semiconductor package of claim 13, wherein the plurality of wire bonds have respective lengths, the lengths being one of a plurality of discrete values.
- 16. The power semiconductor package of claim 15, wherein the number of discrete values is three.
- 17. The power semiconductor package of claim 15, wherein the plurality of wire bonds are disposed adjacent to one another, immediately adjacent wire bonds being of different lengths.
- 18. The power semiconductor package of claim 13, wherein the respective first and second MOSFET die include a lateral width spanning between the first and second spaced apart side edges, the respective wire bonds terminating at one of a plurality of discrete lateral positions.
- 19. The power semiconductor package of claim 18, wherein the number of discrete lateral positions is three.
- 20. The power semiconductor package of claim 18, wherein the plurality of wire bonds within a set are disposed adjacent to one another, immediately adjacent wire bonds terminating at different lateral positions.
- 21. The power semiconductor package of claim 13, wherein the substrate includes a plurality of vias extending between the upper and lower surfaces.
- 22. The power semiconductor package of claim 21, wherein some of the vias provide electrical connection from the respective drains of the first and second MOSFET die through the substrate.
- 23. The power semiconductor package of claim 21, wherein the vias are substantially filled with conductive material such that they are solid.
- 24. The power semiconductor package of claim 23, wherein the conductive material is tungsten.
- 25. The power semiconductor package of claim 21, further including a plurality of conductive balls forming a ball grid array disposed at the lower surface of the substrate, at least some of the balls of the array for providing electrical connection from the conductive material of the vias to an external circuit.
- 26. A power semiconductor package, comprising
a substrate having upper and lower surfaces, the upper surface including and a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a first power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a second power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; a plurality of conductive pads disposed only at the second side edge of the substrate; a plurality of wire bonds extending from the source metalized surface of the first MOSFET die to the source metalized surface of the second MOSFET die; at least one wire bond extending from the gate metalized surface of the first MOSFET die to one of the conductive pads; and at least one wire bond extending from the gate metalized surface of the second MOSFET die to one of the conductive pads.
- 27. The power semiconductor package of claim 26, wherein the plurality of wire bonds extend in substantially the same direction.
- 28. The power semiconductor package of claim 27, wherein the plurality of wire bonds extend transversely with respect to a direction defined from the first side edge to the second side edge of the substrate.
- 29. The power semiconductor package of claim 26, wherein the plurality of wire bonds have respective lengths, the lengths being one of a plurality of discrete values.
- 30. The power semiconductor package of claim 29, wherein the number of discrete values is two.
- 31. The power semiconductor package of claim 29, wherein the plurality of wire bonds are disposed adjacent to one another, immediately adjacent wire bonds being of different lengths.
- 32. The power semiconductor package of claim 26, wherein the respective first and second MOSFET die include a longitudinal width spanning between the front and rear spaced apart edges, the respective wire bonds terminating at one of a plurality of discrete longitudinal positions of each MOSFET die.
- 33. The power semiconductor package of claim 32, wherein the number of discrete longitudinal positions is three.
- 34. The power semiconductor package of claim 32, wherein the plurality of wire bonds are disposed adjacent to one another, immediately adjacent wire bonds terminating at different longitudinal positions of each MOSFET die.
- 35. The power semiconductor package of claim 26, wherein the substrate includes a plurality of vias extending between the upper and lower surfaces.
- 36. The power semiconductor package of claim 35, wherein some of the vias provide electrical connection from the respective drains of the first and second MOSFET die through the substrate.
- 37. The power semiconductor package of claim 35, wherein the vias are substantially filled with conductive material such that they are solid.
- 38. The power semiconductor package of claim 37, wherein the conductive material is tungsten.
- 39. The power semiconductor package of claim 35, further including a plurality of conductive balls forming a ball grid array disposed at the lower surface of the substrate, at least some of the balls of the array for providing electrical connection from the conductive material of the vias to an external circuit.
RELATED APPLICATIONS
[0001] This is a division of U.S. patent application Ser. No. 09/225,254, filed Jan. 4, 1999 in the name of Bharat Shivkumar, Daniel M. Kinzer and Jorge Munoz and entitled CHIP-SCALE PACKAGE.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09225254 |
Jan 1999 |
US |
Child |
10153051 |
May 2002 |
US |