Patent Application
20240153862
With advances in medium- and high-voltage silicon carbide (SiC) devices, wide-bandgap semiconductors can be used in power grid applications. SiC power devices offer the benefits of small size, less weight, high efficiency, and other benefits for power conversion in power grids. However, the high blocking voltages of these devices place a stringent demand on electrical insulation of the packages that interconnect and insulate the devices. The constant push for higher packaging power density only exacerbates the challenge. Over the last twenty years, various module packaging approaches have been developed to improve thermal performance and increase power density. Many approaches involve replacing the conventional wire-bonded structures with sandwiched or planar structures having low package parasitic inductances. Some planar packaging approaches are already being relied upon for semiconductor devices in the sub-kV to 1.2-kV range.
Planar, double-side cooled half-bridge power modules using sintered-silver interposers and all sintered-silver joints are described. Use of the sintered-silver interposers reduces thermo-mechanical stresses at vulnerable interfaces in the power modules as compared to using solid copper interposers. The porous sintered-silver interposers are also easily deformable under a low load, which improves the yield of module interconnections in the presence of imperfections caused by variations in die thickness, interposer height, and substrate distortion. Results on the electrical performance of the modules validate the fabrication approach for the modules, for making high power-density converters with reliable operations at high junction temperatures.
In one example, a power module includes a first substrate, a second substrate, a plurality of semiconductor transistor die positioned between the first substrate and the second substrate, a plurality of terminal pins, a plurality of power terminals, and a plurality of sintered-silver interposers bonded to a top contact of each of the plurality of semiconductor transistor die and positioned between the first substrate and the second substrate in the power module. The plurality of power terminals are staggered for electrical coupling to a busbar. A bottom surface of each of the plurality of semiconductor transistor die is also secured in electrical contact to at least one of the first substrate or the second substrate.
In one aspect of the embodiments, least one of the first substrate or the second substrate comprises an insulated metal substrate (IMS), such as a direct-bond-copper (DBC) substrate. The IMS includes a layer of ceramic or polymer between two layers of copper in some cases. The IMS includes a layer of ceramic or polymer, a first inner metal layer, and a second inner metal layer in some cases. The bottom surface of a first semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the first inner metal layer using sintered silver paste, and the bottom surface of a second semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the second inner metal layer using sintered silver paste. In other aspects, a first power terminal among the plurality of power terminals is electrically coupled to the first inner metal layer, and a second power terminal among the plurality of power terminals is electrically coupled to the second inner metal layer.
In other aspects, the first substrate includes a first inner metal layer, the second substrate comprises a second inner metal layer. The bottom surface of a first semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the first inner metal layer using sintered silver paste, and the bottom surface of a second semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the second inner metal layer using sintered silver paste.
In other aspects, the power module also includes a first plurality of bond wires electrically coupled from a first semiconductor transistor die among the plurality of semiconductor transistor die to a first subset of the plurality of terminal pins. The power module also includes a second plurality of bond wires electrically coupled from a second semiconductor transistor die among the plurality of semiconductor transistor die to a second subset of the plurality of terminal pins.
The plurality of semiconductor transistor die are coupled in a half bridge configuration and each of the plurality of semiconductor transistor die comprises a Silicon Carbide (SiC) metal oxide semiconductor field effect power transistor in one example. In other aspects, the sintered-silver interposers include interposers cut from a bar of sintered silver paste.
In another embodiment, a process or method of manufacturing a power module is described. In one example, the method includes applying a layer of silver paste on a metal layer of a substrate, positioning a plurality of semiconductor transistor die on the layer of silver paste over the metal layer of the substrate, positioning a plurality of silver interposers on the layer of silver paste over the metal layer of the substrate, and heating the substrate, the plurality of semiconductor transistor die, and the plurality of silver interposers to bond the semiconductor transistor die and first plurality of silver interposers to the substrate.
The heating can include heating at a ramp rate to a temperature of about 245° C., and the method can also include applying pressure to the plurality of silver interposers after reaching the temperature of about 245° C. In one case, applying the pressure comprises applying a pressure of about 2-MPa for about 15 minutes.
Additionally, the process can also include applying a second layer of silver paste on top surface contacts of the plurality of semiconductor transistor die, and positioning a second plurality of silver interposers on the second layer of silver paste over the top surface contacts of the plurality of semiconductor transistor die. The process can also include second heating the substrate, the plurality of semiconductor transistor die, the plurality of silver interposers, and the second plurality of silver interposers to bond the second plurality of silver interposers to the plurality of semiconductor transistor die. The second heating can include heating at a ramp rate to a temperature of about 245° C., and the method can also include applying pressure to the second plurality of silver interposers after reaching the temperature of about 245° C.
The method can also include applying a third layer of silver paste on a metal layer of a second substrate, positioning the second substrate over the substrate, with the third layer of silver paste facing the substrate, the plurality of semiconductor transistor die, the plurality of silver interposers, and the second plurality of silver interposers. The method can also include third heating the substrate, the second substrate, the plurality of semiconductor transistor die, the plurality of silver interposers, and the second plurality of silver interposers to bond the second substrate to the first plurality of silver interposers and the second plurality of silver interposers. The third heating can include heating at a ramp rate to a temperature of about 245° C., and the method can also include applying pressure to the second substrate after reaching the temperature of about 245° C.
Advances in wide-bandgap devices, such as SiC and gallium nitride (GaN) devices, have facilitated the development of higher efficiency and power-density power electronics converters. These efforts have posed significant challenges on power module packaging, as the packaging structures, materials, and processing conditions significantly influence the thermal, electrical, and mechanical performance and reliability of the modules.
Wire-bond interconnect technology has been used for electrical couplings to the top-side terminals or contacts of semiconductor devices, because of the maturity, low cost, and flexibility of the technology. However, wire-bonded packages have relatively high parasitic inductances and can only cool the devices from one side, the die-attach side. Also, due to mismatched coefficients of thermal expansion (CTE) between the wire bonds and semiconductor devices, the bonded areas are prone to fatigue failure caused by thermo-mechanical stresses. Paralleled wire bonds, ribbon bonds, direct lead bonding, and copper clip structures have been relied upon in some cases to improve current capacity, reduce parasitic inductances, and improve reliability. Modules made by these interconnect techniques, which use long and thin conductors to connect to the top terminals of semiconductor devices, are still limited to cooling from the die-attach side of the device chips.
Other packaging structures have been introduced in an attempt to improve thermal performance, such as metal-post-interconnected-parallel-plate-structures, flip-chip-on-flex, dimple-array, embedded power, silicon interposer, solder bump, metal bump, flip-chip, power overlay, and press-pack packages. However, many of these packages are structurally rigid as compared to wire-bonded packages, raising concerns for thermo-mechanical reliability.
To make a double-side cooled package, interposers such as metal bricks, balls, or tubes can used for interconnections, and copper (Cu) is a widely used interposer. Some designs have shown that the use of solid Cu interposers introduces more thermo-mechanical stresses in the device chips and at bonded interfaces than in wire-bonded packages. To reduce thermo-mechanical stresses, interposers made of molybdenum (Mo) or Cu/Mo/Cu were evaluated, as the CTE of Mo is closer to that of semiconductor materials than Cu. However, Mo has a lower thermal conductivity than Cu and may require a surface metallization to be compatible with soldering or silver-sintering.
One of the main concerns with thermo-mechanical stresses in double-side cooled power modules is the reduced bonding reliability at the chip-attach, interposer-chip, or interposer-substrate interface. Solders are the most commonly used bonding materials in power modules, but they are easily fatigued under thermo-mechanical stresses due to low melting temperatures, low elastic moduli, and the formation of brittle intermetallic. Thus, use of solders for bonding power modules limits their reliable operation to temperatures below about 200° C. in many cases. The assembly of double-side cooled modules also typically requires multiple bonding steps, which can require a set of solders with different melting temperatures, further limiting operational temperatures.
According to aspects of the embodiments, low-temperature silver (Ag) sintering can be relied upon as an alternative bonding technology to soldering. The sintering process can take place at less than 250° C. with or without pressure. Once sintered-silver joints are formed, the joints melt at 960° C. and have much higher thermal and electrical conductivities. Sintered-silver joints or bonds have much better reliability than soldered joints. These advantages make silver sintering an excellent lead-free and reliable solution for packaging double-side cooled and high-temperature power modules.
However, variations in device chip thickness, substrate flatness, and interposer heights can make it relatively difficult to use sintering processes for bonding double-side cooled modules. Soldering processes can easily overcome such variations because, as solders melt and solidify, they can easily “absorb” these variations to maintain continuity in heights, shapes, and other proportions at bonded interfaces. On the other hand, silver does not melt in the low-temperature silver sintering process. Rather, a sintered bond is formed through solid-state atomic diffusion and large volume shrinkage from densification. Silver sintered bonds cannot accommodate large geometric variations at the bonding line or interface. Some designs have used silver-sintering for semiconductor die and interposer attachment but have also used a thick layer of solder (˜200 μm) for the interposer-to-substrate bonding, to compensate for thickness and spacing variations.
According to aspects of the embodiments, one solution to enable silver sintering for bonded interfaces in a double-side cooled power module is to use interposers that can be plastically deformed under a low applied load during the assembly process. The deformable interposers and load can be relied upon to level geometric variations. And, to reduce the thermo-mechanical stresses, the interposer are made of materials or structures having low CTE, low elastic modulus, or both. Deformable silver tubing and metal foams have been explored as interposers to achieve adjustable height, but the trade-off is large thermal resistance through the top terminals because of the small heat conduction area.
According to aspects of the embodiments, interposers were formed by low-temperature sintering of a pressure-less silver paste, and the interposers were used along with a silver-sintering process to interconnect a double-side cooled power module. The interposers were made by filling and sintering a silver paste inside a trench in a Teflon block. The trench width defined the height of the interposer. Because the as-sintered silver interposers are relatively porous, the interposers can be deformed relatively easily during assembly processes, to accommodate geometric variations found in semiconductor die, substrates, and other components in power modules. The interposers also have a low elastic modulus to reduce thermo-mechanical stresses. Additionally, there is no need to surface-finish the interposers for bonding by silver-sintering.
To demonstrate the advantages of sintered-silver interposers according to the embodiments, a number of double-side cooled half-bridge power modules are described herein. First, the layout and design of the power modules and the thermal and thermo-mechanical simulations are described to show the advantages of the porous sintered-silver interposers. Then, a process for fabricating the interposers and the modules are also described, along with some example electrical performance measurements.
In one case, a double-side cooled half-bridge module including two 1200 V, 149 A SiC MOSFETs was designed, fabricated, and characterized. By using sintered-silver rather than solid copper interposers, simulated results showed that, at a total power loss of 200 W, the thermo-mechanical stress at vulnerable interfaces (e.g., the interposer-attach layer) could be reduced by about 42%. The thermo-mechanical stress in the SiC MOSFET could be reduced by about 50% with a trade-off of only 3.6% increase in junction temperature. The sintered-silver interposers were fabricated into desired dimensions without post-machining and did not require any surface finishing for die-bonding and substrate interconnection by silver sintering. The porous interposers were also deformable under a low force or pressure, which helped to accommodate for variations in chip thickness and substrate-to-substrate gap variations, thus simplifying the fabrication of the modules described herein. Experimental results on the electrical performance of the power modules validated the success of using the porous silver interposers for fabricating planar, double-side cooled power modules.
Turning to the drawings,
The power module 10 is a packaged semiconductor module suitable for use in high efficiency and high power-density power converters, traction inverters in electric drives, and other applications. Referring among
Referring to
The first semiconductor transistor die 30A can be embodied as a power transistor in one example, although the power module 10 can incorporate other types of semiconductor devices in some cases, such as diodes, controlled rectifiers, thyristors, and other devices. Similarly, the second semiconductor transistor die 30B can be embodied as a power transistor in one example, but it can also be embodied as other types of devices. In one example, the transistor die 30A and 30B can be embodied as SiC metal oxide semiconductor field effect power transistors, although they can be embodied as other types of devices formed from the same or other types of semiconductor materials. In the power module 10, the transistor die 30A and 30B are electrically coupled in a half bridge configuration between the first substrate 20A and the second substrate 20B. The electrical couplings are facilitated in part by the metal layer 22A of the first substrate 20A and the metal layer 22B of the second substrate 20B, as described in further detail below with reference to
The first and second semiconductor transistor die 30A and 30B can be embodied as transistors formed from a wide-bandgap material, such as semiconductor materials in the group IV family and semiconductor compounds in the group III-V and family, including SiC and GaN, among others. Wide-bandgap semiconductor materials can be relied upon to form devices capable of operating at much higher voltages, frequencies, and temperatures than conventional semiconductor materials like silicon. The power module 10 is not limited to the incorporation of only wide-bandgap semiconductor devices, however, because the power module 10 can include semiconductor devices formed from silicon and other materials.
The first terminal 40A can be embodied as a metal (e.g., copper or another conductor) terminal or flange for electrical contact with the power module 10. Similarly, the second terminal 40B and the third terminal 40C can also be embodied as metal terminals or flanges for electrical contact with the power module 10. The terminals 40A, 40B, and 40C can be relied upon as power terminals of the power module 10, and they are staggered in space for electrical coupling to a bus bar in the example shown.
Although not shown in
Turning to other features of the power module 10,
The electrical couplings in the power module 10 are now described with reference to
The terminal 40A is electrically coupled to the second inner metal layer 22AA, the terminal 40B is electrically coupled to the second inner metal layer 22BB, and the terminal 40C is electrically coupled to the first inner metal layer 22B. The sintered-silver interposers 32A and 32B are electrically coupled between the source contacts of the transistor die 30A and the first inner metal layer 22A (see also
The sintered-silver interposers 32 can be formed from a silver or nanosilver paste, including a silver powder that is dispersed in a binder for printing, spreading, or dispensing. In one example, the sintered-silver interposers 32 can be formed from NanoTach® X Series nanosilver paste of NBE Technologies, LLC, of Blacksburg, VA, USA, although other types of silver or nanosilver paste can be used. The silver paste can be used for making the sintered-silver interposers 32, chip-bonding, and interposer-chip and interposer-substrate bonding in the power module 10.
To make the sintered-silver interposers 32, a trench was machined on a Teflon block, with a width of the trench being one dimension and a depth of the trench being another of the two dimensions of the interposers 32. The silver paste was squeezed into the trench using a squeegee, followed by pressure-less sintering at 245° C. for 15 mins. The sintered-silver bars were easily demolded out of the trench and cut into individual ones of the interposers 32. The sintered-silver bars include a porous microstructure and are plastically deformable under heat and pressure, as described in further detail below. Due to shrinkage after sintering, the top surface of the sintered-silver bars can be recessed in some cases. Because the width of the trench defined the height of the interposer, height uniformity of the interposers was ensured. The two other dimensions of the interposer, one being the recessed depth and the other being the cut length from the bar, are not necessarily critical in view of the methods of assembly described below.
The wire bonds 34A-34C are electrically coupled between the transistor die 30A and the terminal pins 42A-42C, and the wire bonds 34D-34F are electrically coupled between the transistor die 30B and the terminal pins 42F-42H. Particularly, the wire bonds 34A and 34C are electrically coupled between one or more source contacts of the transistor die 30A and the terminal pins 42A and 42C. The wire bond 34B is electrically coupled between the gate contact of the transistor die 30A and the terminal pin 42B. Additionally, the wire bonds 34D and 34F are electrically coupled between one or more source contacts of the transistor die 30B and the terminal pins 42F and 42H. The wire bond 34E is electrically coupled between the gate contact of the transistor die 30B and the terminal pin 42G. Power can be applied through the terminals 40A, 40B, and 40C of the power module 10, and voltage measurement and signaling (including gate drive signaling) can be applied through the terminal pins 42A-42H of the power module 10.
The dimensions of the power module 10, in one example implementation, were 2.4 cm×1.8 cm×0.36 cm. The terminals 40 are on one side of the power module 10, and the terminal pins 42 are on another side of the power module 10. The configuration of the terminals 40 can be tailored to different busbar structures. Other than the terminal pins 42B and 42G, which are for gate drive, the rest of the terminal pins can be relied upon for current sensor and desaturation protection, among other purposes. In the example implementation, parasitic inductances of the power loop and drive loop were 4.4 nH and 3.0 nH, as extracted from ANSYS Q3D, respectively. The low power loop parasitic inductance can be attributed to having two parallel metal planes for routing.
ANSYS Workbench was used to simulate the temperature distributions in the power module 10. For comparison, the temperature distributions of the power module 10 with Cu and Mo interposers were also simulated. The thermal conductivities of Cu, Mo, and sintered-silver are 385 W/m ° C., 142 W/m ° C., and 175 W/m ° C., respectively. The high thermal conductivity of sintered-silver can be attributed to the percolation of the silver matrix with microstructurally distributed pores. In the simulations, the power dissipation from each transistor device was varied from 10 W to 100 W at an increment of 10 W, and the initial temperature was set at 22° C. Since both the transistor die 30A and 30B in the power module 10 were die-attached on the substrate 20B, for single-side cooling, a convection coefficient of 8000 W/m2·° C. was assumed at the substrate 20B and 20 W/m2·° C. at the substrate 20A. For double-side cooling, a convection coefficient of 8000 W/m2·° C. was assumed at both substrates 20A and 20B.
Although the different types of interposer materials (i.e., Ag, Cu, and Mo) have thermal conductivity values differing by nearly 300%, the differences in their junction temperatures (Tj) were small in simulation, at less than 5% difference under either single-sided or double-sided cooling. This is because a major portion of the heat generated in the power module 10 was dissipated away through the die-attach layer, not through the interposers. Nevertheless, the effect of double-sided cooling was shown to be significant in simulation, at approximately 30% in reduction of the junction temperature as compared to single-sided cooling. For example, at a total power loss of 200 W (100 W from each chip), the Tj of the module with the sintered-silver interposer and double-sides cooling decreased by 28% (or 46° C.) over that with single-sides cooling.
Using IMS or DBC substrates with thicker insulating layers can contribute to higher junction-to-case thermal resistance. This is because the thermal conductivity of the insulating ceramic or aluminum nitride layer is about 15 times lower than that of the copper metal layers in the DBC substrates. Thus, using IMS or DBC substrates with thinner insulating layers can offer a thermal benefit. The insulating layers of IMS or DBC substrates cannot be too thin, however, because dielectric breakdown can lead to failure of power modules. IMS or DBC substrates with ceramic thicknesses equal to 0.38 mm, 0.5 mm, 0.63 mm, 1.0 mm, or other thicknesses can be relied upon, as examples, depending on the application or use case for the power modules.
In simulations, power modules similar to the power module 10, with double-side cooling, were shown to have not only lower Tj, but also more uniform temperature distributions. Thermal simulations were run for plots of the chip power loss versus the heatsink convection coefficient with the maximum allowed junction temperature to be 150, 200, or 250° C. The simulations showed that double-side cooling significantly improves the chip power handling capability. For example, assuming a convection coefficient of 10000 W/m2·° C. and the maximum junction temperature of 150° C., the maximum power loss per chip that the power module 10 can support is about 107 W if cooled from one side and is 161 W if cooled from both sides. Thus, double-side cooling gives the power module 10 about 50% more power handling capability than single-side cooling.
ANSYS Workbench was also used to simulate the thermo-mechanical stresses in the double-side cooled power module 10 with Cu, Mo, and sintered-silver interposers. Table I, below, lists some of the material properties of the Cu, Mo, and sintered-silver.
In the simulations, the Anand viscoelasticity model was used to describe the viscoelastic behavior of all sintered-silver elements with parameters taken from reference materials. Other material parameters for the simulations are listed in Table I above. To simplify the simulations, the wire-bonds and encapsulant were ignored. The stress-free temperature was set at 245° C., close to the silver-sintering temperature for die-attach and interposer-attach. The simulation runs included first finding the thermo-mechanical stresses due to cooling from the sintering temperature down to room temperature and then the stresses from heating by the total module power loss of 200 W, or 100 W per chip.
In reliability studies of power modules, simulations at vulnerable joint locations are widely used to correlate with reliability measurement data. Stresses of attached layers using several spacer or interposer geometries were simulated to evaluate the embodiments, and the number of temperature cycles to failure were also measured by simulation. The testing showed that the number of cycles to failure is inversely correlated to the maximum von Mises stress. Based on the results of simulation, the sintered-silver interposers had the lowest stress among all the interposer materials, namely 81% and 69% lower than the Cu and Mo interposers, respectively. This is because the sintered-silver has two orders of magnitude lower elastic modulus and no CTE mismatch between the sintered-silver interposer and sintered-silver attachment. The stresses in the SiC MOSFETs were also significantly reduced when using sintered-silver interposers, by 50% and 32% compared to that with Cu and Mo interposers, respectively.
In testing, the stresses at the bonded interfaces with the sintered-silver interposers were much lower than those with Cu interposers while they were similar to those with the Mo interposers. Of the three bonded interfaces in each module, the interposer-to-substrate interface had the highest stress, thus it is the most likely sites to fail first. In view of the thermal simulation results, it is possible to realize substantial reductions in thermo-mechanical stresses at vulnerable interfaces by using sintered-silver instead of Cu interposers in the power module 10, with only a minor increase in junction temperature.
Table III is an example list of materials that can be used in the power module 10. However, the use of other materials and devices for the power module 10 is within the scope of the embodiments.
CREE SiC MOSFET chips were used in one case for the transistor die 30A and 30B. The chips are rated at 1.2 kV, 149 A, and 13 mΩ and have drain pads metallized with a nickel (Ni)/gold (Au) surface finish, which is compatible with silver-sintering. However, the source and gate pads were aluminum (Al), which is wire-bondable but not silver-sinterable. To make the source pads silver-sinterable, a metallization of 100-nm of titanium (Ti) and 100-nm of Ag was deposited by magnetron sputtering through a stainless-steel contact mask. Since the gate pad was too small for the metallization process, the gate and Kevin-source pads were wire-bonded by a 0.25 mm-diameter Al wire. The DBC substrates used for the substrates 20A and 20B were obtained from Rogers, Inc. and came with Ag surface finish for bonding by silver-sintering. The terminal pins 42 were locally machined from copper plates and attached to the power module 10 by soldering with a high-Pb solder alloy. An underfill material was used to encapsulate the transistor die 30A and 30B and bond the structure together.
With the arrangement shown in
In step (A), the process includes printing or applying a layer of silver paste on the substrate 20B at certain locations for bonding semiconductor die and interposers. The silver paste can be the silver paste of NBE Technologies, LLC, as described herein, although other silver pastes can be relied upon. As shown in
In step (B), the process includes positioning the semiconductor transistor die 30A and 30B and the interposers 32C and 32D at the locations where the silver paste was spread in step (A). As part of step (B), the process can also include heating the assembly at a constant ramp rate of about 5° C./min (i.e., within +/−10% of 5° C./min) from room temperature to about 245° C. (i.e., within +/−10% of 245° C.). Once the temperature of about 245° C. is reached, downward pressure is applied at a top of the interposers 32C and 32D for about 15 min, maintaining the 245° C. temperature, to sinter the chip-attach and interposer-to-substrate attach. A pressure of 2-MPa can be applied in this step, although larger and smaller amounts of pressure can be applied in other cases, depending on the size and plasticity of the interposers, among other factors.
At step (C), the process includes printing or applying silver paste over the top contacts of the semiconductor transistor die 30A and 30B at locations for the interposers 32A, 32B, 32E, and 32F. The process also includes positioning the interposers 32A, 32B, 32E, and 32F on the silver paste over the semiconductor transistor die 30A and 30B. As part of step (C), the process can also include heating the assembly at a ramp rate of about 5° C./min from room temperature to about 245° C. Once the temperature of about 245° C. is reached, pressure is applied to the interposers 32A, 32B, 32E, and 32F for about 15 min, maintaining the 245° C. temperature, to sinter the interposer-to-chip attach. A pressure of 2-Pa can be applied in this step.
At step (D), the process can include wire-bonding the gate and source pads of the semiconductor transistor die 30A and 30B to the metal contact pads of the bottom substrate 20B, for connection to the terminal pins of the power module 10. At step (E), the process includes printing or applying silver paste on the top substrate 20A at locations for top-attach to the semiconductor transistor die 30A and 30B and the interposers 32A-32F.
At step (F), the process includes arranging the top substrate 20A over the semiconductor transitory die 30A and 30B, the interposers 32A-32F, and the bottom substrate 20B. The process also includes heating the assembly at a ramp rate of about 5° C./min from room temperature to about 245° C. Once the temperature of about 245° C. is reached, pressure is applied to the top substrate 20A for about 15 min, maintaining the 245° C. temperature, to sinter the attach. A pressure of 2-MPa can be applied in this step. A hot press can be used in step (F). Buffer sheets of rubber and Teflon can be used between the top platen of the hot press and the top substrate 20A, to ensure uniform pressure applied on the power module 10.
At step (G), the process includes soldering the terminals 40 and the terminal pins 42 in place as described herein. In step (H), the process includes adding or extruding an underfill material into the empty space between the two substrates 20A and 20B and curing the underfill in place. The encapsulation material keeps oxygen and or moisture away from the silver joints and interposers, thus mitigating the silver migration risk.
Step (H) in
Of the steps described above, step (F) is relatively important. Here, the pressure-assisted sintering is helpful to close any gaps in the interconnection caused by variations in chip thickness, interposer height, and substrate distortion. If the heights of the interposers are different, for example, at first all of the applied load is applied to the taller one(s), which then quickly shrank due to their porous structure until all the interposers were leveled and evenly shared the load. The fact that sintered-silver interposers can be easily deformed under a low load significantly increases assembly yield.
The static characteristics of the power module 10 were tested using a curve tracer. Testing showed that the leakage currents of the transistors were the same, before and after packaging. The package interconnects and terminal leads only added about 2 mΩ of on-resistance to the device. Overall, the static I-V characteristics of the packaged die were similar to those of the bare die. Similarities of the static characteristics between the packaged and bare device suggest that the packaging process described herein, including the sintering steps under 2-Pa pressure, did not alter the device characteristics.
Although embodiments have been described herein in detail, the descriptions are by way of example. In other words, the embodiments of the frame described herein are not limited to frame structures for aircraft, however, and may be relied upon as frame structures for both airborne and ground-based crafts, vehicles, etc. The features of the embodiments described herein are representative and, in alternative embodiments, certain features and elements may be added or omitted. Additionally, modifications to aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present invention defined in the following claims, the scope of which are to be accorded the broadest interpretation so as to encompass modifications and equivalent structures.
This application claims priority to and the benefit of U.S. Provisional Application No. 63/167,885, filed Mar. 30, 2021, the entire contents of which is hereby incorporated herein by reference.
This invention was made with government support under Grant No. DE-EE0008706 awarded by the United States Department of Energy. The government has certain rights in the invention.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2022/071087 | 3/11/2022 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63167885 | Mar 2021 | US |
