Patent Application
20080137315
This application is based on and claims priority of Japanese Patent Application No.2006-332975 filed on Dec. 11, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an electronic component device and a method of mounting an electronic component, and more particularly to an electronic component device constructed by mounting an electronic component such as a semiconductor device or a capacitor on a wiring substrate and a method of mounting the same.
2. Description of the Related Art
In the prior art, there is an electronic component device constructed by mounting an electronic component such as a semiconductor device or a capacitor on a wiring substrate. The electronic component is bonded to a wiring pattern of the wiring substrate by mainly using solder, thereby being mounted. As shown in
As the arts related to this, Patent Literature 1 (Japanese Patent Application Laid-open Publication No. 2005-216884) discloses that a plurality of first chip components (e.g., chip capacitors) each having a pair of electrodes are mounted on a wiring pattern of a circuit substrate by solder, and second chip components (e.g., chip resistors) are mounted on the first chip components in a multilayer stack structure.
Also, Patent Literature 2 (Japanese Patent Application Laid-open Publication No. 2000-261123) discloses a mounting structure in which a chip resistor is arranged on a printed wiring board via thick glass film functioning as a spacer in between, and component electrodes on the side surfaces of the chip resistor are bonded to a soldering pad of the printed wiring board by solder.
Recently, a higher-density and higher-performance of electronic component device are demanded, and hence to mount a smaller-sized electronic component on a wiring substrate is required. However, the electronic component of a smaller size (of, for example, not more than 0.6 mm×0.3 mm) causes various problems when such electronic component is mounted to be bonded by solder.
In the case that the capacitor component 400 as mentioned above and shown in
It is an object of the present invention to provide an electronic component device and a method of mounting an electronic component, in which an electronic component can be mounted on a wiring substrate with high reliability, even if the electronic component is of an extremely small size.
The present invention is concerned with an electronic component device, which includes a wiring substrate having a wiring pattern, an electronic component mounted on the wiring pattern of the wiring substrate and provided with an electrode on a side surface thereof, and a gold bump provided on the wiring pattern of side neighborhood of the electrode of the electronic component and bonded to the electrode of the electronic component and the wiring pattern, wherein the electrode of the electronic component is electrically connected to the wiring pattern through the gold bump.
According to the present invention, the electronic component (such as a semiconductor device or a capacitor component) provided with the electrode on a side surface thereof is mounted on the wiring pattern of the wiring substrate, and the electrode of the electronic component is electrically connected to the wiring pattern of the wiring substrate through the gold bump provided in side neighborhood of the electrode.
In the present invention, unlike a bonding method using fluidic solder, since the gold bump hardly flow, there is no possibility that a lifting failure, a misalignment failure, or a bridge failure occurs, even in the case of mounting of an electronic component of an extremely small size (for example, not more than 0.6 mm×0.3 mm). Therefore, this enables mounting the electronic component of extremely small size on the wiring substrate with high reliability and high yield.
The electronic component device of the present invention is manufactured by temporarily fixing the electronic component on the wiring substrate, and then forming the gold bump on the wiring pattern of side neighborhood of the electronic component by the wire bump method. The formation of the gold bump by the wire bump method can set processing temperature low and also achieve higher bond strength rather than the case of mounting with solder. Therefore, the reliability of the electronic component device can be improved. Moreover, since the solder is not used in the present invention, there are advantages in which a printing apparatus and a reflow apparatus, or the like are not need, thereby cost reduction is achieved, and it can contribute to the reduction of environmental pollutant.
According to one mode of the present invention, the electrical component device may have a structure in which a plurality of electronic components are mounted on the wiring substrate, the gold bump is provided for each of the electrodes of a plurality of electronic components, and a plurality of electronic components may be connected through the wiring pattern.
Also, according to another mode of the present invention, a plurality of electronic components on the wiring substrate may be directly connected through the gold bump arranged therebetween.
As described above, in the present invention, since the electronic component is bonded to the wiring substrate with a gold bump, the electronic component can be mounted on the wiring substrate with high reliability without any problems even if the electronic component is of an extremely small size.
Embodiments of the present invention will be explained with reference to the accompanying drawings hereinafter.
As shown in
The capacitor component 20 is a multilayer capacitor chip, and a capacitor section is constructed by stacking a plurality of first electrode layers 24 and a plurality of second electrode layers 26 via dielectric layers 28 therebetween. A plurality of first electrode layers 24 are connected to a first electrode 20a at one end side, and a plurality of second electrode layers 26 are connected to a second electrode 20b at the other end side.
The capacitor component 20 is arranged on the wiring pattern 12 in a manner that the first electrode 20a and the second electrode 20b are aligned side by side. Moreover, gold bumps 14 which are bonded to the first electrode 20a and the second electrode 20b and the wiring pattern 12 are respectively formed on the wiring pattern 12 of each side neighborhood of the first electrode 20a and the second electrode 20b of the capacitor component 20. Thereby, the first electrode 20a and the second electrode 20b of the capacitor component 20 are electrically connected to the wiring pattern 12 of the wiring substrate 5 through the gold bumps 14.
The gold bumps 14 are formed by a wire bump method (or a wire bonding method), after the capacitor component 20 is temporarily fixed to be aligned on the wiring pattern 12 of the wiring substrate 5. Detailed description will be given below. First, a predetermined length of gold wire is drawn out from a capillary of a wire bonder, and an end portion of the gold wire is spherically shaped by electric discharge. Then, the capillary is moved down so that the end spherical portion of the gold wire is disposed on the wiring pattern 12 of side neighborhood of the capacitor component 20, and the end spherical portion is bonded to the wiring pattern 12 as well as the first electrode 20a and the second electrode 20b of the capacitor component 20 by heating and ultrasonic vibration. Then, the gold wire is clamped while the capillary is moved up, and the wire is cut away immediately above the end spherical portion to thereby obtain the gold bump 14.
Incidentally, the capacitor component 20 having a pair of the electrodes 20a and 20b is shown for example in
According to the electronic component device 1 according to the first embodiment, as described above, the gold bumps 14 are formed by the wire bump method in a state that the capacitor component 20 is temporarily fixed on the wiring substrate 5, and the first electrode 20a and the second electrode 20b on the side surfaces of the capacitor component 20 are electrically connected to the wiring pattern 12 of the wiring substrate 5 through the gold bumps 14. Unlike a bonding method using fluidic solder, since the gold bumps 14 hardly flow, and the gold bumps 14 can be independently arranged in the side neighborhood of the temporarily-fixed capacitor component 20, there is no possibility that a lifting failure, a misalignment failure, a bridge failure, or the like occurs.
Therefore, this enables mounting a microminiature electronic component with high reliability and high yield without any problems, even in the case of mounting an electronic component of an extremely small size (of, for example, 0.4 mm×0.2 mm or 0.2 mm×0.1 mm).
Also, in the solder bonding in the prior art, when a repair job for modifying a specified portion on the wiring substrate is carried out, there is a problem that solder is easily to remain on the wiring substrate when the electronic component is detached. However, the gold bumps formed by the wire bump method are easily removed from the wiring substrate when the electronic component is detached. Accordingly, the efficiency and yield of the repair job can be increased. Moreover, bonding with the gold bumps by the wire bump method can improve the reliability of bonding of the electronic component, because of achieving higher bond strength than that of the solder bonding.
Further, in the first embodiment, since the solder is not used, a printing apparatus, a reflow apparatus, or the like is not need, thereby cost reduction is achieved, and it can contribute to the reduction of environmental pollutant.
Moreover, the formation of the gold bumps by the wire bump method can reduce damage to the electronic component, and the reliability of the electronic component device can be improved, because processing temperature can be set lower than the solder bonding method.
An electronic component mounted in the second embodiment is an active component, and description will be given taking the semiconductor device as an example. As shown in
In the second embodiment, as shown in
An electronic component device 2 according to the second embodiment is constructed by this manner. The second embodiment achieves effects similar to those of the first embodiment. In addition, in the wire bump method, the gold bumps 14 can be independently arranged with small pitches of the order of 40 μm or less. Therefore, the gold bumps 14 can be arranged to be bonded to each electrodes 30a of the semiconductor device 30 (
The processing temperature upon bonding with the solder is between 300 to 330° C. in the prior art. In particular, in a case that a high-performance semiconductor device is mounted, damage to the semiconductor device may become a problem. However, the temperature for the formation of the gold bumps by the wire bump method is between 100 to 175° C., therefore even in the case of mounting the high-performance semiconductor device, it causes no damage to the semiconductor device.
As shown in
An inductor component 40 provided with a pair of electrodes 40a on the side surfaces thereof is mounted on the wiring pattern 12 connected to the first semiconductor device 31. Also in the inductor component 40, the gold bumps 14 are formed on the wiring pattern 12 of the side neighborhood of the electrodes 40a, and thereby the electrodes 40a of the inductor component 40 are electrically connected to the wiring pattern 12 through the gold bumps 14. The first semiconductor device 31 has the function of a power supply controller, and the inductor component 40 is interposed in a power supply line to function as an anti-noise filter.
Further, a second semiconductor device 32 provided with a plurality of electrodes 32a on the side surfaces thereof is mounted on the wiring pattern 12 of the right side of the wiring substrate 5, and the electrodes 32a of the second semiconductor device 32 are electrically connected to the wiring pattern 12 through the gold bumps 14 provided on the wiring pattern 12 of the neighborhood of the electrodes 32a.
Referring additionally to the partial plan view of
The gold bumps 14 are arranged on the wiring patterns 12 of the side neighborhood of the pair of the electrodes 21a of each of the first capacitor components 21, and thereby the electrodes 21a of the first capacitor components 21 are electrically connected to the wiring patterns 12 through the gold bumps 14. In this manner, the three first capacitor components 21 are electrically connected in parallel through the gold bumps 14 and the wiring patterns 12.
Further, one of electrodes 22a of a second capacitor component 22 is connected through the gold bump 14 to the wiring pattern 12 connected to the second semiconductor device 32 and the first capacitor components 21. Moreover, the other electrode 22a of the second capacitor component 22 is connected through the gold bump 14 to the wiring pattern 12 connected to the first semiconductor device 31.
Moreover, each of electrodes 23a of two third capacitor components 23, which are different in electrical polarity are arranged to face each other on the wiring pattern 12 of the wiring substrate 5, and the two third capacitor components 23 are mounted as electrically connected in series. The electrodes 23a of the third capacitor components 23 are likewise electrically connected to the wiring pattern 12 through the gold bumps 14.
The second semiconductor device 32 functions as a CPU (Central Processing Unit) and the first capacitor components 21 connected thereto function as decoupling capacitors to reduce high-frequency noise.
Moreover, solder resists 16 are formed in regions around the first and second semiconductor devices 31 and 32, the inductor component 40 and the first, second and third capacitor components 21, 22 and 23. The regions between the solder resists 16 and the electronic components may be filled with a resin and thereby encapsulated therein. Incidentally, the solder resists 16 are omitted from the partial plan view of
In the third embodiment, as described above, a plurality of electronic components (namely, the first and second semiconductor devices 31 and 32, the inductor component 40 and the first, second and third capacitor components 21, 22 and 23) are mounted on the wiring substrate 5, and the gold bump 14 is provided for each of the electrodes of the electronic components. In this manner, a plurality of electronic components are connected each other through the gold bumps 14 and the wiring patterns 12.
In the electronic component device 3a according to the third embodiment, even if various electronic components of extremely small size are used, the electronic components can be mounted on the wiring substrate 5 with high reliability by the reason mentioned above. Accordingly it can easily meet demands for high density and high performance of the electronic component device.
Incidentally, a form in which, besides the capacitor components and the inductor components, various passive components such as a resistor component are mounted in the same manner may be employed.
Referring additionally to the partial plan view of
Further, one gold bump 14 is arranged between the electrodes 23a, facing each other, of the two third capacitor components 23 connected in series, and the two third capacitor components 23 are directly connected in series through the gold bump 14 without the use of the wiring pattern 12.
As mentioned above, in a portion where the passive components each having a pair of electrodes at both ends are electrically connected in series, the electrodes of a plurality of passive components, facing each other, may be directly connected through the gold bump. Moreover, in a portion where the electrodes of the passive components each having a pair of electrodes at both ends are electrically connected in parallel as arranged side by side to lateral direction, a plurality of passive components may be directly connected through the gold bumps bonded to each other by arranging a plurality of passive components in contact with each other and providing the gold bumps for each individual electrode. Since other structural elements are the same as those of the third embodiment (see
In the fourth embodiment, the inductor component 40 can achieve its full performance since the first semiconductor device 31 is connected directly to the inductor component 40 through the gold bump 14. Moreover, capacitor characteristics can be improved since the first capacitor components 21 connected in parallel are directly connected through the gold bumps 14 and the third capacitor components 23 connected in series are directly connected through the gold bump 14.
Since other configurations are the same as those of the fourth embodiment (
In the fifth embodiment, the three first capacitor components 21 connected in parallel are connected directly to the second semiconductor device 32 through the gold bumps 14. This enables achieving extremely low parasitic inductance, as compared to a connection method using the wiring pattern. Therefore, the first capacitor components 21 achieve a more sufficient performance to function as the decoupling capacitors for the second semiconductor device 32 that operates at high speed.
Since other configurations are the same as those of the sixth embodiment (
As mentioned above, as explained in the fourth to seventh embodiments (
Moreover, a predetermined portion of the electrodes of a plurality of electronic components may be bonded with solder, or all electrodes of the electronic components may be connected to the wiring pattern through the gold bumps without any use of solder bonding.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-332975 | Dec 2006 | JP | national |
