Patent Application
20150214204
The present invention relates to an electronic device and a method for fabricating an electronic device.
An electronic device may comprise a first semiconductor chip and a second semiconductor chip. Both of these semiconductor chips may be attached to a carrier. However, the first and second semiconductor chips maybe attached to the carrier using different attaching techniques which may lead to one or more of increased complexity of the fabrication process and increased cost of the electronic device. For these and other reasons there is a need for the present invention.
The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It may be evident, however, to one skilled in the art that one or more aspects of the embodiments may be practiced with a lesser degree of the specific details. In other instances, known structures and elements are shown in schematic form in order to facilitate describing one or more aspects of the embodiments. In this regard, directional terminology, such as “top”, “bottom”, “left”, “right”, “upper”, “lower” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In addition, while a particular feature or aspect of an embodiment may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application, unless specifically noted otherwise or unless technically restricted. Furthermore, to the extent that the terms “include”, “have”, “with” or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprise”. The terms “coupled” and “connected”, along with derivatives thereof may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other; intervening elements or layers may be provided between the “bonded”, “attached”, or “connected” elements. Also, the term “exemplary” is merely meant as an example, rather than the best or optimal.
The semiconductor chip(s) described further below may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits and/or passives, logic integrated circuits, control circuits, microprocessors, memory devices, etc.
The embodiments of an electronic device and a method for fabricating an electronic device may use various types of semiconductor chips or circuits incorporated in the semiconductor chips, among them AC/DC or DC/DC converter circuits, power MOS transistors, diodes, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analogue integrated circuits, mixed signal integrated circuits, sensor circuits, MEMS (Micro-Electro-Mechanical-Systems), power integrated circuits, chips with integrated passives, etc. The embodiments may also use semiconductor chips comprising MOS transistor structures or vertical transistor structures like, for example, IGBT (Insulated Gate Bipolar Transistor) structures or, in general, transistor structures in which at least one electrical contact pad is arranged on a first main face of the semiconductor chip and at least one other electrical contact pad is arranged on a second main face of the semiconductor chip opposite to the first main face of the semi-conductor chip. Moreover, the embodiments of insulation materials may, for example, be used for providing insulation layers in various types of enclosures and insulation for electrical circuits and components, and/or for providing insulation layers in various types of semiconductor chips or circuits incorporated in semiconductor chips, including the above mentioned semiconductor chips and circuits.
The semiconductor chip(s) can be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, GaN, or from any other semiconductor material, and, furthermore, may contain one or more of inorganic and organic materials that are not semiconductors, such as for example insulators, plastics or metals.
The semiconductor chip(s) considered herein may be thin. In order to allow handling or manipulation of the semiconductor chip, e.g. handling/manipulation required for packaging, eWLP (embedded Wafer Level Packaging), or semiconductor device assembly, the semiconductor chip may form part of a composite chip. A composite chip may comprise the semiconductor chip and a reinforcing chip secured to the semiconductor chip. The reinforcing chip adds stability and/or strength to the composite chip to make it manageable.
The devices described below may include one or more semiconductor chips. Byway of example, one or more semiconductor power chips may be included. Further, one or more logic integrated circuits may be included in the devices. The logic integrated circuits may be configured to control the integrated circuits of other semiconductor chips, for example the integrated circuits of power semiconductor chips. The logic integrated circuits may be implemented in logic chips.
The semiconductor chip(s) may have contact pads (or electrodes) which allow electrical contact to be made with the integrated circuits included in the semiconductor chip(s). The electrodes may be arranged all at only one main face(s) of the semiconductor chip(s) or at both main faces of the semiconductor chip(s). They may include one or more electrode metal layers which are applied to the semiconductor material of the semiconductor chip(s). The electrode metal layers may be manufactured with any desired geometric shape and any desired material composition. For example, they may comprise or be made of a material selected of the group of Cu, Ni, NiSn, Au, Ag, Pt, Pd, an alloy of one or more of these metals, an electrically conducting organic material, or an electrically conducting semiconductor material.
The semiconductor chip(s) may be bonded to a carrier. The carrier may be a (permanent) device carrier used for packaging. The carrier may comprise or consist of any sort of material as, for example, ceramic or metallic material, copper or copper alloy or iron/nickel alloy. The carrier can be connected mechanically and electrically with one contact element of the semiconductor chip(s). The semiconductor chip(s) maybe connected to the carrier by one or more of re-flow soldering, vacuum soldering, diffusion soldering, or adhering by means of a conductive adhesive or a non-conductive adhesive. If diffusion soldering is used as the connection technology between the semiconductor chip(s) and the carrier, solder materials may be used which result in inter-metallic phases at the interface between the semiconductor and the carrier due to interface diffusion processes after the soldering process. In case of copper or iron/nickel carriers it may therefore be desirable to use solder materials comprising or consisting of AuSn, AgSn, CuSn, AgIn, AuIn or CuIn. Alternatively, if the semiconductor chip(s) are to be adhered to the carrier, conductive adhesives can be used. The adhesives can, for example, be based on epoxy resins or other suitable glues. The adhesives can be enriched with particles of gold, silver, nickel or copper to enhance their electrical conductivity.
The contact elements of the semiconductor chip(s) may comprise a diffusion barrier. The diffusion barrier prevents in case of diffusion soldering that the solder material diffuses from the carrier into the semiconductor chip(s). A thin titanium layer on the contact element may, for example, effect such a diffusion barrier.
Bonding the semiconductor chip(s) to the carrier may e.g. be done by soldering, gluing, or sintering. In case the semiconductor chip(s) are attached by soldering, a soft solder material or, in particular, a solder material capable of forming diffusion solder bonds may be used, for example a solder material comprising one or more metal materials selected from the group of Sn, SnAg, SnAu, SnCu, In, InAg, InCu and InAu.
The semiconductor chip(s) may be covered with an encapsulation material in order to be embedded in an encapsulant (artificial wafer) for eWLP processing or after being bonded to a device carrier (substrate). The encapsulation material may be electrically insulating. The encapsulation material may comprise or be made of any appropriate plastic or polymer material such as, e.g., a duroplastic, thermoplastic or thermosetting material or laminate (prepreg), and may e.g. contain filler materials. Various techniques may be employed to encapsulate the semiconductor chip(s) with the encapsulation material, for example compression molding, injection molding, powder molding, liquid molding or lamination. Heat and/or pressure may be used to apply the encapsulation material.
In several embodiments layers or layer stacks are applied to one another or materials are applied or deposited onto layers. It should be appreciated that any such terms as “applied” or “deposited” are meant to cover literally all kinds and techniques of applying layers onto each other. In particular, they are meant to cover techniques in which layers are applied at once as a whole like, for example, laminating techniques as well as techniques in which layers are deposited in a sequential manner like, for example, sputtering, plating, molding, CVD, etc.
In the following description and claims different embodiments of a method for fabricating an electronic device are described as a particular sequence of processes or measures, in particular in a flow diagram. It is to be noted that the embodiments should not be limited to the particular sequence described. Particular ones or all of different processes or measures can also be conducted simultaneously or in any other useful and appropriate sequence.
An embodiment of an electronic device may comprise a first semiconductor chip and a second semiconductor chip, each attached to a carrier. The carrier may comprise a leadframe. However, the first and the second semiconductor chips may be attached to the carrier using different die attach processes. In particular, the first semiconductor chip may be attached to the carrier using a solder process. According to an embodiment, a diffusion solder process may be used. The second semiconductor chip however may be attached to the carrier using a gluing process using an adhesive. According to another embodiment, attaching the second semiconductor chip comprises a sintering process.
The first and second semiconductor chips may be individually electrically connected to the carrier or may be individually electrically insulated from the carrier. For example, a conductive glue may be used to electrically connect the second semiconductor chip to the carrier. Alternatively, an insulation layer may be used to provide electrical insulation.
The first and second semiconductor chips may each comprise a first main face, a second main face opposite the first main face and side faces connecting the first and second main face. The semiconductor chips may be attached to the carrier such that the second main faces face the carrier and the first main faces are located in the same plane, that is they are coplanar. Coplanarity of the first main faces of the first and second semiconductor chips may be very good. That means, a deviance of a first plane spanned by the first main face of the first semiconductor chip from a second plane spanned by the first main face of the second semiconductor chip may be less than 40 μm, or less than 30 μm, or less than 25 μm, or even less than 20 μm. Furthermore, each of the first and second plane may enclose an angle with an ideal plane of orientation, wherein each angle may be less than 2°, or less than 1°, or less than 0.5° or may even be essentially zero, meaning that the first and second plane are essentially parallel.
The first and second semiconductor chips may exhibit a difference in thickness measured from the first main face to the second main face. The difference in thickness may be large and may in particular be larger than 5 μm, larger than 10 μm, larger than 20 μm, larger than 30 μm, or even larger than 40 μm.
In order for two semiconductor chips of different thickness in an electronic device to have coplanar first main faces, a carrier surface may comprise a cavity designed for accommodating one of the semiconductor chips. For example, the second semiconductor chip may be accommodated in the cavity.
As stated above the second semiconductor chip comprised in an electronic device may be attached to the carrier using a glue. According to an embodiment the glue may completely cover the second main face and all side faces of the second semiconductor chip from the second main face up to the first main face. Such a thorough coverage with glue may improve heat dissipation away from the second semiconductor chip. For example, conductive glue may have 23 times the heat conductance of epoxy. Furthermore, the glue may comprise an upper face coplanar with the first main face of the second semiconductor chip.
According to an embodiment an electronic device may comprise at least a third semiconductor chip. The first main face(s) of the one or more further semiconductor chip(s) may be coplanar with the main faces of the first and second semiconductor chips.
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Then the semiconductor chips 10, 20 and the carrier 40 may be brought into contact such that the second main face 12 of the first semiconductor chip 10 contacts the diffusion solder deposit 41 and the second main face 22 of the second semiconductor chip 20 contacts the glue deposit 42. Note that during the attachment process the semiconductor chips 10, 20 are still connected to the transfer means 30. Furthermore, attaching the semiconductor chips 10, 20 may be done simultaneously in a parallel process.
Attaching may comprise applying one or more of heat and pressure to the diffusion solder deposit 41 and the glue deposit 42. As shown in
Diffusion soldering of the first semiconductor chip 10 may comprise Advanced Diffusion Soldering (ADS). In particular, ADS may require heat of no more than 260° C., or even no more than 250° C. due to the use of low temperature solder. Standard diffusion soldering may require higher or even much higher temperatures which may not be suitable for gluing. Due the comparably low temperature requirements of ADS diffusion soldering of the first semiconductor chip 10 and gluing of the second semiconductor chip 20 to the carrier 40 respectively can be carried out in one simultaneous heating step.
After hardening of the solder bond and the glue the transfer means 30 may be removed from the first main faces 11, 21. Transfer means 30 may for example comprise a thermo release foil which loses its adhesive properties upon a temperature change. Furthermore, transfer means 30 may for example comprise a UV foil which changes its adhesive properties under UV illumination. Furthermore, transfer means 30 may comprise a plate, for example a glass plate. The plate may be covered with an adhesion means, like a glue or an adhesive tape, designed to adhere to semiconductor chips. Transfer means 30 may further comprise a metal plate. The metal plate may be designed to homogeneously apply a temperature to semiconductor chips adhered to the transfer means. The metal plate may further be designed to stabilize an adhesive foil and allow for a homogeneously pressing adhered semiconductor chips onto a carrier during an attachment process. Removing the adhesive foil from the semiconductor chips may comprise applying mechanical force to it or it may simply comprise peeling off the adhesive foil from the first main faces 11, 21.
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According to a further embodiment not shown here third semiconductor chip 90 may be attached to carrier 80 using a solder analogously to first semiconductor chip 60. In any case, first main faces of all semiconductor chips 60, 70, 90 are coplanar due to them being connected to transfer means 30 during the attachment process.
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For the method of fabricating an electronic device using a transfer means 30 this tilt may be smaller than it would be possible when using a serial process like a pick and place process to attach the chips 60, 70 to a carrier. In particular, the angles alpha, beta may be smaller than 2°, smaller than 1°, smaller than 0.5°, smaller than 0.1° and may even be essentially zero.
Furthermore, due to the presence of the transfer means during the attachment of chips 60, 70 on the carrier the first main faces 61, 71 may exhibit a height deviation from plane P which may be less than 40 μm, or less than 30 μm, or less than 25 μm, or even less than 20 μm and may even be essentially zero.
With respect to
Method 600 further comprises a second step 602 comprising simultaneously attaching the first and second semiconductor chips to the carrier. Attaching the first semiconductor chip may comprise soldering and attaching the second semiconductor chip may comprise gluing. Soldering and gluing may comprise applying heat in a single process step to both a solder reservoir and a glue reservoir. Such a simultaneous soldering and gluing step may be highly cost efficient compared to a serial process. The costs of a serial process may be a factor two higher than the costs of the parallel attachment process of method 600.
Method 600 further comprises a third step 603 comprising removing the transfer means from the first and second semiconductor chips. According to an embodiment of method 600 the transfer means is removed after the solder and the glue applied in step 602 are cured and the first and second semiconductor chips are firmly attached to the carrier.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.
