Embodiments pertain to packaging of integrated circuits (ICs). Some embodiments relate to interconnection of ICs using an IC package that includes a glass core.
Electronic systems often include integrated circuits (ICs) that are interconnected and packaged as a subassembly. It is desired to integrate multiple types of IC dice into a single electronic package to create an efficient system in a package. There is demand for miniaturization of form factor for such packages yet there is also demand for increased levels of integration for high performance. These demands are driving sophisticated packaging approaches in the semiconductor industry. Die partitioning enables miniaturization of small form factor and can provide high performance without yield issues seen with other methods but needs fine die-to-die interconnections.
Embedded Multi-die Interconnect Bridge (EMIB) enables a lower cost and simpler packaging approach for very high-density interconnects between heterogeneous dice on a single package. In EMIB, instead of an expensive silicon interposer with through silicon vias (TSVs), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate.
Future generations of dice partitioning for electronic packaging may need several bridges that can connect the dice at much finer bump pitches (25 microns or lower) than are currently provided by EMIB packaging. The EMIB approach suffers from a high cumulative Bump Thickness Variation (BTV), and as the number of bridges to be embedded increases, the cost of embedding the IC dice will increase and the yield of EMIB assemblies will decrease.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
To meet the demand for increased functional complexity in smaller devices, manufacturers integrate multiple types of IC dice in a single IC package to create an efficient electronic system in a package. Future generations of electronic packaging will need interconnection for IC dice at much finer bump pitches than is currently available.
An option for enabling fine die-to-die interconnections is to incorporate a thin glass core into the substrate package. A glass core offers several advantages over conventional epoxy cores including a higher plated through hole (PTH) density, lower signal losses, lower total thickness variation (TTV), among others. However, handling a thin glass core (on the order of 400-500 microns) at a panel level (510×515 millimeters) is a significant challenge. Thus, alternative options that do not require repurposing existing substrate manufacturing infrastructure for glass handling of thin glass cores would lead to significant reductions in capital expenditure for manufacturers.
An approach to ease the stringent handling requirements associated with handling of full panel, thin glass cores is to encase an array of glass core patches of arbitrary size (unit sized, quarter panel sized, etc.) within a mold or epoxy or dielectric matrix. By using such an approach, the soft material can accommodate existing substrate manufacturing infrastructure panel handling configurations and manufacturers will still reap the benefits of using glass core in package substrate (e.g., low TTV, good dimensional stability, high PTH density, etc.).
The electronic system 100 includes multiple IC dice. Only two IC dice (106, 108) are shown in the example for simplicity, and an actual implementation may have many IC die. The multiple IC die can include central processing unit tiles and high bandwidth memory tiles. The IC die may be embedded or encapsulated in a mold layer 110 with the contact pads (e.g., I/O pads) of the IC die exposed.
The glass core patch 102 includes through glass vias (TGVs) 116. The TGVs 116 include electrically conductive material (e.g., metal) the extends from the top surface of the glass core patch 102 to the bottom surface of the glass core patch. The encapsulating layer 104 includes through layer vias (TLVs) 118 connected to each end of the TGVs 116. The electronic system 100 also includes a redistribution layer (RDL) 112. The RDL 112 includes a dielectric and one or more layers of electrically conductive interconnect 114. In some examples, the RDL 112 is first layer interconnect (FLI). The electrically conductive interconnect 114 of the RDL 112 electrically connects one or more contact pads 126 of the IC dice to one or more of the TGVs 116 of the glass core patch 102.
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The methods, devices, and systems described herein provide interconnect that can accommodate high frequency signals while providing very dense signal routing. Encapsulating glass core patches is a robust approach for IC packaging, which relaxes the handling requirements for manufacturing. This reduces the need for specialized tooling to fabricate the IC packages.
An example of an electronic device using assemblies with system level packaging as described in the present disclosure is included to show an example of a higher level device application.
In one embodiment, processor 410 has one or more processing cores 412 and 412N, where N is a positive integer and 412N represents the Nth processor core inside processor 410. In one embodiment, system 400 includes multiple processors including 410 and 405, where processor 405 has logic similar or identical to the logic of processor 410. In some embodiments, processing core 412 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 410 has a cache memory 416 to cache instructions and/or data for system 400. Cache memory 416 may be organized into a hierarchal structure including one or more levels of cache memory.
In some embodiments, processor 410 includes a memory controller 414, which is operable to perform functions that enable the processor 410 to access and communicate with memory 430 that includes a volatile memory 432 and/or a non-volatile memory 434. In some embodiments, processor 410 is coupled with memory 430 and chipset 420. Processor 410 may also be coupled to a wireless antenna 478 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface 478 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra-Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In some embodiments, volatile memory 432 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
Memory 430 stores information and instructions to be executed by processor 410. In one embodiment, memory 430 may also store temporary variables or other intermediate information while processor 410 is executing instructions. In the illustrated embodiment, chipset 420 connects with processor 410 via Point-to-Point (PtP or P-P) interfaces 417 and 422. Chipset 420 enables processor 410 to connect to other elements in system 400. In some embodiments of the invention, interfaces 417 and 422 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In some embodiments, chipset 420 is operable to communicate with processor 410, 405N, display device 440, and other devices 472, 476, 474, 460, 462, 464, 466, 477, etc. Buses 450 and 455 may be interconnected together via a bus bridge 472. Chipset 420 connects to one or more buses 450 and 455 that interconnect various elements 474, 460, 462, 464, and 466. Chipset 420 may also be coupled to a wireless antenna 478 to communicate with any device configured to transmit and/or receive wireless signals. Chipset 420 connects to display device 440 via interface (I/F) 426. Display 440 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor 410 and chipset 420 are merged into a single SOC. In one embodiment, chipset 420 couples with (e.g., via interface 424) a non-volatile memory 460, a mass storage medium 462, a keyboard/mouse 464, and a network interface 466 via I/F 424 and/or I/F 426, I/O devices 474, smart TV 476, consumer electronics 477 (e.g., PDA, Smart Phone, Tablet, etc.).
In one embodiment, mass storage medium 462 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 466 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra-Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
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The devices, systems, and methods described can provide improved routing of interconnection between ICs for a multichip package in addition to providing improved transistor density in the IC die. Examples described herein include two or three IC die for simplicity, but one skilled in the art would recognize upon reading this description that the examples can include more than three IC die.
Example 1 includes subject matter (such as an electronic device) comprising a mold layer that includes multiple integrated circuit (IC) dice having contact pads, a glass core patch embedded in encapsulating material that surrounds the top, bottom, and sides of the glass core patch, and a first redistribution layer arranged between the first mold layer and the glass core patch. The first redistribution layer includes electrically conductive interconnect that electrically connects one or more contact pads of the IC dice to the glass core patch.
In Example 2, the subject matter of Example 1 optionally includes a glass core patch that includes through glass vias (TGVs).
In Example 3, the subject matter of Example 2 optionally includes a first redistribution layer that includes a die-to-die bridge device electrically connected to one or more pads of the IC dice and electrically connected to one or more of the TGVs.
In Example 4, the subject matter of one or both of Examples 2 and 3 optionally include an encapsulating layer that includes through layer vias, with a first through layer via connected to a first end of a TGV, and a second through layer via connected to a second end of the TGV.
In Example 5, the subject matter of one or any combination of Examples 1-4 optionally includes a second redistribution layer arranged on an opposite side of the glass core patch from the first redistribution layer. The first redistribution layer includes first level interconnect, and the second redistribution layer includes one or both of second level interconnect and mid-level interconnect.
In Example 6, the subject matter of one or any combination of Examples 1-5 optionally includes a glass core patch includes silicate glass.
In Example 7, the subject matter of one or any combination of Examples 1-6 optionally includes encapsulating material that includes at least one of a mold material or a dielectric material.
In Example 8, the subject matter of one or any combination of Examples 1-7 optionally includes an encapsulating material that includes epoxy.
Example 9 includes subject matter (such as a method of forming an electronic system) or can optionally by combined with one or any combination of Examples 1-8 to include such subject matter, comprising forming a glass core, patterning the glass core with one or more through glass vias (TGVs), separating the glass core into multiple glass core patches, encapsulating the glass core patches in an encapsulating material, attaching the glass core patches to respective redistribution layers to form glass core patch and redistribution layer assemblies, and dicing to separate the glass core patch and redistribution layer assemblies.
In Example 10, the subject matter of Example 9 optionally includes forming one or more vias in the encapsulating material that connect to the one or more TGVs. The encapsulating material covers a top surface, bottom surface, and sidewalls of each of the glass core patches.
In Example 11, the subject matter of one or both of Examples 9 and 10 optionally includes laminating a carrier with the encapsulating material, placing a bottom side of the glass core patches on the laminated carrier, covering a top side and side walls of the glass core patches with the encapsulating material, and removing the encapsulated glass core patches from the carrier.
In Example 12, the subject matter of one or any combination of Examples 9-11 optionally includes attaching at least one IC die to the respective redistribution layers. The respective redistribution layers provide electrical continuity between at least one pad of the IC die and at least one TGV of a glass core patch.
In Example 13, the subject matter of one or any combination of Examples 9-12 optionally includes separating the glass core into glass core patches of different sizes.
In Example 14, the subject matter of one or any combination of Examples 9-13 optionally includes attaching a first side of the glass core patches to a first level interconnect redistribution layer and connecting the second side of the glass core patches to a second level interconnect redistribution layer or a mid-level interconnect redistribution layer.
In Example 15, the subject matter of one or any combination of Examples 9-14 optionally includes encapsulating the glass core patches with at least one of a dielectric material, a mold material, or an epoxy.
In Example 16, the subject matter of one or any combination of Examples 9-15 optionally includes adding the redistribution layers using bulk processing.
Example 17 includes subject matter (such as a packaged electronic system) or can optionally be combined with one or any combination of Examples 1-16 to include such subject matter, comprising a mold layer that includes multiple integrated circuit (IC) dice, wherein the IC dice include at least one processor die and at least one memory die, an antenna coupled to one or more of the IC dice, a glass core patch layer and a first level interconnect layer. The glass core patch layer includes a glass core patch encapsulated within an encapsulating material and including multiple electrically conductive through glass vias (TGVs), and multiple through layer vias in the encapsulating material contacting the TGVs. The first level interconnect layer is arranged between the mold layer and the glass core patch layer, wherein the first level interconnect layer provides electrical continuity between the through layer vias and pads of the IC dice.
In Example 18, the subject matter of Example 17 optionally includes encapsulating material that covers a top side, a bottom side, and sidewalls of the glass core patch.
In Example 19, the subject matter of one or both of Examples 17 and 18 optionally includes a first level interconnect that includes a die-to-die bridge connector in electrical contact with at least two IC dice of the multiple IC dice and in electrical contact with at least one TGV of the glass core patch.
In Example 20, the subject matter of one or any combination of Examples 17-19 optionally includes a second level interconnect layer, wherein the first level interconnect layer is arranged to contact a first side of the glass core patch layer, and the second interconnect layer is arranged to contact a second side of the glass core patch layer.
These non-limiting examples can be combined in any permutation or combination. The Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.