Patent Grant
10951174
The present invention relates to a high-frequency amplifier including a wire.
It has been necessary in high-frequency amplifiers to reduce the floating capacitance generated between the drain and the gate of an FET. Therefore, a structure in which a cavity is provided above an FET by using a metal frame and a metal cap has been used. Furthermore, a structure in which resin having a low dielectric constant is coated on the FET to reduce a parasitic capacitance has been also used. However, the effect of reducing the parasitic capacitance is smaller than that of the former structure. Also, the stricture of the metal cap of the former structure has a shielding effect, and also has an effect of suppressing radiation noise of the FET.
It has been also disclosed that the floating capacitance between the gate and the drain is reduced with the shielding effect by providing a wire between the gate and the drain (for example, see PTL 1). Furthermore, it has been disclosed that the floating capacitance is reduced by providing a metal above the FET plate with a gap of 0.2 μm or less therebetween to provide a cavity above the FET (for example, see PTL 2).
[PTL 1] JP H04-165655 A
[PTL 2] JP 2004-6816 A
For example, in order to enhance the high frequency characteristics of a high electron mobility transistor (HEMT: high electron mobility transistor) and obtain a sufficient power gain, it is required that a cavity or a low dielectric constant layer be provided above an FET so that floating capacitance between the gate and the drain is reduced. Furthermore, from the viewpoint of the cost, the number of materials and the manufacturing process, a structure in which wires connected to a semiconductor chip are sealed with thermosetting resin is used. However, in terms of characteristics, it is better to use a hollow structure in which a cavity is provided above a transistor by using a metal frame and a metal cap.
The present invention has been made to solve the problem as described above, and has an object to provide a high-frequency amplifier capable of reducing the floating capacitance between a gate electrode and a drain electrode and suppressing radiation noise of a transistor.
A high-frequency amplifier according to the present invention includes: a semiconductor substrate; a transistor provided on a surface of the semiconductor substrate and having a gate electrode, a source electrode and a drain electrode; first and second wirings provided on the surface of the semiconductor substrate and sandwiching the gate electrode, the source electrode and the drain electrode; plural wires passing over the gate electrode, the source electrode and the drain electrode and connected to the first and second wirings; and a sealing material sealing the transistor, the first and second wirings, and the plural wires, wherein the sealing material contains a filler, an interval distance between the plural wires is smaller than a particle diameter of the filler, and the sealing material does not intrude into a space between the plural wires and the transistor so that a cavity is formed.
In the present invention, the plural wires pass over the source electrode and the drain electrode and are connected to the first and second wirings. An interval distance between the plural wires is smaller than a particle diameter of the filler. Therefore, the sealing material does not intrude into a space between the plural wires and the transistor so that a cavity is formed. This cavity can reduce the floating capacitance between the gate electrode and the drain electrode. Furthermore, by covering the upper side of the transistor with the plural wires, it is possible to suppress radiation noise.
A high-frequency amplifier according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.
A transistor 2 is formed on the surface of a semiconductor substrate 1. A gate electrode 3 of the transistor 2 and a lead frame 4 are connected to each other by a gate wire 5. A drain electrode 6 of the transistor 2 and a lead frame 7 are connected to each other by a drain wire 8. A source electrode 9 of the transistor 2 is connected to source wirings 10 and 11. The source wiring 10 is connected to lead frames 12 and 13 by source wires 14 and 15, respectively. The source wiring 11 is connected to lead frames 16 and 17 by source wires 18 and 19, respectively.
The source wirings 10 and 11 are formed on the surface of the semiconductor substrate 1 so as to sandwich the transistor 2 therebetween. Plural wires 20 pass over the transistor 2, and are connected to the source wirings 10 and 11. A sealing material 21 seals the transistor 2, the source wirings 10 and 11, the plural wires 20, and the like. A cavity 22 into which the sealing material 21 does not intrude is formed between the plural wires 20 and the transistor 2.
First, as shown in
Next, the transistor 2, the source wirings 10 and 11, the plural wires 20 and the like are sealed with the sealing material 21. The sealing material 21 is epoxy resin containing fillers 21a of silica, and thermosetting resin having high hitting viscosity is used within a usable range. The interval distance a between the plural wires 20 is smaller than the particle diameter c of the tillers 21a. Therefore, as shown in
When a low noise FET is taken as an example of the transistor 2, the size of the transistor 2 is equal to 140 μm×140 μm. The diameter of each of the gate wire 5, the drain wire 8, the source wires 14, 15, 18 and 19, and the plural wires 20 is equal to 20 μm. The interval distance a between the plural wires 20 is equal to 30 μm or less, and the height b of the plural wires 20 is equal to 30 μm or less. The particle diameter c of the fillers 21a is larger than 30 μm.
The floating capacitance Cgd between the gate electrode 3 and the drain electrode 6 is determined by Cgd=ε0×εr×(S/L). Here, ε0 represents the permittivity of vacuum, εr represents the relative permittivity, S represents the passing area between objects, and L represents the distance between the objects. The relative permittivity εr of the sealing material 21 is equal to 3 to 4. The relative permittivity εr of the cavity 22 is approximately equal to 1 of air. Accordingly, by providing the cavity 22 as in case of the present embodiment, the floating capacitance Cgd between the gate electrode 3 and the drain electrode 6 can be reduced to ⅓ to ¼ as compared with a case where the cavity 22 is not provided. The height b of the cavity 22 to obtain the effect of reducing the floating capacitance is not limited to a specific one.
Furthermore, since the transistor 2 and the outside are mutually shielded from each other with the plural wires 20 by covering the upper side of the transistor 2 with the plural wires 20, it is possible to suppress radiation noise in which radiation leaks from the transistor 2 to the outside.
In the present embodiment, plural first wires 20a and plural second wires 20b arranged above the first wires 20a are used instead of the plural wires 20 of the first embodiment. The interval distance d between the plural first wires 20a and the plural second wires 20b is equal to or smaller than the particle diameter c of the fillers 21a so that the first and second wires 20a and 20h are not in contact with each other.
The plural second wires 20b are arranged in the gaps between the plural first wires 20a in plan view which is taken from a direction vertical to the surface of the semiconductor substrate 1. As a result, the gaps between the plural first wires 20a are embedded with the plural second wires 20b, and the wires above the transistor 2 are densified, so that an effect of shielding radio frequency interference between the transistor 2 and the outside is enhanced. Accordingly, the radiation noise in which the radiation of the transistor 2 leaks to the outside can be suppressed as compared with that in the first embodiment.
Ground wirings 23 and 24 which are independent from the source electrode 9 of the transistor 2 are provided. The ground wirings 23 and 24 are arranged outside the source electrode 9, and are not connected to the source electrode 9. The plural wires 20 pass over the transistor 2, and are connected to the ground wirings 23 and 24. The ground wiring 23 is connected to lead frames 27 and 28 by wires 25 and 26, respectively. The ground wiring 24 is connected to lead frames 31 and 32 by wires 29 and 30, respectively.
Since the plural wires 20 are arranged at low position to prevent intrusion of the sealing material 2, a slight floating capacitance is generated between the gate electrode 3 or the drain electrode 6 and the plural wires 20. Accordingly, when the plural wires 20 are connected to the source wirings 10 and 11 as in the case of the first and second embodiments, the source voltage may vary during the operation of the transistor 2 to fluctuate the floating capacitance Cgd between the gate electrode 3 and the drain electrode 6, so that the electric characteristics of the transistor 2 are influenced. In order to suppress this, in the present embodiment, the plural wires 20 are connected to the ground wirings 23 and 24 which are independent of the source electrode 9 of the transistor 2. As a result, it is possible to suppress the influence of the voltage variation of the source wirings 10 and 11 with respect to the floating capacitance between the gate electrode 3 or the drain electrode 6 and the plural wires 20.
Therefore, in the present embodiment, wires 34 crossing between the first transistor 2a and the second transistor 2b are provided. An isolating wiring 36 is formed on the surface of the semiconductor substrate 1 between the first and second transistors 2a and 2b. The wires 34 are connected to the lead frame 37, the isolating wiring 36, and another lead frame 38. The wires 34 and the isolating wiring 36 are not connected to the first and second transistors 2a and 2b.
The wires 34 act as a radio wave shield to suppress mutual interference of the electric fields generated from the first and second transistors 2a and 2b. As a result, it is possible to suppress the adverse effect on the electrical characteristics of the first and second transistors 2a and 2b.
Note that the wires 34 may be connected to the other lead frame 38 across the space between the first transistor 2a and the second transistor 2h from the lead frame 37 without providing the isolating wiring 36.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/081406 | 10/24/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2018/078686 | 5/3/2018 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5757082 | Shibata | May 1998 | A |
| 8012868 | Naval et al. | Sep 2011 | B1 |
| 8637975 | Liou | Jan 2014 | B1 |
| 20040021156 | Asano et al. | Feb 2004 | A1 |
| 20100171211 | Jao et al. | Jul 2010 | A1 |
| 20160211222 | Kuo et al. | Jul 2016 | A1 |
| Number | Date | Country |
|---|---|---|
| 1291492 | Dec 2006 | CN |
| S64-050470 | Feb 1989 | JP |
| H04-165655 | Jun 1992 | JP |
| H09-045723 | Feb 1997 | JP |
| 2004-006816 | Jan 2004 | JP |
| 2004-128125 | Apr 2004 | JP |
| 2004-289869 | Oct 2004 | JP |
| 2012-164852 | Aug 2012 | JP |
| Entry |
|---|
| International Search Report issued in PCT/JP2016/081406; dated Dec. 27, 2016. |
| Written Opinion issued in PCT/JP2016/081406; dated Dec. 27, 2016. |
| Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration issued in PCT/JP2016/081406; dated Dec. 27, 2016. |
| An Office Action; “Notification of Reasons for Refusal,” issued by the Japanese Patent Office dated Feb. 21, 2017, which corresponds to Japanese Patent Application No. 2017-503024. |
| An Office Action; “Notification of Reasons for Refusal,” issued by the Japanese Patent Office dated Jun. 20, 2017, which corresponds to Japanese Patent Application No. 2017-503024. |
| An Office Action issued by the Taiwanese Patent Office dated Dec. 28, 2017, which corresponds to Taiwanese Patent Application No. 105140209. |
| Number | Date | Country | |
|---|---|---|---|
| 20200274497 A1 | Aug 2020 | US |
