The present disclosure is directed to high-power electronics devices and methods of manufacturing same. More specifically, this disclosure relates to solid-state devices and methods of manufacturing same.
As the “moving vehicle,” industrial, commercial, and consumer markets become electrified, the need for more reliable, smaller, lighter weight, and lower cost electronics grows. Along with this trend, there is a need for controls and switches that will be used to reliably and intelligently regulate the electrics.
In the past, relays were used to provide this function, but relays are large, electro-mechanical devices with limited life and performance, unable to meet growing requirements. Relays are not a practical alternative for next generation electronics.
Solid-state switches which use MOSFETs (Metal Oxide Field Effect Transistors) are a more reliable, smaller, lighter, and cost-effective alternatives to the relays that have been used in the past. MOSFETs can be used individually or be placed in parallel to carry several hundred amps of current for the applications that require this level of power.
One of the challenges associated with transferring high power (high current) is the heat generated in the current path (I2×R). As the heat increases, the life and performance of the electronics is reduced. The key to minimizing the heat generated in the current path is to reduce the resistance in the system.
With conventional printed circuit board (PCB) packaging methods, the ability to carry high current is limited by the thickness of the copper traces. For higher current applications, the practical limit due to the processes used to manufacture PCBs, are circuit boards with four (4) ounce (144 micron thick) copper layers. In some cases, multiple layers are interconnected with electrical and thermal vias in order to be able to carry higher current and to remove heat. This causes a number of problems: PCBs get very expensive; heat becomes difficult to remove from inner layers; and mixing high current layers with signal layers gets to be very challenging.
Applicant has a proprietary technology—referred to as ASEP technology—which integrates the benefits of high current conductive metal stampings, high temperature dielectric materials, and selectively metalized circuit patterns on the surface of the dielectric materials to create a system that is often smaller, lighter, more reliable, and cost effective. ASEP technology allows designers to create high current carrying switches or modules using conventional manufacturing methods such as stamping and molding, eliminating the need for expensive (thick copper) PCBs, reducing the size of the system, and ultimately producing a very cost-effective product.
Although ASEP technology enables the design and manufacture of high-power electronics devices that may not have been possible in the past, the process requires additional capital and tooling. For lower volume applications, the additional costs may be difficult to justify. Furthermore, there may be some applications that could be produced using more conventional manufacturing methods.
Thus, there is a need for improved high-power electronics devices and improved methods of manufacturing same.
Accordingly, in an embodiment, the present disclosure provides a high-power electronics device formed of a first layer of molding compound, a second layer on top of the first layer comprising a printed circuit board, a third layer on top of the second layer formed of electrically conductive contacts, a fourth layer on top of the third layer formed of at least one electronic component, and a fifth layer on top of the fourth layer formed of molding compound.
In an embodiment, the present disclosure provides a high-power electronics device formed of a first layer of molding compound, a second layer on top of the first layer comprising a printed circuit board, a third layer on top of the second layer formed of electrically conductive contacts, a fourth layer on top of the third layer formed of at least one electronic component, and a fifth layer on top of the fourth layer formed of molding compound.
In an embodiment, the present disclosure provides a method of forming a high-power electronics device including forming a stamping out of a sheet of thick conductive material, the stamping including a lead frame portion and at least first and second electronic component mounting contacts coupled to the lead frame portion by fingers, and attaching an electronic component to the first and second electronic component mounting contacts to form an assembly, the electronic component having a plurality of terminals, wherein one of the plurality of terminals of the electronic component is not attached to the first and second electronic component mounting contacts.
The present disclosure is illustrated by way of example, and not limited, in the accompanying figures in which like reference numerals indicate similar elements and in which:
The appended drawings illustrate embodiments of the present disclosure and it is to be understood that the disclosed embodiments are merely exemplary of the disclosure, which may be embodied in various forms. Therefore, specific details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present disclosure.
A high-power electronics device 20 and improved methods of manufacturing same are provided herein. One type of high-power electronics device 20 are solid-state devices, such as a solid-state switch which requires one FET (Field Effect Transistor) for switching less than 50 Amps of power. In an embodiment, the FET is a MOSFET (Metal Oxide Field Effect Transistors).
A first method of manufacturing is shown in
Attention is invited to the first method of manufacturing shown in
As shown in
As shown in
The first electronic component mounting contact 28a has a first mounting portion 68a which is adjacent to, parallel to, and spaced from a second mounting portion 68b of the electronic component mounting contact 28b. A space 70 is defined between the first and second mounting portions 68a, 68b. One of the mounting portions 68a has a length which is greater than the length of the other mounting portion 68b such that a void 72 is provided. The circuit board contact 54 extends into the void 72. The configuration shown in
As shown in
Thereafter, as shown in
Populated conventional printed circuit boards (PCBs) 84 are provided within a PCB panel 86,
Next, as shown in
Finally, as shown in
The step shown in
In an embodiment, circuit board contact 54 (and circuit board contact 56) are eliminated and the signal terminal 74 of the electronic component 76 is directly electrically coupled to the PCB 84.
The first method of manufacturing shown in
If the embodiment with the two FETs 76 is provided, the contacts form pins. One pin may be a current sense pin, a pin may be a fault detection pin (which is used to shut the device 20 down if a fault is detected), a pin may be an enable pin (which turns current on/off), a pin may be ground, a pin may be configured to connect to a battery (power source), and a pin is configured to connect to the load (the item being driven). In an embodiment, one FET 76 is connected to the battery pin, while the other FET 76 is connected to the load pin, and the shunt 80 is connected to each of the battery and load pins. Thus, the device 20 essentially forms a smart solid-state relay.
Attention is invited to the second method of manufacturing shown in
The stamping 22 is formed as shown in
Thereafter, the contact subassemblies 24a, 24b, 24c, 24d are singulated to form individual subassemblies, see
As shown in
Thereafter, the PCB 84 is laid on top of the carrier 92, or inserted through an opening 94 in the carrier 92, such that an edge 96 of the PCB 84 is proximate to the contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and contact 56 if provided), see
As shown in
Alternatively, the step shown in
The contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and contacts 28c, 28d, second circuit board contact 56, if provided) are then electrically coupled to the PCB 84 by, for example, one or more of solder, fasteners, such as a self-tapping screws, wire or ribbon bond, and the like. Other means for coupling may also be provided.
In an embodiment, circuit board contact 54 (and circuit board contact 56, if provided) are eliminated and the signal terminal 74 of the electronic component 76 is directly electrically coupled to the PCB 84.
Finally, as shown in
The second method of manufacturing shown in
This second embodiment recognizes that solid-state devices suffer from low junction temperatures of the integrated circuits used in them. Many of these devices use FETs and Insulated-Gate Bipolar Transistors (IGBTs) which generate their own heat while operating. This self-generating heat, plus the high temperatures provided in their environment, require thermal management to transfer the heat away from the FETs so the junction temperature is not reached. Current solutions use bare-dies with intimate thermal contact to heat sinks to eliminate heat. This second embodiment solders a packaged FET/IC on thick thermally conductive contact terminal blades to transfer the heat out of the device 20. The PCB 84 may be coupled to the packaged IC terminal using a wire or ribbon bond, and the PCB 84 may be coupled to the signal terminal 74 using a wire or ribbon bond. Manufacturing of the aforementioned solid-state device is described and illustrated below.
While particular embodiments are illustrated and described with respect to the drawings, it is envisioned that those skilled in the art may devise various modifications without departing from the spirit and scope of the appended claims. It will therefore be appreciated that the scope of the disclosure and the appended claims is not limited to the specific embodiments illustrated in and discussed with respect to the drawings and that modifications and other embodiments are intended to be included within the scope of the disclosure and the appended drawings. Moreover, although the foregoing descriptions and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the disclosure and the appended claims. Further, the foregoing descriptions describe methods that recite the performance of a number of steps. Unless stated to the contrary, one or more steps within a method may not be required, one or more steps may be performed in a different order than as described, and one or more steps may be formed substantially contemporaneously. Finally, the drawings are not necessarily drawn to scale.
The disclosure provided herein describes features in terms of preferred and exemplary embodiments thereof. Numerous other embodiments, modifications and variations within the scope and spirit of the appended claims will occur to persons of ordinary skill in the art from a review of this disclosure.
This application claims priority to U.S. Provisional Application No. 63/121,524 filed Dec. 4, 2020, which is incorporated herein by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/IB2021/061333 | 12/3/2021 | WO |
Number | Date | Country | |
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63121524 | Dec 2020 | US |