Patent Application
20240332239
The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to three-dimensional (3D) hybrid bond integration for a multi-die assembly for power distribution and heat dissipation.
Packaging is one of the final manufacturing processes in the transformation of electronic devices into functional products for end users. Packaging must provide electrical and photonic connections for signal input and output, power input and voltage control. Packaging also provides for thermal dissipation and for the physical protection required for reliability.
In the field of electronic packaging, there has been a recent drive to develop thinner and larger structures. This has led to 3D chip stacks, in which chips or dies are layered on top of one another in a 3D stack with electrical interconnects between layers. This configuration has many benefits, such as providing a designer with the ability to place an increased number of chips in a two (2)-D area with an increased amount of electrical communications between them.
Embodiments of the present invention are directed to a three-dimensional (3D) die architecture. A non-limiting example of the three-dimensional (3D) die architecture includes a first die and a second die. The second die includes multiple interior layers of various types and is hybrid bonded to the first die along a hybrid bond layer. The 3D die architecture further includes oxide liner material extending from an exposed surface of the second die to the hybrid bond layer, a first through-silicon-via (TSV) extending from the exposed surface to a corresponding one of the multiple interior layers and a second TSV extending within the oxide liner material from the exposed surface to the hybrid bond layer.
Embodiments of the present invention are directed to a three-dimensional (3D) die architecture package. A non-limiting example of the 3D die architecture package includes a package die, first conductive bumps and a second conductive bump electrically communicative and thermally communicative with the package die, respectively, first and second dies hybrid bonded to one another and each including multiple interior layers of various types, oxide liner material extending through the first and second dies, first through-silicon-vias (TSVs), a second TSV and a heat sink. The first TSVs are electrically communicative with the first conductive bumps and extend from the first conductive bumps and through the second die to a corresponding one of the multiple interior layers. The second TSV is thermally communicative with the second conductive bump and extends within the oxide liner material through the second and first dies. The heat sink is thermally communicative with the second TSV.
Embodiments of the invention are directed to a method of assembling a three-dimensional (3D) die architecture. A non-limiting example of the method includes fabricating a first die, fabricating second dies comprising multiple interior layers of various types, hybrid bonding the second dies to the first die along a hybrid bond layer, extending oxide liner material between the second dies to the hybrid bond layer, extending first through-silicon-vias (TSVs) partially through each of the second dies to respective corresponding ones of the multiple interior layers and extending a second TSV within the oxide liner material between the second dies and to the hybrid bond layer.
Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.
The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.
In the accompanying figures and following detailed description of the described embodiments, the various elements illustrated in the figures are provided with two or three-digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, 3D integration (3DI) is a device system integration method that brings heterogeneous devices together in close proximity so that they function as a homogeneous device. 3DI is different than traditional 2D planar back-end-of-line (BEOL) integration in that 3DI adds an additional dimension, (Z) integration, which allows for more devices from different sources and types to be integrated into the system in close proximity and enables them to function as a unit.
There are many advantages of 3DI. These include increased multi-functionality integration of differing dies (memory, logic circuits, signal components, optoelectronic devices, nano-devices, sensors, etc.) into one assembly, increased and improved device performance, increased device density, reduced form factor and packaging and increased yield and reliability.
Some issues associated with 3DI remain. These include, but are not limited to, the need for increased power distribution and density and the corresponding need for heat dissipation and uniformity.
Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing for differently-sized through-silicon-vias (TSVs) to be incorporated into a 3D architecture. These differently-sized TSVs can allow for direct paths through the hierarchy of the 3D architecture to thereby provide faster and shorter direct power distribution paths along with increased heat dissipation.
The above-described aspects of the invention address the shortcomings of the prior art by providing for.
Turning now to a more detailed description of aspects of the present invention,
The 3D die architecture 101 further includes oxide liner material 130, a first TSV 140 and a second TSV 150. The oxide liner material 130 can be formed of a thick oxide material, such as low temperature oxide, which can be built into overmold and/or underfill to prevent die damage and degradation. The oxide liner material 130 extends along a thickness direction D of the second dies 120 from an exposed surface 125, which is opposite the hybrid bond layer 115, to the hybrid bond layer 115. The first TSV 140 extends along the thickness direction D of the second dies 120 from the exposed surface 125 to a corresponding one of the multiple interior layers (i.e., one of the BEOL layers 123). The first TSV 140 can be provided as multiple first TSVs 140 and the following description will generally relate to the case in which the first TSV 140 is provided as multiple first TSVs 140 for each of the second dies 120. The second TSV 150 extends along the thickness direction D within the oxide liner material 130 from the exposed surface 125 to at least the hybrid bond layer 115 or further into the first die 110.
As shown in
With the second TSV 150 extending to at least the hybrid bond layer 115, the second TSV 150 can increase a power distribution to the 3D die architecture 101. In particular, the second TSV 150 can deliver power directly to the hybrid bond layer 115 whereupon the power can be distributed to the various bond pads present in the hybrid bond layer 115 and then to metallization within the first die 110 and the second dies 120.
With reference to
In greater detail, the 3D die architecture package 201 can include the package die 210, the first conductive bumps 221 by which the first TSVs 140 are electrically communicative and/or thermally communicative with the package die 210 and the second conductive bump 222 by which the second TSV 150 is electrically communicative and/or thermally communicative with the package die 210. As above, the 3D die architecture package 201 can include the first TSVs 140 and the second TSV 150 and can also include one or more first dies 110 and two or more second dies 120 that are hybrid bonded to one another along hybrid bond layer 115 (see
Whereas the second TSV 150 extends to at least the hybrid bond layer 115 in
With continued reference to
With reference to
With reference to
Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The phrase “selective to,” such as, for example, “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.
The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases can be controlled and the system parameters can be set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. An epitaxially grown semiconductor material can have substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface can take on a {100} orientation. In some embodiments of the invention, epitaxial growth and/or deposition processes can be selective to forming on semiconductor surface, and cannot deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.
As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.
In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.
The flowchart and block diagrams in the Figures illustrate possible implementations of fabrication and/or operation methods according to various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
