Patent Application
20080237873
The present invention relates generally to integrated circuit package systems, and more particularly to a system for integrated circuit packages with bonding.
The demands for smaller, higher performance semiconductor devices, which support portable electronic devices, have motivated the development of new techniques for producing smaller and less expensive semiconductor devices. Modern consumer electronics particularly personal portable devices, such as cellular phones, digital cameras, and music players, require increasing integrated circuit die content to fit an ever-shrinking physical space as well as increasing performance. One of these technologies involves packaging the integrated circuit die in as small a form factor as possible and manufacturing the integrated circuit die as efficiently as possible.
Semiconductor packaging technology is one of the key technologies for realizing small, highly performing electronic devices. A variety of types of semiconductor packages have evolved over time in order to realize ever increasing high density packaging, such as the dual inline package (DIP), the small outline package (SOP) and the ball grid array (BGA). A key issue with implementing high density and performing electronics is that the area occupied by a semiconductor chip's package should be reduced when possible, which is often accomplished by reducing the width of the package's wires, the pitch of the package's external terminals and the size of the package's outer casing.
First-level IC packaging performs the function of electrically connecting a silicon chip to a carrier enabling it to be safely handled and assembled into an electronic system. Key objectives of IC packaging are to route the connections of the chip to a carrier substrate in a cost-effective way, to minimize the form factor of the final IC package, and to minimize degradation of electrical performance that can be caused by packaging parasitics such as inductance, resistance, and capacitance. Therefore, an electrical objective is to maintain signal integrity despite the presence of packaging parasitics. In other words, the electrical objective is to provide an electrical path in the package on which electrical data can travel without undue noise, distortion, or interference from parasitic elements along that path.
The negative effects of these parasitics can increase with operating frequency. As chip and system speeds now routinely operate at significantly higher frequencies, it is more necessary than ever to carefully select packaging technologies, which do not interfere with the proper functioning of the system. Currently, the two of the major packaging technologies used within the IC packaging industry for chip-to-carrier, or “first-level”, interconnections: are Wire-based interconnection (90-95% of chips connected) and bump-based interconnection (5-10% of chips connected).
In the case of the wire-based interconnection, a wire is bonded from a bond pad on the silicon chip to a bond finger on a carrier substrate. The resulting interconnection is referred to as a wirebond and the package is referred as a wire-based IC package. Electrical parasitics from this method of interconnection arise primary from the loop inductance of wire, the self inductance of the wire, capacitive coupling. With this method, functional limitations may arise with increased frequencies. The practical limit for this method is in large part determined by the frequency.
With bump-based interconnects, solder bumps are used instead of bonding wires. These bumps are located on the chip and each bump is soldered to a corresponding pad on a carrier substrate. During package assembly, this array of bumps on the chip must be carefully aligned with an associated array of pads on the carrier substrate. The interconnection scheme from chip bump to carrier pad needs to be determined at the time that the carrier substrate is designed; it can be difficult and expensive to reassign a bump on the chip to a different pad on the carrier substrate from the one placed directly below it. High density bump-based packages typically drive a much higher chip carrier, or substrate cost to route the bumps.
In contrast, the wire-based interconnect method allows the connection scheme between the bond pads and bond fingers to be determined at the later IC packaging manufacturing phase. This allows for electrical design flexibility at a later stage of IC packaging, which is generally desirable.
Thus, a need still remains for an integrated circuit package system to improve integrated circuit packages particularly processing, handling, and transporting mold segments. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
The present invention provides a substrate having an opening provided therein, forming a conductor in the opening in the substrate open at the top and having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.
Certain embodiments of the invention have other aspects in addition to or in place of those mentioned above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs. Where multiple embodiments are disclosed and described, having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.
For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the invention, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
The term “on” as used herein means and refers to direct contact among elements. The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, and/or removal of the material or trimming as required in forming a described structure. The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.
Referring now to
The substrate open connector 108 can also include a lower closed end of a conductor 110 over the opening near the second substrate layer 106 providing a bonding surface of the substrate open connector 108. The lower closed end of the substrate open connector 108 can preferably be electrically connected to the second substrate layer 106 including a substrate pad 112 and a substrate insulator 114. The substrate insulator 114 can be formed with a material such as a dielectric or a solder resist. The substrate pad 112 of the second substrate layer 106 can provide electrical connectivity to a next level system such as another package or a printed circuit board.
An integrated circuit die 116 can be attached over the first substrate layer 104 with a die attach layer 118 such as an adhesive. A die interconnect 120 such as a wire bond can electrically connect the integrated circuit die 116 and the substrate open connector 108. The die interconnect 120 can be formed by a process such as wire bonding. An encapsulant 122 can optionally be applied over the die interconnect 120, the integrated circuit die 116, the substrate open connector 108, and part of the substrate 102. The encapsulant 122 can provide protection and structural integrity to the integrated circuit package system 100.
For illustrative purposes, the die interconnect 120 is shown having a direct wire bonding on the lower closed end of the conductor 110 and a ball bump on the integrated circuit die 116 for reversed-stand-off-stitch bonding (RSSB), although it is understood that any connection may be used.
It has been discovered that the integrated circuit package system 100 with bonding in via significantly improves electrical performance due in part to a shorter interconnection path and eliminates the need to cover or plug the substrate interconnect with a material such as a metal cap, a solder mask resist, or any kind of epoxy plugging material.
Referring now to
Referring now to
The substrate open connector 308 can also include a lower closed end of the conductor 310 over the opening near the second substrate layer 306 providing a bonding surface of the substrate open connector 308. The lower closed end of the substrate open connector 308 can preferably be electrically connected to the second substrate layer 306 including a substrate pad 312 and a substrate insulator 314. The substrate insulator 314 can be formed with a material such as a dielectric or a solder resist. The substrate pad 312 of the second substrate layer 306 can provide electrical connectivity to a next level system such as another package or a printed circuit board.
An integrated circuit die 316 can be attached over the first substrate layer 304 with a die attach layer 318 such as an adhesive. A die interconnect 320, such as a wire bond, can electrically connect the integrated circuit die 316 and the substrate open connector 308. The die interconnect 320 can be formed by a process such as wire bonding. An encapsulant 322 can optionally be applied over the die interconnect 320, the integrated circuit die 316, the substrate open connector 308, and part of the substrate 302. The encapsulant 322 can provide protection and structural integrity to the integrated circuit package system 300.
For illustrative purposes, the die interconnect 320 is shown having a direct wire bonding over the integrated circuit die 316 and a ball bump on the lower closed end of the conductor 310 for stitch-off-bonding (SSB), although it is understood that any connection may be used.
Referring now to
Referring now to
Referring now to
The substrate open connector 108 can be formed having an open connector first width 602 in the first substrate layer 104 of approximately one hundred microns and an open connector second width 604 near the second substrate layer 106 of approximately seventy-five microns. A substrate thickness 606 of the substrate between the first substrate layer 104 and the second substrate layer 106 can be approximately sixty microns.
Referring now to
A conductive material 712 can electrically connect the first substrate layer 704, the second substrate layer 706, the third substrate layer 708, and the fourth substrate layer 710. The substrate 702 preferably includes a substrate open connector 714 such as a plated via. The substrate open connector 714 can connect the first substrate layer 704 and the second substrate layer 706 and be formed with the conductive material 712 and substantially vertical edges.
The substrate open connector 714 can also include a lower closed end of a conductor 716 providing a bonding surface of the substrate open connector 714. The lower closed end of the substrate open connector 714 can preferably be electrically connected to the second substrate layer 706 with the conductive material 712. The second substrate layer 706 can be electrically connected to the third substrate layer 708 with a substrate connector 718 such as a blind via. The substrate connector 718 can preferably formed with the conductive material 712.
The third substrate layer 708 can be electrically connected to the fourth substrate layer 710 with a closed substrate connector 720 such as a plated via and a substrate pad 722. The closed substrate connector 720 can preferably be formed with the conductive material 712 and include a substrate insulator 724. The substrate insulator 724 can be formed from a material such as a solder resist, an epoxy plugging material or a dielectric. The substrate pad 722 of the fourth substrate layer 710 can provide electrical connectivity to a next level system such as another package or a printed circuit board.
An interconnect forming device 726 such as a wire bond capillary can provide a die interconnect 728 having a connectivity end 730 such as a ball. The connectivity end 730 of the die interconnect 728 can be formed by the interconnect forming device 726 preparing for attaching the die interconnect 728 to the lower closed end of the conductor 716.
Referring now to
The substrate 702 can preferably include a first substrate thickness 806 of the substrate 702 between the first substrate layer 704 and the second substrate layer 706 of approximately forty microns. Further, a second substrate thickness 808 between the second substrate layer 706 and the third substrate layer can preferably be approximately sixty microns. Similar to the thickness between the first substrate layer 704 and the second substrate layer 706, a third substrate thickness 810 between the third substrate layer and the fourth substrate layer can preferably be approximately forty microns.
Referring now to
The substrate open connector 908 can also include a lower closed end of a conductor 910 over the opening near the second substrate layer 106 providing a bonding surface of the substrate open connector 908. The lower closed end of the substrate open connector 908 can preferably be electrically connected to the second substrate layer 906 including a substrate pad 912 and a substrate insulator 914. The substrate insulator 914 can be formed with a material such as a dielectric or a solder resist. The substrate pad 912 of the second substrate layer 906 can provide electrical connectivity to a next level system such as another package or a printed circuit board.
An integrated circuit die 916 can be attached over the first substrate layer 904 with a die attach layer 918 such as an adhesive. A die interconnect 920 such as a wire bond can electrically connect the integrated circuit die 916 and the substrate open connector 908. The die interconnect 920 can be formed by a process such as wire bonding. An encapsulant 922 can optionally be applied over the die interconnect 920, the integrated circuit die 916, the substrate open connector 908, and part of the substrate 902. The encapsulant 922 can provide protection and structural integrity to the integrated circuit package system 900.
For illustrative purposes, the die interconnect 920 is shown having a direct wire bonding on the lower closed end of the conductor 910 and a ball bump on the integrated circuit die 916 for reversed-stand-off-stitch bonding (RSSB), although it is understood that any connection may be used.
Referring now to
In greater detail, a system to provide the method and apparatus of the integrated circuit package system 100, in an embodiment of the present invention, is performed as follows:
Thus, it has been discovered that the integrated circuit package system method and apparatus of the present invention furnish important and heretofore unknown and unavailable solutions, capabilities, and functional aspects. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
