Patent Application
20100007017
The present invention relates to a semiconductor package, and more particularly to an inter-connecting structure for a semiconductor package and a method for the same.
The function of chip package includes power distribution, signal distribution, heat dissipation, protection and die encapsulation support as well-known in the art. As a semiconductor becomes more complicated, the traditional package technique, for example lead frame package, flex package or rigid package technique, can't meet the demand of producing smaller chip with high density elements thereon. In general, array packaging such as Ball Grid Array (BGA) packages provides a high density of interconnects relative to the surface area of the package. Typical BGA packages include a convoluted signal path, giving rise to high impedance and an inefficient thermal path which results in poor thermal dissipation performance. With increasing package density, the spreading of heat generated by the device is increasingly important. In order to meet packaging requirements for newer generations of electronic products, efforts have been expended to create reliable, cost-effective, small, and high-performance packages. Such requirements are, for example, reductions in electrical signal propagation delays, reductions in overall component area, and broader latitude in input/output (I/O) connection pad placement. In order to meet those requirements, a WLP (wafer level package) has been developed, wherein an array of I/O terminals is distributed over the active surface, rather than peripheral-leaded package. Such distribution of terminals may increase the number of I/O terminals and improve the electrical performance of the device. Further, the area occupied by the IC with interconnections when mounted on a printed circuit board is merely the size of the chip, rather than the size of a packaging lead-frame. Thus, the size of the WLP may be made very small. One such type may refer to chip-scale package (CSP).
Improvements in IC packages are driven by industry demands for improved thermal and electrical performance and reduced size and cost of manufacture. In the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. The formation of the solder bumps may be carried out by using a solder composite material. Flip-chip technology is well known in the art for electrically connecting a die to a mounting substrate such as a printed circuit board. The active surface of the die is subject to numerous electrical couplings that are usually brought to the edge of the chip. Electrical connections are deposited as terminals on the active surface of a flip-chip. The bumps include solders and/or plastics that make mechanical connections and electrical couplings to a substrate. The solder bumps after RDL have bump high around 50-100 um. The chip is inverted onto a mounting substrate with the bumps aligned to bonding pads on the mounting substrate, as shown in
Furthermore, because conventional package technologies have to divide a dice on a wafer into respective dies and then package the die respectively, these techniques are time-consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, today's trend of package techniques is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), and Wafer level package (WLP). “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dice). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. The wafer level package has extremely small dimensions combined with extremely good electrical properties.
U.S. Pat. No. 6,271,469 discloses a package with RDL layer 124 as shown in
The traditional microelectronic package as mentioned above still suffers some problems. For example, when a stress is applied on the solders 138 vertically, the solders 138, the metal pads 134, the conductive traces 124 and the dielectric players 118 and 126 will be pressed downwards because the encapsulation material 112 is elastic, such that the conductive traces 124 will be deformed to generate a drop height and become easy to crack.
Therefore, the present invention provides a solution to the aforementioned problem to increase the ball shear strength of the microelectronic package and to prevent the conductive traces from being deformed by an external force.
The present invention discloses an inter-connecting structure for a semiconductor package and a method for the same. In one aspect of the present invention, the inter-connecting structure for the semiconductor package includes a substrate formed to support a die thereon; core paste formed on the substrate and adjacent to the die; and a stiffener formed in an upper portion of the core paste, wherein the hardness of the stiffener is larger than the hardness of the core paste. The inter-connecting structure for the semiconductor package further includes a gap formed between the side wall of the stiffener and the side wall of the die. Furthermore, an upper surface of the stiffener is substantially in the same level with an upper surface of the die. The thickness of the stiffener is about 12.5-125 micrometers and the material of the stiffener includes polyimides (PI), copper clad laminate (CCL), or liquid crystal polymer (LCP).
In another aspect of the present invention, the inter-connecting structure for the semiconductor package includes a substrate formed to support a die thereon; core paste formed on the substrate and adjacent to the die; a stiffener formed in an upper portion of the core paste, wherein the hardness of the stiffener is larger than the hardness of the core paste; a redistribution layer (RDL) formed in a stacked built-up layer formed on the stiffener and the core paste; and an under bump metallurgy (UBM) formed through the redistribution layer to be attached onto the upper surface of the stiffener. The inter-connecting structure for the semiconductor package further includes a gap formed between the side wall of the stiffener and the side wall of the die. Furthermore, the under bump metallurgy (UBM) is partially attached onto the upper surface of the stiffener. An upper surface of the stiffener is substantially in the same level with an upper surface of the die. The material of the stiffener includes polyimides (PI), copper clad laminate (CCL) or liquid crystal polymer (LCP), and the thickness of the stiffener is about 12.5-125 micrometers.
In still another aspect of the present invention, a method for forming an inter-connecting structure for a semiconductor package includes providing an alignment tool with an alignment pattern; attaching a die with bonding pads thereon and stiffeners onto the alignment tool with a gap between the die and the stiffeners; filling core paste on the die and the stiffeners and into the gap therebetween; attaching a substrate onto the core paste; and curing the core paste and separating the alignment tool from the die and the stiffeners.
One advantage of the present invention is that the inter-connecting structure for the semiconductor package can minimize the drop heights of the redistribution layers (RDLs).
Another advantage of the present invention is that the inter-connecting structure for the semiconductor package can decrease the risk of fractures of the redistribution layers (RDLs).
Still another advantage of the present invention is that the inter-connecting structure for the semiconductor package can increase the ball shear strength of the semiconductor package.
Yet another advantage of the present invention is that the inter-connecting structure for the semiconductor package can prevent the solder balls and the under bump metallurgies (UBMs) from falling away from the dielectric layer and the stiffeners when a stress is applied on the semiconductor package.
These and other advantages will become apparent from the following description of preferred embodiments taken together with the accompanying drawings and the appended claims.
The present invention may be understood by some preferred embodiments and detailed descriptions in the specification and the attached drawings below. The identical reference numbers in the drawings refer to the same components in the present invention. However, it should be appreciated that all the preferred embodiments of the invention are only for illustrating but not for limiting the scope of the claims and wherein:
The invention will now be described with the preferred embodiments and aspects and these descriptions interpret structure and procedures of the invention only for illustrating but not for limiting the claims of the invention. Therefore, except the preferred embodiments in the specification, the present invention may also be widely used in other embodiments.
The present invention discloses a semiconductor package with an inter-connecting structure and a method for the same. With reference to
Furthermore, stiffeners 205 are formed in the upper portion of the core paste 204 to render the upper surfaces of the stiffeners 205 to be substantially in the same level with the upper surface of the die 201, so as to increase ball shear strength of the semiconductor package because the stiffeners 205 are rigid and the hardness of the stiffeners 205 is larger than that of the core paste 204. As shown in
A plurality of under bump metallurgies (UBMs) 211 are formed on the plurality of partial exposed surfaces of the first dielectric layer 207 and on the side walls of the openings to receive and couple with a plurality of solder balls 212 as shown in
With reference to
With reference to
With reference to
Therefore, the present invention provides the inter-connecting structure which utilizes stiffeners to prevent the solder balls, the under bump metallurgies (UBMs), and the redistribution layers (RDLs) near the solder balls from being pressed downwards when a stress is applied on the semiconductor package, so as to minimize the drop heights of the redistribution layers (RDLs) 210 and the risk of fractures of the redistribution layers (RDLs) 210 and increase the ball shear strength of the semiconductor package. Moreover, the present invention provides the inter-connecting structure which can prevent the solder balls and the under bump metallurgies (UBMs) from falling away from the dielectric layer and the stiffeners when a stress is applied on the semiconductor package by attaching the under bump metallurgies (UBMs) onto the stiffeners directly or partially, so as to further increase the ball shear strength of the semiconductor package.
The foregoing description is a preferred embodiment of the present invention. It should be appreciated that this embodiment is described for purposes of illustration only, not for limiting, and that numerous alterations and modifications may be practiced by those skilled in the art without departing from the spirit and scope of the invention. It is intended that all such modifications and alterations are included insofar as they come within the scope of the invention as claimed or the equivalents thereof.
