Technical Field
The present disclosure relates to an LDMOS semiconductor device and to a method for manufacture thereof.
Description of the Related Art
As is known, some applications of MOSFET power devices (or power MOSFETs) operate said MOSFET power devices at high switching frequencies. An example is that of electrical switches used in the field of high-frequency pulse-width modulation (PWM). In order to maximize the efficiency of the device, it is expedient for the levels of dynamic performance to exhibit a negligible loss of power during the switching operations. Said condition is obtained by minimizing the values of capacitance of the parasitic capacitors internal to said devices. Particular attention is directed at minimization of the gate-to-drain capacitance CGD, since said capacitance CGD determines the duration of the period of transient of the voltage signal during switching. It is hence of importance to minimize the value of capacitance CGD so as to minimize the power losses of the MOSFET power device. A parameter, which is strictly linked to the parasitic capacitance and is typically used for characterizing the efficiency of a MOSFET power device during switching, is the gate charge QG. In fact, the value of gate charge QG furnishes an estimate of the amount of current to supply to the gate terminal of the MOSFET power device to obtain switching of said device from the off state (in which it does not conduct electric current) to the on state (in which there is conduction of electric current between the source and drain terminals).
Lateral double-diffused MOSFETs (LDMOSs) can advantageously be used in a wide range of frequencies, with powers that range from a few watts to a few hundred watts. A classic LDMOS structure comprises a substrate, which has, in lateral sectional view, a horizontal sequence constituted by a low-resistance laterally diffused area (of a P+ type, referred to as “sinker”), a source region, a gate region, and a light-doped-drain (LDD) region that provides the drain terminal. The LDD region moreover faces a surface of the substrate. Said structure of a known type forms, for obvious reasons, an elementary cell with a large pitch.
Lateral MOSs have been amply studied, and known in the literature are techniques of minimization of the internal capacitances and information on how to obtain values of drain-to-source on-state resistance (RDS_ON) that are comparable with the values of the technology of trench field-effect transistors (also known as “trench-FETs”).
In order to minimize the parasitic capacitance between the gate terminal 6 and the LDD region 3, the structure shown in
As an alternative, more complex processes may be used, of the type described in U.S. Pat. No. 7,829,947, wherein a power LDMOS has a field-oxide region underneath the gate region in order to minimize the capacitance between the gate region and the LDD region. Said device, however, presents major manufacturing difficulties in order to control overlapping between the LDD region and the gate region.
Some embodiments of the present disclosure provide an LDMOS semiconductor device and a method for manufacture thereof that will be free from the drawbacks of the known art.
According to one embodiment of the present disclosure an LDMOS semiconductor device includes:
a semiconductor body having a first side and a second side opposite to one another along a first direction and including a first structural region, which faces the second side and has a first conductivity; and a second structural region which extends over the first structural region, faces the first side, and has a second conductivity opposite to the first conductivity;
a body region having the second conductivity and extending in the second structural region at the first side;
a source region having the first conductivity, extending within the body region and facing the first side;
a drain region having the first conductivity and facing the first side of the semiconductor body;
a gate electrode extending over a portion of the first side of the semiconductor body between the source region and the drain region;
a first trench which extends through the second structural region and houses a trench dielectric region and a first trench conductive region; and
a second trench which extends through part of the second structural region inside the body region, said second trench housing a second trench conductive region electrically connected with the body region and with the source region.
The drain region extends through the second structural region, electrically contacts the first structural region, and is arranged between, and in direct contact with, the body region and the trench dielectric region, said first and second trench conductive regions being electrically coupled to one another.
For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:
According to the present disclosure, a power device is provided, in particular a lateral-diffusion MOS transistor (LDMOS) with drain electrode on the back of the device.
The elementary cell 21 of
Extending over the substrate 22 is a structural region 26, for example made of silicon grown epitaxially, having a second conductivity (e.g., of a P− type), different from the first conductivity. The structural region 26 has a thickness chosen according to the need, in particular approximately 1.2 μm or 1.3 μm. It is evident that other values may be chosen, for example any value of thickness starting from 0.6 μm.
According to other embodiments, the structural region 26 has the first conductivity (e.g., of an N− type) and a value of conductivity lower than the value of conductivity of the substrate 22.
The structural region 26 is delimited by a first side 26a and by a second side 26b opposite to one another in the direction Z. The second side 26b of the structural region 26 faces the first side 22a of the substrate 22. According to one embodiment, the second side 26b of the structural region 26 is in direct electrical contact with the first side 22a of the substrate 22. According to alternative embodiments (not shown), one or more further structural regions, for example grown epitaxially and similar to the structural region 26 and/or to the region 22, extend between the first side 22a of the substrate 22 and the second side 26b of the structural region 26.
Extending over the first side 26a of the structural region 26 is a dielectric layer 28, for example made of silicon oxide, having the function of gate oxide.
A gate electrode 30 extends over the dielectric layer 28. The gate electrode 30 is formed by a stack of layers of polysilicon with N+ doping 30a, silicide 30b, insulating material 30c (e.g., silicon oxide), and silicon nitride 30d. According to one embodiment, the silicide layer 30b is constituted by a metal layer, obtained by reaction with cobalt, or else via deposition of tungsten silicide in sequence to the polysilicon, or in any other way.
A drain region 38, having the first conductivity (of an N type), extends in the direction Z between the first side 26a of the structural region 26 and the first side 22a of the substrate 22, substantially aligned with a side wall 30′ of the gate electrode 30 (or in any case overlapping to a minimal extent the gate electrode 30). In top plan view, the drain region 38 extends alongside, in the direction X, the gate electrode 30, and possibly overlaps the gate electrode, as a consequence of the steps of the manufacturing process.
A trench 31 extends in depth in the direction Z, in the structural region 26, and in part of the substrate 22, and terminates in the substrate 22. A first trench conductive region 32 extends inside the trench 31 and is surrounded by one or more dielectric layers (in
The trench 31 extends alongside (in the direction X) the gate electrode 30 and the drain region 38. The first trench conductive region 32 is electrically insulated from the gate electrode 30 by the second trench dielectric 36 (and, as described more fully hereinafter by a further dielectric designated in the figure by the reference number 40a). In addition, the first trench conductive region 32 is electrically insulated from the drain region 38 by the first and second trench dielectrics 34, 36. Moreover, the first and second trench dielectrics 34, 36 insulate electrically the first trench conductive region 32 from the substrate 22.
Hence, both the first and the second trench dielectrics 34, 36 are designed to insulate electrically the first trench conductive region 32 from the structural region 26 and from the substrate 22, whereas the second trench dielectric 36 and the dielectric 40a are designed to insulate electrically the first trench conductive region 32 from the gate electrode 30.
The first trench conductive region 32 forms an electrode, which can be connected to a reference voltage GND (e.g., connected to ground) designed to reduce the electrical field, and hence generation of hot electrons in the drain region 38, in particular in areas corresponding to the portion of the drain region 38 that extends in the proximity of the gate electrode 30. This enables a good control (in particular, a reduction) of the phenomena of charge trapping or injection (known as “hot-carrier injection”) in the drain region 38. The distance between the first trench conductive region 32 and the drain region 38 may be adjusted by choosing appropriately the thickness of the first and second trench dielectrics 34, 36.
The present applicant has found that a thin trench dielectric (for example in the range of approximately 50-200 nm, extremes included) makes it possible to approach the first trench conductive region 32 to the drain region 38, with consequent reduction of the electrical field (potential lines) in the portion of the structural region 26 in which the drain region 38 faces the gate electrode 30. This leads, as has been said, to the advantage that the phenomenon of generation of hot electrons is minimal even at high doping concentrations of the drain region 38.
Moreover, this enables an optimal compromise to be achieved between control of the aforementioned electrical field and the dose of doping of the LDD region, which, if increased as compared to the solutions of a known type, enables reduction of the drain-to-source on-state resistance RDS_ON.
Formation of the drain region 38 will be described more fully hereinafter, and is obtained place via slanted implantation, where the angle is chosen such a way that the drain region 38 thus formed extends between the first side 26a and the second side 26b of the structural region 26, substantially adjacent to the first trench dielectric 34, and is in electrical contact with the substrate 22.
At the second side 22b of the substrate 22 a first metallization 41 is present, in electrical contact with the substrate 22. In use, the drain region 38, the substrate 22, and the first metallization 41 form a drain electrode of the power device 20.
The elementary cell 21 of
The elementary cell 21 of
In addition, a source region 46 extends in the body region 44, facing the first side 26a of the structural region 26, for a depth in the direction Z comprised, for example, between approximately 100 nm and 150 nm. The source region 46 has the first conductivity (e.g., of an N+ type) and overlaps, in top plan view, to the gate electrode 30 by an amount, measured along the axis X, comprised for example between approximately 0.05 μm and 0.15 μm.
In use, the portion of the body region 44 comprised between the source region 46 and the drain region 38 houses the conductive channel of the power device 20.
An enriched region 48 (p-well), having the second conductivity and a value of doping higher than that of the body region 44 (e.g., P+, with a concentration of around 1·1018 cm−3), extends in the body region 44 underneath the source region 46 (i.e., substantially vertically aligned to the source region 46 in the direction Z). The enriched region 48 has the function of reducing, in use, the sheet resistance of the body region 44, which is located underneath the source region 46, so as to prevent turning-on of a parasitic bipolar transistor in the avalanche multiplication during breakdown.
The elementary cell 21 of
The second trench conductive region 52 is moreover electrically separated from the gate electrode 30 by the spacer 40b.
A second metallization 56 extends over the first trench conductive region 32, the second trench conductive region 52, and the gate electrode 30, in electrical contact with the first trench conductive region 32 and the second trench conductive region 52, and electrically insulated from the gate electrode by the silicon-nitride layer 30d and the dielectric layer 30c.
In this way, via the second metallization 56, the body region 44 and the source region 46 are electrically coupled to the first trench conductive region 32.
In use, according to one embodiment of the present disclosure, the second metallization 56 is biased at a reference voltage GND (for example, ground).
The present applicant has found that lowering the parasitic capacitance CGD between the gate electrode 30 and the drain region 38, more effectively decouples the gate electrode 30 electrically from the drain region 38. According to the embodiment of FIG. 2, the gate electrode 30 is electrically decoupled from the drain region 38 via the body region 44. According to one aspect of the present disclosure, in use, the body region 44 is biased at the reference voltage GND via the second trench conductive region 52 and the second metallization 56. The drain region 38, as has been said, is of a vertical type and extends in the structural region 26 along Z; likewise, also the first trench conductive region 32 extends vertically along Z in the structural region 26, and borders laterally (along X) on the drain region 38. According to the structure described, the only contributions at the basis of electrical coupling between the gate electrode 30 and the drain region 38 are: (i) electrical coupling due to the overlapping portion between the drain region 38 and the gate electrode 30, through the insulating layer 28; and (ii) electrical coupling due to the interaction between the side wall 30′ of the gate electrode 30 and the drain region 38.
Some applications desire threshold voltages of the power device 20 ranging between 1 V and 2 V. This entails the use of low concentrations of P doping of the body region 44 (around 5·1016-2·1017 cm−3) when thick gate oxides are used (in the region of 40-60 nm; in
According to the embodiment of
The elementary cell 71 of
The buffer layer 102 is indifferently obtained by epitaxial growth or implantation of dopant species which have the first conductivity. The doping concentration of the buffer layer 102 is of around 5·1015-5·1016 cm−3. The thickness of the buffer layer 102 is, for example, comprised between 0.4 μm and 0.8 μm. The presence of the buffer layer 102 enables improvement (i.e., increase) of the value of the breakdown voltage of the power device 100.
The embodiments of
According to the embodiments of
Irrespective of the particular embodiment, the power device according to the present disclosure presents the following advantages: the phenomena of hot-carrier injection (HCI) are negligible thanks to the implementation of a superjunction; the specific on-state resistance RDS_ON has an optimized value thanks to the reduction in the value of pitch of the elementary cell and to the lateral-doping doses (LDD) used; low gate charge QG (parasitic capacitances inside the device of low value); moreover, high versatility due to integration of a monolithic half-bridge, thanks to the drain terminal on the back.
With reference to
With reference to
The substrate has the first side 22a and the second side 22b opposite to one another and substantially orthogonal to the direction Z. Formed on the first side 22a is the structural region 26, for example by epitaxial growth of silicon. The structural region 26 has, according to one embodiment, the second conductivity with a doping concentration of approximately 1·1015 cm−3.
According to a different embodiment, the structural region 26 has the first conductivity with a doping concentration of approximately 1·1015 cm−3. Doping of the structural region 26 is obtained by introducing appropriate dopant species in the reaction chamber during the epitaxial growth. Alternatively, doping of the structural region 26 is obtained by implantation of dopant species at the end of, or during, formation of the structural region 26. For example, a doping of an N type is obtained with arsenic or phosphorus, whereas a doping of a P type is obtained with boron.
Then, the dielectric layer 28 is formed, made, for example, of silicon oxide SiO2. The dielectric layer 28 is formed, for example, by thermal oxidation of the structural region 26, or by deposition of dielectric material. The dielectric layer 28 has a thickness of between 30 nm and 60 nm.
The process then proceeds with formation of the stack of layers, which, in subsequent manufacturing steps, form one or more gate electrodes 30. For this purpose, formed by deposition on the dielectric layer 28 is a first intermediate layer 30a of doped polysilicon, in particular of an N type, having a thickness comprised between 300 nm and 400 nm. Then, formed on the first intermediate layer 30a is a second intermediate layer 30b, made, for example, of silicide (formed in a way in itself known, with a process of thermal reaction) or of deposited metal. The second intermediate layer 30b has a thickness comprised between 100 nm and 200 nm. The first intermediate layer 30a is the gate electrode proper, whereas the layer 30b has the function of metal electrode.
Next, formed on the second intermediate layer 30b is a third intermediate layer 30c, made of dielectric material, for example by deposition of silicon oxide SiO2. The third intermediate layer 30c has, for example, a thickness comprised between 300 nm and 400 nm.
Then, formed on the third intermediate layer 30c is a fourth intermediate layer 30d, made, for example, of deposited silicon nitride. The fourth intermediate layer 30d has, for example, a thickness of between 70 nm and 140 nm, and has the function of etch-stop layer in the steps of etching of the insulating layer 36 (see the step of
Next, gate electrodes 30 are defined, via masked etching. With reference to
Then (
Next (
Then (
Next (
Then (
In alternative embodiments, the enrichment region 48 can be obtained with implantation carried out after formation of the spacers 40a and 40b.
The implantation energy chosen during the step of
Then (
Said etching step is carried out so as to remove completely the covering dielectric layer 128 from the wafer 200 except for portions of the covering dielectric layer 128 adjacent to the side walls 30′ of the gate electrodes 30.
Moreover, said etching step is continued until portions of the dielectric layer 28 which extend underneath the covering dielectric layer 128 are removed. The anisotropic dry etch is such that the covering dielectric layer 128 is removed at a higher rate in areas corresponding to portions of the latter orthogonal to the etching direction, whereas portions of the covering dielectric layer 128 substantially longitudinal to the etching direction (for example, the portions of the covering dielectric layer 128 that extend along the side walls 30′ of the gate electrodes 30) are removed at a lower rate. Along the side walls 30′ of the gate electrodes 30, spacers 40a and 40b are thus formed, which have a substantially triangular shape, or a shape tapered along Z such that the lateral thickness, measured along X, of the spacers 40a, 40b, decreases starting from the top side 26a of the structural region 26. In particular, the spacers 40a, 40b have a base side having a thickness, measured along X, equal to approximately the thickness chosen for the covering dielectric layer 128 (e.g., between 100 and 200 nm).
Moreover, the spacers 40a, 40b protect, during the previous etching step, portions of the dielectric layer 28 that extend underneath them, which are thus not removed.
Then (
The trenches 132 are formed by anisotropic etching of the structural region 26 and of the substrate 22. According to one embodiment, an etching of a DRIE type is used.
In order to protect the intermediate source region 46′ from the etch, a photoresist mask 133 is formed in an area corresponding to the intermediate source region 46′, between the gate electrodes 30. With reference to
Then (
Then (
The step of implantation of
Then, a step of thermal annealing is carried out to favor diffusion of the implanted dopant species (e.g., at 1000° C. for 30 s). In this step, there is also the diffusion of the dopant species implanted in the previous steps (e.g., during the steps of
Then (
With reference to
The embodiment of
The embodiments of
According to this embodiment, after deposition of the second trench dielectric, formed on the wafer 200 is a silicon-nitride layer having a thickness of some tens of nanometers. The silicon-nitride layer is formed by deposition of Si3N4, which penetrates in the trenches 132 to form a silicon-nitride layer on the walls and on the bottom of the trenches 132 (i.e., forming the filling subregion 64a). Then, formed on the wafer 200 is a silicon-oxide layer having a thickness of some hundreds of nanometers (e.g., 200 nm), which fills, at least partially, the trenches 132. Then, by etching selectively the silicon oxide with an etching chemistry having a high selectivity in regard to silicon nitride, the silicon oxide is removed partially inside of the trenches 132 to form the dielectric subregion 64b, which fills part of the trenches 132 (in particular, the bottom of the trenches 132). By modulating appropriately, and in a way in itself known, the duration of the etch, it is possible to remove the desired amount of silicon oxide from the trenches 132. The latter etch is moreover designed to remove the oxide layer deposited on the wafer 200 outside the trenches 132, until the underlying silicon-nitride layer (deriving from the immediately previous deposition step) is reached. Finally, said silicon-nitride layer may be removed from the wafer 200 with an etch of a standard type, without the need to resort to any photomask. Inside the trenches 132, the silicon-nitride layer is removed elsewhere, except for the areas of the latter protected by the dielectric subregion 64b. A second filling region 64 is thus formed, comprising the dielectric subregion 64a, made of silicon nitride, which surrounds laterally and at the bottom the dielectric subregion 64b, made of silicon oxide. It is thus possible to proceed with formation of the first trench conductive region 32′, in the way already described previously. It is evident that the dielectric subregions 64a and 64b may be made of dielectric materials different from those indicated by way of example.
According to a further embodiment (not shown in the figure), the filling regions 64 are provided by causing the step of formation of the second trench dielectric 36 to be followed by a step of formation (e.g., deposition) of a third trench dielectric having an etching rate higher than the respective etching rate of the second trench dielectric 36. In this way, it is possible to modulate etching of the third dielectric without incurring in undesirable damage to the second trench dielectric 36. The third dielectric may, for example, be etched in such a way as to remove it only in part from the trenches 132 but completely from the rest of the wafer. The trenches 132 are thus partially filled with dielectric material in areas corresponding to their bottom.
Even more in particular, the thickness (along X) of the trench dielectric 136 is equal to dMIN substantially as far as a depth z1, measured starting from the first side 26a of the structural region 26, approximately equal to the depth reached by the body region 44. Then, beyond a depth z1 in the trench 136, the thickness (along X) of the trench dielectric 136 passes, as has been said, to the maximum value dMAX. According to this embodiment, dMIN is given by the sum of the thicknesses, along X, of the trench-oxide layers 34 and 36, and dMAX is given by the sum of the thicknesses, along X, of the trench-oxide layers 34 and 36, and thicknesses, along X, of the layers 181 and 183 (the latter are shown hereinafter in
Consequently, the conformation of the first trench conductive regions 32 follows the conformation of the trench dielectric 136. The first trench conductive regions 32, hence, have a thickness, in cross-sectional view and along X that is maximum when measured at the first side 26a of the structural region 26, and minimum when measured at the bottom end of the first trench conductive region 32.
Steps of formation of the trench dielectric 136, having the conformation represented in
With reference to
Then (
Then (
Next (
This embodiment presents the advantage of improving the degree of freedom between the on-state drain-to-source resistance RDS_ON and the phenomenon of hot-carrier injection (HCI). The conformation of the dielectric region 36 of
Moreover, the potential lines resulting from a structure of this type have a smooth curvature in so far as, as has been said, a thick dielectric 136 (with a thickness dMAX) makes it possible to render the lines of field in said region less dense. Hence, the distribution of electrical field is improved as compared to devices of a known type and also as compared to the embodiments of
With reference to
The drain electrode D of the transistor T1 (“high-side” transistor) can be biased, in use, at a voltage VH, whilst the source electrode S of the transistor T2 (“low-side” transistor) can be biased, in use, at a voltage VL, with VH>VL. The source electrode of the transistor T1 is electrically coupled to the drain electrode of the transistor T2 at a common node 310.
With reference to
The wafer 300 comprises a substrate 301, made of semiconductor material, for example silicon, with a doping of an N+ type, and a structural region 302, for example silicon grown epitaxially, of a P type. The structural region 302 has a top side 302a and a bottom side 302b, where the bottom side 302b is in contact with the substrate 301.
The transistor T1 includes: gate electrodes 315 arranged on the top side 302a of the structural region 302 and separated from the latter by a gate dielectric layer 303; body regions 316, formed in the structural region 302 and facing the top side 302a of the structural region 302; source regions 318 formed in the structural region 302, inside the body regions 316, and facing the top side 302a of the structural region 302; p-wells 319 formed in the structural region 302, inside the body regions 316, underneath the source regions 318; and drain regions 320, which extend in the structural region 302, facing the top side 302a of the structural region 302, between body regions 316. One or more plugs 322 made of electrically conductive material, for example metal, extend through the structural region 302 starting from the top side 302a until the substrate 301 is reached, and terminating inside the substrate 301. The plugs 322 are in electrical contact with respective source regions 318 and have the function of forming an electrical connection between the source regions 318 and the substrate 301.
Extending over the structural region 302 and the gate electrodes 315 is a dielectric layer 326, for example made of silicon oxide, as a protection and insulation of the gate electrodes and of the plugs 322. A further conductive plug 324 extends through the dielectric layer 326 and the gate oxide 303 until it reaches and comes into electrical contact with the drain region 320. In order to favor said electrical contact, the drain region 320 locally has an electrical-contact region 328 having a level of doping higher than the doping of the drain region 320.
A metallization 330 extends over the wafer 300, on the dielectric layer 326, in electrical contact with the plug 324, to form a drain electrode D of the transistor T1. A metallization 332 extends over the back of the wafer 300, in electrical contact with the substrate 301 and with the source regions 318 (via the substrate 301 and the plugs 322). The metallization 332 concurs in forming a source electrode for the transistor T1.
The transistor T2 is a power device according to any one of the embodiments described with reference to
The transistor T2 includes: gate electrodes 335 arranged on the top side 302a of the structural region 302 and separated from the latter by the gate dielectric layer 303; body regions 336, formed in the structural region 302 and facing the top side 302a of the structural region 302; source regions 338 formed in the structural region 302, inside the body regions 336, and facing the top side 302a of the structural region 302; p-wells 339 formed in the structural region 302, inside the body regions 336, underneath the source regions 338; and drain regions 340 (LDD regions), which extend vertically in the structural region 302 (in the direction Z), between the top side 302a of the structural region 302 and the bottom side 302b of the structural region 302.
A conductive plug 341 extends through the dielectric layer 326 and the gate oxide 303 until it reaches and comes into electrical contact with respective source regions 338 and p-wells 339. A metallization 342 extends over the wafer 300, on the dielectric layer 326, in electrical contact with the plug 341, to form a source electrode S of the transistor T2. The metallizations 330 of the transistor T1 and 342 of the transistor T2 are electrically insulated from one another.
The transistor T2 further comprises deep trenches 346, which extend through the dielectric layer 326, the gate oxide 303, the structural region 302, and part of the substrate 301, to terminate in the substrate 301. In particular, the trenches 346 are, in this case, provided according to the embodiment of
The trenches 346 include one or more dielectric insulation layers 348 and an internal conductive region 349, surrounded by the one or more dielectric insulation layers. In particular, the trenches 346 extend adjacent to the drain regions 340.
The drain regions 340 of the transistor T2 are in electrical contact with the substrate 301 and with the metallization 332. Consequently, the source regions 318 of the transistor T1 and the drain regions 340 of the transistor T2 are electrically coupled together. The metallization 332 and the substrate 301 provide the common node 310 of
From an examination of the characteristics of the disclosure provided according to the present disclosure, the advantages that it affords are evident.
The horizontal dimensions (measured along X), or pitch, of a power device according to any one of the embodiments of the present disclosure are considerably reduced as compared to the known art; the drain electrode is provided on the back of the wafer, enabling a packaging of a standard type; the performance is not impaired, and is comparable to that of horizontal-channel LDMOS devices of a known type.
Moreover, thanks to the fact that during formation of the LDD regions the spacers 40a, 40b function as hard-masks, the alignment between the gate electrodes and the drain regions is carefully controlled, reducing the parasitic capacitances.
Thanks to the implementation of the concept of superjunction, the phenomena of hot carrier injection are negligible.
The specific on-state drain-to-source resistance RDS_ON is low thanks to the reduced pitch of the elementary cell (and hence of a device including a plurality of elementary cells) and thanks also to the doses of LDD used.
In addition, the internal capacitances are minimized, enabling reduction of the gate charge QG.
Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the sphere of protection of the present disclosure.
For example, as shown in
Filling of the trenches 132 includes one or more dielectric layers and a conductive filling 32, according to any one of the embodiments of
According to a further embodiment, shown in
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Number | Date | Country | Kind |
---|---|---|---|
TO2013A0021 | Jan 2013 | IT | national |
Number | Name | Date | Kind |
---|---|---|---|
7589378 | Kocon et al. | Sep 2009 | B2 |
7829947 | Hébert | Nov 2010 | B2 |
7936007 | Marchant et al. | May 2011 | B2 |
8193559 | Haeberlen et al. | Jun 2012 | B2 |
20020053699 | Kim et al. | May 2002 | A1 |
20020175351 | Baliga | Nov 2002 | A1 |
20040056284 | Nagaoka | Mar 2004 | A1 |
20050205897 | Depetro et al. | Sep 2005 | A1 |
20070085204 | Korec et al. | Apr 2007 | A1 |
20090298248 | Fung | Dec 2009 | A1 |
20100237411 | Hsieh | Sep 2010 | A1 |
20100237416 | Hebert | Sep 2010 | A1 |
20100327348 | Hashimoto et al. | Dec 2010 | A1 |
20110127602 | Mallikarjunaswamy | Jun 2011 | A1 |
20130313640 | Shen | Nov 2013 | A1 |
20140197487 | Cascino et al. | Jul 2014 | A1 |
20150206968 | Cascino et al. | Jul 2015 | A1 |
Number | Date | Country |
---|---|---|
2 202 794 | Jun 2010 | EP |
2009081385 | Apr 2009 | JP |
2011054009 | May 2011 | WO |
Entry |
---|
Shen et al., “Performance Analysis of Lateral and Trench Power MOSFETs for Multi-MHz Switching Operation,” PowerSOC Workshop, Florida Power Electronics Center, School of Electrical Engineering and Computer Science, University of Central Florida, date unknown, 24 pages. |
Number | Date | Country | |
---|---|---|---|
20160087084 A1 | Mar 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14151527 | Jan 2014 | US |
Child | 14964130 | US |