Patent Application
20200211934
This Disclosure relates to semiconductor packaging, more particularly to vertically offset (e.g., downset) lead frames for multichip semiconductor packages.
Plastic semiconductor packages include leadframes. A conventional plastic package includes an integrated circuit (IC) die attached to a leadframe, encapsulated in a plastic body. The leadframe supports the die during a molding process, and provides the internal traces and terminal leads of the completed IC package. Leadframes are provided in strips (or panels) adapted to simultaneously form multiple packages, which are subsequently singulated into individual packages.
One type of leadframe includes a mounting paddle (or die pad) for the IC die, and patterns of lead fingers spaced around the peripheries of the mounting paddle. Prior to the molding process, the back side of the die can be attached to the die pad using an adhesive such as epoxy. In addition, metal wires can be wire bonded from bond pads on the die to the lead fingers. Using a transfer molding process, a plastic material, such as an epoxy resin, is molded to either side of the die and leadframe, and over the wire bonded wires. The leadframe is then singulated into multiple packages, and the lead fingers are trimmed and shaped to form the terminal leads of the packages.
One approach to plastic IC packaging involves providing the die pad recessed a depth measured from a plane coincident to a major plane of the leadframe that includes the lead fingers to enable locating the IC die at a level below the major plane in what is termed a downset. The downset improves the wire bonding process by reducing drag forces on the bondwires during wire bonding, and allows the bondwires to be more easily encapsulated by the plastic (mold compound) body.
Some packaged IC devices are multichip module (MCM) devices. One wirebond package arrangement has a plurality of die pads lateral to one another each with an IC die on a die pad.
One particular type of IC device is an isolation device which prevents the propagation of DC and unwanted AC currents between its input and output, while allowing the transmission of the desired AC signal. The isolation device accomplishes this function using an isolation barrier that has a high breakdown voltage and low leakage. A high resistive path exists across the isolation barrier, but the isolation device can still transfer information in the desired AC signal across the isolation barrier by capacitive, inductive, or by optical coupling.
One common reinforced-isolation device arrangement is in the form of a packaged MCM, where each IC die in the package includes at least one embedded high voltage (HV) isolation capacitor (ISO cap), such as using two thick SiO2 capacitors connected in series by a bondwire between the input and the output that together constitute a double isolation barrier. During MCM isolation device operation there is generally a HV (e.g., 1,000 V root mean square (rms)) applied across the device which generally results in the respective die pads having a large potential difference.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed aspects recognize during packaged MCM isolation (ISO) device operation and testing there can be a high electric field (E field) in the air above and below the bottom side of the mold compound, where the E field intensity below the mold compound can increase relative to the E-field compared to a zero downset die pad. As used herein, a zero downset die pad refers to <0.2 mm of downset. This Disclosure includes a partially etched die pad for at least one of the die pads sometimes referred to herein as a sink pad for packaged MCM ISO devices. Partially etched die pads provide the advantage of gaining more space for thicker components (e.g., inductors) which may increase device efficiency, or a thicker mold compound for reducing the E field in the air above or below the mold compound during testing or operation of the packaged ISO device which can eliminate or at least reduce arcing in the air between leads that arc between a lead connected to high voltage and a lead connected to a ground.
Disclosed aspects include a leadframe for a multichip semiconductor package includes a first die pad and at least a second die pad both vertically offset at least 0.2 mm relative to leads or lead terminals that are positioned on at least 2 sides beyond the first die pad and the second die pad. At least one of the first and second die pads has a reduced thickness portion and a full thickness portion, and wherein the full thickness portion has the same thickness as a thickness of at least an outside portion the leads or the lead terminals.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure.
A conventional downset die pad that is typically used to improve the mold flow or increase the height for wire bonding is recognized to result in less mold compound thickness below the die pad as compared to the mold compound thickness above the die pad. This downset arrangement results in the internal E field (the E field lines between the respective die pads) adding more E field to the E field in the air gap between the leads (or land pads that the leads are on) under the mold compound that are biased to different potentials during testing and field use. Typically all leads on one side of the ISO device are biased relative to all the leads on the other side of the ISO device. Field lines extending out of the package from the internal E field adds E field to the external E field thus strengthening the total net E field intensity in the air gap between the leads across the package as well as under the mold compound. If the total E field is high enough to cause air ionization during device testing, the result is ISO test failures that can result in scrapping of packaged ISO devices.
Disclosed packaged ISO devices reduce the E field when biased during testing or while in field use by increasing the mold compound thickness between the location of the minimum internal dielectric spacing (being the gap between the respective die pads) and thus for a downset arrangement particularly in the air region under the mold compound between the external leads which are generally soldered to printed circuit board (PCB) land pads. This mold thickness increase is realized by thinning a portion of the die pads in the package.
Although not shown herein, it should be recognized that this Disclosure also applies to leadless leadframes, such as quad flat no lead (QFN) leadframes. The distance from the bottom of the die pads portion 112a and 122a to the bottom edge of the mold compound is shown as Bin
Disclosed leadframes having die pads with reduced thickness portions can be formed using a masked etch process that uses an etch mask to protect the full thickness die pad portions. It is generally desirable to have some full metal thickness portions, such as in the die attach area, and to ensure mechanical strength and flatness for vacuum stabilization during the assembly process. A liquid (chemical spray) or gaseous etchant can be used before the etching process. After etching, the etch mask is then removed. In one particular arrangement the full metal thickness is 254 μm, and the reduced thickness portion is 152 μm. The etching depth can be controlled by the etching time. The etching of the die pad can be performed on the bottom side, on the top side, or on both the bottom side and on the top side.
Die pad 282 is shown having a reduced thickness die pad portion 282a. Transformer coils with magnetic material are shown on the reduced thickness die pad portion 282a along with a die shown as Die 1 on a full thickness portion 282b of the die pad 282, and Die 2 is shown on die pad 291. Bond wires are also shown.
Due to the series connection provided by the ISO caps, during operation of the packaged MCM ISO device 300 based on the voltage divider rule the bondwire 130 is generally at one half the HV difference between the bottom plate 119 of the first IC die 110 and the bottom plate 129 of the second IC die 120. However, in some somewhat uncommon applications, the voltage on the top plate may not be equal to one half the HV difference, but instead some other fraction that results from the respective ISO cap capacitances not being equal to one another in the series assembly. The full HV appears between the first die pad 112 and the second die pad 122 (same HV as being between the bond pad 111 and the bond pad 121).
The first top plate 118 has a top dielectric layer thereon that has a top plate dielectric aperture, with one of the lower metal layers as its bottom plate. Similarly, a second IC die 120 is on the die attach adhesive 123 on the second die pad 122 including functional circuitry 126 with a metal stack thereon 127 including a top metal layer and a plurality of lower metal layers, with at least a second ISO cap shown as C2 utilizing the top metal layer as the second top plate 128 along with the second bottom plate 129. The second top plate 128 has a top dielectric layer thereon having a top plate dielectric aperture and one of the lower metal interconnect layers as its bottom plate.
Bond pads comprising the top metal layer are indirectly coupled to the bottom plates 119 and 129 of the ISO caps through vias and intermediate metal levels as well as circuitry. The bond pad 111 is coupled by connection circuitry depicted by a dashed line to the first bottom plate 119, and the bond pad 121 coupled by connection circuitry depicted by a dashed line to the second bottom plate 129. The circuitry for coupling bond pads to the bottom plates 119 and 129 generally comprises analog-to-digital converters or digital-to-analog converters which includes groups of transistors, before going through vias and the respective metal levels of their metal stacks to reach their respective bond pads 111 and 121.
During packaged MCM ISO device 300 operation, there is generally an analog signal that comes into the device externally from the first lead 114 and the second lead 124 that get connected by bondwires 131, 132 to the die bond pads 111 and 121, respectively. In typical operation, there will generally be signals either coming from the first lead 114 pin that gets sent across to the other side of the isolation barrier, such as to the pin of the second lead 124, or coming from second lead 124 and being sent across the isolation barrier back to first lead 114. One series cap HV cap pair either transmits across the ISO barrier or receives from the other side of the ISO barrier, but not both. Generally, there can be more than one communication “channel” on the IC die and the die can have either one channel as a transmit channel and 3 channels as receive channels (on a 4-channel device), or any combination of transmit/receive channels on a device that has 1 to 6 channels. Then the signal from the die bond pads 111 and 121 get routed to signal processing circuitry to send/receive digital signals to the bottom plates 119 and 129 that will transmit across the ISO barrier provided by C1 and C2.
The leads 114, 124 together with the first die pad 112 and second die pad 122 may collectively be termed a ‘split leadframe’. The leadframe as known in the art is generally manufactured by plating Ni and Au material onto a flat sheet of copper or copper-alloy material, and either etching or stamping this material into the desired form to provide external pads, routing, and die supports within the package.
Functional circuitry 116 and 126 more generally realizes and carries out a desired functionality, such as that of a digital IC or an analog IC, and in one aspect comprises a BiCMOS (MOS and Bipolar) IC. The capability of the functional circuitry provided on an IC mentioned herein may vary, for example ranging from a simple device to a complex device.
A first end 130a of the bondwire 130 is coupled within the top plate aperture on the first top plate 118. A second end 130b of the bondwire 130 is coupled within the top plate aperture on the second top plate 128. Although each IC die 110, 120 is shown having a single ISO cap so that there is a single ISO cap to ISO cap bondwire, each IC die can have multiple ISO caps so that there can be a plurality of disclosed ISO Cap to ISO Cap bondwires.
The bondwire 130 is embedded in a mold compound 160, typically a heterogeneous material comprising epoxy with embedded silica filler particles. The second end 130b of the bondwire includes a stitch bond shown as 134. There is a ball 133 shown on the first top plate 118, and on the bond pads 111 and 121.
The first ISO and second ISO caps C1 and C2 generally can have silicon oxide as their capacitor dielectric layer. The ISO caps and generally have a capacitor dielectric layer thickness of at least 4 μm to provide a nominal breakdown voltage of at least 2,000 Volts. The capacitor dielectric layer thickness is more generally 2 μm to 20 μm.
Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different semiconductor IC devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.
Disclosed aspects are further illustrated by the following specific Examples, which should not be construed as limiting the scope or content of this Disclosure in any way.
Data was simulated for a packaged MCM ISO device resembling the packaged MCM ISO device 300 in
The control distance from the bottom of the die pads to the bottom of the mold compound was 660 μm, and for the disclosed leadframe this distance due to die pad thinning was increased to 787 μm. The E field in the air at the bottom of the package was thus reduced by the disclosed leadframe having thinned die pad portions to mitigate lead to lead arcing through the air. The disclosed die pad having thinned die portions demonstrated that the E-field was reduced in an applied voltage range of 6.5 kV to 10 kV, where the E field volume vs. the device with the control leadframe was reduced about 0.1 mm3 (>3V/μm) at 6.5 kV bias (from 0.78 to 0.68 in mm3), and was reduced 0.47 mm3 (>3V/μm) under a 9 kV bias (from 8.33 to 7.84 in mm3).
Those skilled in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the above-described aspects without departing from the scope of this Disclosure.
