Patent Application
20240136287
This invention generally relates to semiconductors and, more specifically, relates to local VDD and VSS power supply through dummy gates with gate tie-down.
In semiconductor devices formed using a backside power distribution network (BSPDN), there are some areas that could be improved. For instance, a source/drain (S/D) epitaxial silicon (epi) area may have to connect to the backside through a via-to-buried power rail (VBPR). As another example and because of the VBPR, another S/D epitaxial silicon area may only access one signal track above (e.g., near the back end of line, BEOL, area).
Concerning the VBPR and similar technologies, consider Divya Prasad, et al., “Buried Power Rails and Back-side Power Grids: Arm CPU Power Delivery Network Design Beyond 5 nm”, 2019 IEEE International Electron Devices Meeting (IEDM), which states the following about a Power Delivery Network (PDN): “To remove the overhead of power tap cells and the whole PDN, altogether, from the front side (which decouples the sharing of wiring resources between signals and power delivery), 3D integration techniques have been proposed to implement a back-side PDN where power is delivered using a small (‘micro’) Through-Silicon-Via (μTSV) that lands on the buried rail.” Multiple technologies are explored: “Three power-rail technologies are explored in this study”, “namely, the traditional Front-Side (FS) PDN, Front-Side with Buried-Power-Rails (FS-BPR) and Back-Side power delivery with Buried-Power-Rails (BS-BPR).” The FS-BPR and BS-BPR do not address the above issues and require a lot of extra processing steps.
This section is meant to be exemplary and not meant to be limiting.
In an exemplary embodiment, an integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer, and a frontside back end of line (BEOL) wire layer connected to the power supply rail through a gate. The gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. This provides power and/or ground access at the frontside BEOL wire layer without using a via-to-backside power rail, which frees space to allow certain source/drain (S/D) epitaxial regions to contact multiple signal tracks, one of which can be in an area not currently accessed, and also allows other S/D regions to be powered from tracks above the regions. Manufacturing is also minimally impacted, and this technique can be combined with current techniques, each used on different locations of the semiconductor wafer so that both conventional and new structures can be used on the same wafer.
Another example is an integrated circuit structure according to the previous wherein the gate is a first gate and the power supply rail is a first power supply rail. The integrated circuit structure further includes: a second power supply rail formed in the backside of the semiconductor wafer; and another frontside BEOL wire layer connected to the second power supply rail through a second gate, wherein the second gate is of a type to be powered off by a power supply coupled through the second gate from the second power supply rail to the other frontside BEOL wire layer. This allows multiple routings of power supplies to the frontside BEOL wire layer.
A further example is the integrated circuit structure according to the previous paragraph, wherein the first gate is an n-type gate and the power supply for the first gate is ground; and the second gate is a p-type gate, and the power supply for the first gate is power. Furthermore, the first and second gates may be formed adjacent to each other and isolated at least by a gate cut formed between the adjacent first and second gates. This allows both power and ground to be routed to frontside BEOL wire layers, e.g., using adjacent gates.
Another example is the integrated circuit structure, further comprising a frontside BEOL wire that is connected to one or more source/drain epitaxy silicon areas of corresponding transistors. An additional example is the integrated circuit structure according to the previous sentence, wherein the frontside BEOL wire is connected to the one or more source/drain epitaxy silicon areas of corresponding transistors using corresponding one or more vias. An additional example is the integrated circuit structure according to the first sentence of this paragraph, wherein the frontside BEOL wire layer is connected to the frontside BEOL wire. What these provide are the ability for a source/drain region to access multiple signal tracks, including one in N2N (n-type to n-type) semiconductor areas or in P2P (p-type to p-type) semiconductor areas, and another in NFET or PFET (respectively) areas.
A further example is a method of forming an integrated circuit structure, comprising the following: forming a power supply rail in a backside of a semiconductor wafer; forming a gate in the semiconductor wafer; and forming a frontside back end of line (BEOL) wire layer connected to the power supply rail through the gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. This provides power and/or ground access at the frontside BEOL wire layer without using a via-to-backside power rail, which frees space to allow certain source/drain (S/D) epitaxial regions to contact multiple signal tracks, one of which can be in an area not currently accessed, and also allows other S/D regions to be powered from tracks above the regions. Manufacturing is also minimally impacted, and this technique can be combined with current techniques, each used on different locations of the semiconductor wafer so that both conventional and new structures can be used on the same wafer.
Another example is a method according to the previous paragraph, wherein: forming the gate in the semiconductor wafer further comprises forming multiple gates on a substrate of the semiconductor wafer, wherein forming the multiple gates comprises: performing gate patterning to pattern multiple gates on a substrate, of which the gate is one; performing source/drain epitaxy to form source/drain regions for the multiple gates; performing interlayer dielectric deposition to cover at least the source/drain regions and at least partially isolating the multiple gates; and forming a frontside back end of line (BEOL) wire layer comprises forming BEOL interconnects and bonding a carrier wafer to the substrate on which the multiple gates have been formed.
A further method includes the method of the previous paragraph, wherein: forming the gate in the semiconductor wafer further comprises forming a backside gate-tie-down via at an edge of the gate and filling the backside gate-tie-down via with conductive material at a same time conductive material forming the gate is formed; the method further comprises forming a gate via contact to connect the gate having the gate-tie-down via to the frontside back end of line (BEOL) wire layer; and the method further comprises further comprises connecting the power supply rail to the gate-tie-down via.
Another exemplary method further comprises forming a source/drain contact contacting a corresponding source/drain region and extending beyond the source/drain region to provide access to one of a signal track that is in a region between two doped regions of the same type and a signal track that is within the doped region.
What these provide are the ability for a source/drain region to access multiple signal tracks, including one in N2N (n-type to n-type) semiconductor areas or P2P (p-type to p-type) semiconductor areas, and another in NFET or PFET (respectively) areas.
Another method further comprises connecting one or more source/drain regions of corresponding one or more others of the multiple gates which need power supplies to one or more corresponding frontside BEOL wires, the one or more corresponding frontside BEOL wires connected to the frontside back end of line (BEOL) wire layer.
A further method includes a method wherein: the gate is a first gate and the power supply rail is a first power supply rail; the method further comprises: forming a second power supply rail formed in the backside of the semiconductor wafer; and forming another frontside BEOL wire layer connected to the second power supply rail through a second gate, wherein the second gate is of a type to be powered off by a power supply coupled through the second gate from the second power supply rail to the other frontside BEOL wire layer; the first gate is an n-type gate and the power supply for the first gate is ground; and the second gate is a p-type gate, and the power supply for the first gate is power.
A further method includes the method of the previous paragraph, but wherein forming the first and second gates comprise forming the first and second gates adjacent to each other and the method comprises forming and filling a gate cut between the adjacent first and second gates.
These examples provide power and/or ground access at the frontside BEOL wire layer without using a via-to-backside power rail, which frees space to allow certain source/drain (S/D) epitaxial regions to contact multiple signal tracks, one of which can be in an area not currently accessed, and also allows other S/D regions to be powered from tracks above the regions.
Furthermore, these methods may be combined with current techniques, each used on different locations of the semiconductor wafer, e.g., meaning current designs do not have to be modified to implement the current improvements.
Abbreviations that may be found in the specification and/or the drawing figures are defined below, at the end of the detailed description section.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this Detailed Description are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims.
The instant disclosure concerns the front-end-of-line (FEOL), the middle-of-line (MOL) and the back-end-of-line (BEOL). An introduction to these concepts is now presented. The FEOL covers the processing of the active parts of the chips, i.e., the transistors that reside on the bottom of the chip. The BEOL, the final stage of processing, refers to the metal layer interconnects that reside in the top part of the chip. The FEOL and the BEOL are tied together by the MOL. The MOL is typically made up of metal structures that serve as contacts to the transistor's source, drain, and gate. These structures connect to the local interconnect layers of the BEOL.
The architectures that make up the FEOL may include gate-all-around (GAA) nanosheet, forksheet, and complementary field effect transistor (CFET) devices. The architectures of these devices impact the local interconnect layers, calling for different BEOL materials (such as ruthenium (Ru), molybdenum (Mo), and metal alloys) and various integration schemes (such as hybrid metallization, semi-damascene, and hybrid-height with zero via structures). Vias-to-backside-power-rail (VBPRs) are part of the power delivery network and may be used in MOL to wire some terminals of the transistors to backside power distribution network as help to reduce the congestion in lower BEOL.
Now that an introduction to the FEOL, the MOL, and the BEOL has been provided, as stated above, in semiconductor devices formed using a backside power distribution network (BSPDN), there are some areas that could be improved. These are shown via a figure, described below, but the following are issues with conventional techniques: a source/drain (S/D) epitaxial silicon (epi) area may have to connect to the backside through a via-to-backside power rail (VBPR); and/or another S/D epitaxial silicon area may only access one signal track above (e.g., near the back end of line, BEOL, area). Further, there is typically no access to a signal track in N2N or P2P regions. Thus, a gate tie-down to backside power rail offers opportunity to re-design the routings locally by power supply from dummy gates with a gate tie-down. These issues are addressed herein, and figures of semiconductor devices illustrating a conventional POR (process of record) are described.
Consider
By contrast,
Techniques to remove the VBPR for one or both of VDD or VSS are described herein, but include forming and using a “dummy” gate to provide a bridge from a power supply rail in the backside to the frontside BEOL wiring. This is described in much more detail below, but such dummy gates 1130 can be seen at least in
Furthermore, there are advantages in manufacturing. One such advantage is that multiple gates are already being formed, so there are only a few extra steps to create a gate or gates with corresponding gate tie downs, which then provide the benefits as described above and herein.
Additionally, the techniques herein are fully compatible with the POR process (e.g., as illustrated by
These improvements address the deficiencies described above.
An integrated circuit structure may therefore include the following:
Additional examples include the following.
As an overview of the exemplary embodiments, an example process flow, e.g., to form the integrated circuit structure 2, at least in part, is illustrated as the following:
As will be described further in text and corresponding figures below, an overview of an exemplary semiconductor device can include the following:
The following figures illustrate an exemplary process flow, e.g., for the previously described method and to form the integrated circuit structure 2.
Although gate areas 115 and dummy gate area 117 are illustrated in
As can be seen, the OPL coating 210 and HM 155 have been removed.
The local VSS 740 or VDD 750 is part of BEOL (in M1), and it supplies ground or power, respectively, for only few transistors nearby, therefore it is referred to as “local” (as contrasted with “global”). A more specific definition is the following: a local VSS/VDD is a segment of M1 wire, which only supplies power for transistors within 10 contacted poly pitch (CPP).
As indicated by reference 780, by introducing local VSS 740 and/or local VDD 750, the S/D can be powered directly, and neighboring S/D epitaxial regions can access a signal track within N2N, P2P regions. That is, the local VSS 740-1 is introduced, so the S/D epitaxial region 410-1 can be powered directly (e.g., instead of having to connect through a VBPR to the backside VSS as illustrated in
Furthermore, the ground rail 1160-1 and power rail 1160-2 can be generalized to a power supply rail 1160, as both VSS and VDD are power supplies. That is, VSS is the power supply for NFET, and VDD is the power supply for PFET.
There are two dummy gates 1130 illustrated, an N-dummy gate 1130-1 and a P-dummy gate 1130-2. The N-dummy gate 1130-1 uses an NFET area 140, and the P-dummy gate 1130-2 uses a PFET area 130. The N-dummy gate 1130-1 and the P-dummy gate 1130-2 are isolated from each other at least by the gate cut 510-1, though other techniques could be used for isolation. The N-dummy gate 1130-1 can be isolated from the N-active gate 1140-1 (having a gate that uses S/D regions of the corresponding NFET area 140 to form a corresponding NFET) by the gate cut 510-2. Note that the gate 1140-1 is not active in this example (e.g., there is no via VB connected to the channel region), but the gate could be active in other examples. The P-dummy gate 1130-2 can be isolated from the P-active gate 1140-2 (having a channel formed within the gate region and using the corresponding PFET area 130 to form a corresponding PFET) by the gate cut 510-3.
A gate-tie-down means the device is turned off by its gate. For an NFET, it needs to be turned off by adding a VSS power supply to the gate. This is the way N-dummy gate 1130-1 is constructed, e.g., using the ground rail 1160-1. For a PFET, it needs to be turned off by adding a VDD power supply to the gate to turn off. This is the way P-dummy gate 1130-2 is constructed, e.g., using power rail 1160-2.
As illustrated, ground rail 1160-1 and its corresponding gate 1130-1 and the power rail 1160-2 and its corresponding gate 1130-2 are adjacent. It is noted that there could be two adjacent ground rails 1160-1 and corresponding gates 1130-1, or two adjacent power rails 1160-1 and corresponding gates 1130-2, if desired, although the dummy gate 117 would have to span two NFET regions or two PFET regions, respectively, instead of spanning an NFET region and a PFET region as in the above examples.
Turning to
The local VDD region 750 is illustrated in
In the foregoing description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be appreciated by one of ordinary skill of the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may have been omitted or may have not been described in order to avoid obscuring the presented embodiments. It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly” over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “in direct contact”, “abutting”, “directly adjacent to”, “immediately adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
