Patent Application
20210319984
This invention relates to a plasma etching device according to claim 1 and a process to plasma-etch a semiconductor substrate in such a plasma etching device according to claim 20.
AMOLED active matrix organic light emitting diode
CCDs charge-coupled device sensor
CH4 methane gas
CTE coefficient of thermal expansion
ESC electrostatic chuck
ICP inductively coupled plasma
ITO oxide of indium and tin (InxSnyOz)
LCD liquid crystal display
LED light emitting diode
RIE reactive Ion etching
TCO transparent conductive oxide, e.g. ITO or zinc oxide (ZnO)
For Langmuir measurements to optimize systematically certain plasma parameters like ion and electron densities (Ne and Ni, [cm−3]), floating and plasma potentials (Vf and Vp, [V]), electron temperature (Te [eV]) and ion flux (Ii [mA cm−2]) a Smart Probe™ automated modified Langmuir probe plasma diagnostic device from Scientific Systems has been used in a circular etching compartment of a CLN300E multi-chamber system, having a diameter of 480 mm and a height of 162 from the pedestal to the top. A modified flexible probe with a tip length of 6 mm and tip radius 0.7 mm has been moved through the grounded shields in the plasma in parallel to the pedestal/wafer surface in a distance of about 20 mm. For the test series a low pressure of about 0.1 Pa and a high pressure of about 0.5 Pa has been used. A MF-power of 1'000 W, at a frequency of 400 kHz has been applied by an MF-source to a 15 loops coil wound around the etching compartment. Such a basis configuration has been also used for further tests without Langmuir probe measurement using different gas mixtures and varying MF and RF-power. The measurement system has been triggered by an external trigger having a frequency >100 kHz wherewith a sawtooth signal from −50 to +50 V has been applied to the probe.
For particle measurement on a wafer surface after the etching process a Reflex Table Top laser surface analyzer from NanoPhotonics has been used. Thereby an ellipsoidal mirror is located so that its first focal point coincides with the laser spot on the wafer surface. It collects all light scattered from that point and focuses it in the second focal point, where a diaphragm is placed. The diaphragm allows only light coming from the laser spot to pass, thus reducing the effects of external illumination. Two flat mirrors are used to change the direction of light and thus make overall system smaller in size. Since such optical system is symmetrical relatively to the axis that is perpendicular to wafer surface, the amount of collected scattered light is independent of particle orientation relative to the optics. Such systems are capable in counting particles and characterize these in size as well as distinguish from scratches or haze effects on the wafer surface. They are used as standard system in the semiconductor metrology.
“Pasting” processes are processes using essentially the same setup as with production processes to sputter a material capable of gettering water vapor or volatile organic compounds from a substrate of the same dimensions as the product substrates. Basically the same process parameters can be used as for the product substrates, however in many cases slight modifications as a longer etch time and/or different sputter gases and/or pressure is applied. Pasting is seen as an alternative to either a time consuming shield change or a real back-etching of the films deposited on the walls, which is in many cases not possible or requires very aggressive plasma chemistry. Pasting is usually seen as a “reset” of the chamber to defined wall conditions, nevertheless after a certain period a shield change is usually required.
Opto-electronic devices such as displays (LCDs, AMOLEDs, micro-LED), sensors (CCDs), amorphous silicon solar cells and the like often include thin-film transparent electrodes placed over a light transmitting or light emitting element. The transparent electrodes are typically composed of transparent conductive oxide (TCO). Typical examples of TCO are oxide of zinc (ZnO) and oxides of indium and tin (InxSnyOz; e.g. 90% In2O3 and 10% SnO2) commonly labeled as ITO. During the manufacturing the electrode material is deposited as a thin-film of TCO on a substrate. Thereafter the TCO is selectively etched to remove pre-selected portions and thereby define desired conductive paths or wiring. New developments, as for example in displays with very high definition and ultra-high resolution require to define the conductive TCO areas with very narrow line and space within sub-micron dimensions, whereto more effective micro/nanoscale processing is required. Thus, aspect ratios and critical dimensions of etched lines and islands together with a very tight particle specification are requested. Furthermore the TCO processes are towards the end of the entire process flow and such substrates or wafers are of considerable high value wherefore manufacturing yield plays an important role, so that front end particle specifications of at the maximum 0.04 particles >0.2 μm per cm2 are applied to TCO processes, which refers to less than thirty particles (<30 pcs) of a size bigger than 0.2 μm in at least one dimension are allowed on a 300 mm wafer.
Such tight restrictions cannot be met easily with state of the art equipment for high volume production. To allow to meet such tight particle restriction more easily is one aim of the present invention which can be reached by an etching device and an etching process as disclosed in the following. This aim goes in line with the aim to provide an etching device of high flexibility with reference to the temperature management of different parts of the etching compartment. A further aim is to provide a device and a process whereby a wafer substrate can be heated fast to a high temperature of about 100° C. or more and hold at that temperature during the etching process without exceeding a maximum temperature critically for the substrate material. Which means in other words to hold and stabilize the substrate temperature under a high energy flux from the ICP-plasma and thermal load from the substrate bias. Another aim is to reduce essentially the number of service and pasting steps used to upheld high process specifications.
In an embodiment of the present invention the Plasma etching device comprises a vacuum chamber for at least one plate shaped substrate with side walls looping around a central axis A, the chamber including
It should be mentioned that in a basic version of the invention heating and cooling means and further or as mentioned below supplementary heating and/or cooling means can be supplied by a first heating and cooling device with respective heating or cooling fluid according to the process needs.
In a further embodiment the chamber may comprise temperature control means connected to the heating and cooling means to control heating and cooling of the pedestal and keep the substrate at a constant temperature between 30° and 200° C., e.g. between 60° and 180° C., see also table 1 below. The control means may comprise a control circuit to set heating power and/or cooling power in dependency of the substrate temperature measured by a temperature measurement device.
Additionally a lower shield which constitutes the surface of the second electrode can be connected to supplementary heating and/or cooling means or comprise supplementary heating and/or cooling means to keep the lower shield at a constant temperature, e.g. from −40° C. to 100° C. Similar to heating and cooling means or further heating and/or cooling means as mentioned above these supplementary heating and/or cooling means may be connected with temperature control means to hold the lower shield on constant temperature or adjust temperature to certain process needs (see also table 1 below).
Thereby at least one of the first heating means, further heating means, and supplementary heating means may comprise an electrical resistance heating device, a radiation heating device or at least one heating circuit comprising a heating fluid, and at least one of the first cooling means, further cooling means, and supplementary cooling means may comprise at least one cooling circuit encompassing a cooling fluid.
In addition, at least one of the first heating means, further heating means, and supplementary heating means may comprise a fluid circuit the intake of which is connected to two fluid reservoirs of different temperature and a mixing unit to set the heating/cooling temperature. The at least one heating and/or cooling circuit can be mounted within the chamber wall to heat or cool at least one of the shields by an extensive contact area between respective surfaces of the wall and shield.
The at least one gas inlet can be connected to the chamber or to the reservoirs of a reductive and an inert gas by usual pipes and gas lines and/or metering devices, e.g. mass-flowmeter control devices (MFCs), to meter the respective gas proportions. An additional inlet connected via additional gas lines ending in channels or cavities within the surface of the pedestal or the ESC directly below the wafer can be further connected to a cool gas reservoir which usually will be an inert gas too, e.g. Ar. Any valves as disclosed can be replaced by one or several MFCs when MFCs are provided with a secure gas stop function.
The reductive gas may comprise at least one of hydrogen, and a hydrocarbon gas volatile at room temperature and the inert gas may comprises at least one of Argon (Ar), Helium (He), Neon (Ne) and Xenon (Xenon). In one embodiment which has proofed to be very efficient in terms of low particle emission the reductive gas comprises hydrogen (H2) and methane (CH4) and the inert gas is Argon (Ar).
To avoid eddy current losses of ICP power within the screen, the screen shield can be slotted essentially in parallel to a central axis (A) of the pedestal, whereby slots can be tilted, e.g. from 25° to 45°, with reference to a radial direction originating from central axis A, to avoid a line of sight connection between the plasma and the sidewall and/or the bottom wall which also can be a part of the lower sidewall.
The upper shield and the screen-shield can be made as a single piece element, which can be formed pot-like and mounted upside down above the pedestal, whereby easy mounting and demounting for service is assured, e.g. via swiveling the pedestal and connected systems (depending on the actual construction: pedestal base, darkroom shield, first voltage source, lower sidewall, . . . ) by 180° or a service top cover which can be opened or lift of from the chamber.
In a further embodiment the thermal contact between the pedestal and the wafer may be improved by an electrostatic chuck (ESC), which can be foreseen in addition to mechanical clamping or alone if shadowing or stress by mechanical clamping should be avoided.
A further aim of the actual invention is to provide a process to plasma-etch a semiconductor substrate, e.g. a wafer, using a plasma etching device as disclosed above. Whereby as an example transparent conductive oxide (TCO) layers, having light transmitting or light emitting properties, like for instance indium tin oxide (ITO) or zinc oxide, can be etched from the substrate in the vacuum etching-chamber. Such layers may be masked partially by a photo resist to structure the surface of the substrate/wafer. Such a process comprises the following steps:
The reductive gas may comprise or consist of at least one of a hydrocarbon being volatile at room temperature, which can be methane, and hydrogen. Other hydrocarbons could be other volatile alkanes, like ethane, propane, cyclopropane, butane, however small molecules with single carbon-bonds are preferred to avoid plasma polymerization. When methane is used a proportion from 10 to 50% can be adjusted in the gas mixture. Hydrogen can be used alone or together with a hydrocarbon, e.g. methane, in a proportion from 5 to 30% in the gas mixture. In one embodiment which has proofed to be very efficient in terms of low particle emission the reductive gas comprises hydrogen (H2) and methane (CH4) and the inert gas is Argon (Ar).
A substrate surface to be etched can be heated to or near an etch temperature between 30° and 200° C. by at least one of heating the pedestal with heating and cooling means and heating a substrate surface by radiation heating. Thereby controlling of the substrate temperature especially when in the following etching of the surface takes place plays an important role. Therefor a control circuit may be used during the process to keep the etch temperature constant within ±10° C. by at least controlling the temperature of the pedestal in a temperature region from −40 to 200° C. in dependency of at least one of a pedestal or shield reference temperature measured with an electric temperature measurement device (37′) and/or a substrate reference temperature measured with an optic measurement device (37) at the back-side surface of the substrate. This control value or values can be used to control the first heating/cooling device, e.g. via a central control panel, to regulate flow and temperature of a heating/cooling fluid or the power of a radiation heater as examples. It should be mentioned that this may comprise a considerable change in the heat to be fed to or taken from the pedestal. E.g. at the beginning of a process heat has to be transferred from the pedestal to the substrate, which may be an ITO coated and photo resist masked wafer. After having reached a process temperature of 100 to 120° C. the etching process starts whereby depending on the etch energy used, the surface temperature as well as the temperature of the substrate itself could quickly rise, without controlled change of temperature flow from the heating and cooling means. Whereby, as an example, a cold fluid could be admixed to the heating fluid or even could replace that fluid completely at the beginning or during any point of time during the etching process, where mixing can be performed stepwise or in a continuous way.
A temperature measurement device as used to control the temperature of the pedestal or one of the (electrode) shields may comprise at least one of a thermocouple, thermistor, resistance temperature detector (RTD) in a surface, e.g. of the pedestal or a shield, or a remote, e.g. optic measurement device for a substrate surface, a pedestal surface or a shield surface exposed to etching. Whereby primarily such control circuits and measurement devices will be foreseen with the pedestal or a pedestal surface in close vicinity to the substrate which can be combined with a remote back-side surface measurement of the substrate itself to enable an even tighter temperature control as a function of two temperatures or temperature profiles. As remote measurement devices optical devices like infrared measurement devices or a pyrometer can be used.
To improve thermal contact between wafer and pedestal an electrostatic chuck (ESC) can be used.
Tempering may comprise also the heating of the third electrode shield(s), which are the upper shield and the screen shield, to a temperature between 30° and 100° C., to avoid largely the formation of layers from etching residuals, e.g. from etched ITO surfaces, by reacting such residuals on the surface to volatile compounds. For that purpose the partial pressure of the at least one reductive gas, e.g. methane (CH4) or hydrogen and methane, can be set to avoid mostly deposition of oxidized species at least on the surface of the upper shield and screen-shield. Especially when using relatively thick shields of 3 to 6 mm thickness, the further heating and/or cooling means need not be to be coupled directly to all shields of the third electrode but may be confined to a tight thermal contact between the top wall and the upper shield whereby adequate heat flow can be provided from the upper shield to the screen shield for tempering, e.g. during loading, preheating or a service step, and vice versa if cooling is necessary during the etching process.
Tempering may also comprise heating or cooling of the lower shield(s) to a temperature between −40° (minus forty) and 100° C. This may vary up to the specific process needs and simplicity of process by either keep the lower shield cooler than other surfaces in the chamber to trap particles which could not be reacted to volatile compounds and be pumped away, or keeping the lower shield of the second electrode at the same temperature like the other shields, which would allow to use the same further heating and cooling device for the shields of the 2nd electrode (lower shield) and the 3rd electrode (screen shield and upper shield).
As a rule of thumb, temperature ranges which should be able to be applied to different parts of the vacuum chamber to meet the needs of different etching processes as discussed above can be found in table 1 below. The highest flexibility can be met with a chamber where temperature ranges as given in column ΔT flex can be applied to substrate(s), pedestal and different shields in the chamber, whereas column ΔT opt gives the temperature range where best results for usual RIE processes on TCO or ITO coated wafers, e.g. silicon wafers, could be achieved in terms of fast etching rate and low particle emission. Whereas ΔT med gives a good mixture of high process flexibility and good results.
Thereby the first voltage-source is an RF-source and can be driven with a frequency from 2 MHz to 30 MHz, or from 3 to 27.01 MHz, or at 13.56 MHz. Thereby a power in the range from 0.3 Wcm−2 to 1.4 Wcm−2, or from 0.6 Wcm−2 to 0.8 Wcm−2 should be applied.
The second voltage-source, which is the ICP-source is an MF-source and can be driven with a frequency from 300 to 2'100 Hz, or from 350 to 600 Hz. Thereby a power of 600 to 1200 W should be applied to the coil by the second source giving an electron density from 1 e10 cm−3 to 5 e11 cm−3 or from 3 e10 cm−3 to 3 e11 cm−3.
By applying such inventive processes to an ITO coated wafer, an ITO-etch rate of 0.6 to 1.2 nm/s can be achieved.
Further on a series of inventive processes as described above is disclosed which are characterized by a pasting parameter
P{f
PR_cov}=(No of produced wafers)/(No of pasting wafers),
for, e.g. single or multiple wafer processes where PR_cov is the surface coverage of the TCO layer, e.g. an ITO layer, with photo resist, and P{fPR_cov} can be chosen at least within one of the following ranges from P(PR_Cov) at least to P(PR_Cov) opt as shown in table 2 below, whereby PR_Cov refers to different surface coverages of a TCO-coated wafer:
Thereby an in film adders count could be measured consistently below 30, for particles >0.2 μm, for every single process, which means that there are less than 30 submicron defects on the whole surface of a 300 mm wafer. This again shows the high potential of the present inventive process as state of the art processes often need a pasting parameter between P {fPR_cov} 1 and 10 to keep process dust in adequate levels.
Further on a series of inventive processes as described above is disclosed which are characterized in that shield temperature(s) of at least the screen shield and the upper shield is(are) constantly held at elevated temperatures before, during and after the first process of a series and in between the single processes of the series, e.g. in accordance to the necessities of the pasting processes strongly depending on the photoresist coverage as mentioned above from 25 to 50, from 100 to 200 or 2'000 to 10'000 RIE processes, until the shield(s) are changed for service. Thereby essentially constant heat conditioning before processing as well as in idle times is applied.
The invention shall now be further described with the help of schematically and simplified figures and examples. With figures as described in the following same reference numbers refer to same features or at least features having the same function:
Etching of wafer blanks as well as etching TCO-coated, e.g. ITO-coated wafers has been performed on a Clusterline CLN300E multi-chamber system from Evatec AG equipped with an lop Etch Module 1 modified according to the present invention, which is merely schematically shown in
Second and third electrode 12, 13 are counter electrodes which both are connected to ground potential. The shields 12 of the second electrode are looped around the pedestal 12 in observance of a dark room distance to separate the etching compartment 31 from the pumping compartment 32 and have at least one respective opening, like a slit or a grid covered opening, to enable a high pumping conductance towards the vacuum pump system 4 comprising pump valve 6, high vacuum pump 5 and exhaust valve 7, the latter leading to a backing pump (not shown). A dark space shield 55 protects the circumference of the pedestal and its cylindrical base; at least where the base is too on RF-potential.
Upper shield 13′ and screen shield 13″ from the third electrode 13 are pot like and made from one piece for optimal thermal conductance, with a central gas inlet 34 connected to a first gas supply 20, comprising a first gas inlet valve 22, and first gas reservoir comprising a sub reservoir 21 for Argon or another inert gas and two sub reservoirs 21′ for reducing gas, here methane and hydrogen. The shield 13′ is mounted in tight thermal contact to the top-wall 19 which comprises a further internal liquid circuit 36 connected to a further (2nd) heating/cooling device via further (2nd) heating/cooling lines. Additionally shields 12 of the second electrode could be cooled by supplementary (2nd) heating/cooling lines 29′—shown in dashed lines—which can be connected to the further heating/cooling device 17 or to a separate heating/cooling device 29.
The vacuum chamber 2 is confined by a bottom wall 30, the top wall 19 and sidewalls 18, 18′ and houses the etching 31 and the pumping compartment 32. The bottom wall 30 comprises the feed through 46 for the basis 33 of the pedestal wherein also respective electrical, cooling liquid and gas feed throughs for the pedestal 11 are foreseen. The top wall 19, comprises connections for the as mentioned further internal liquid circuit 36 and a feed through for the central gas inlet 34. Bottom wall 30 and lower sidewall 18′ can form a metal surrounding wall and together with the lower shield 12 and the outer circumference of the basis 33, form the pumping compartment 32. Sidewalls with the present embodiment, that is with the pumping compartment below the etching compartment 31, comprise a lower sidewall 18′ round the pumping compartment, which is made from a usual stainless steel material or aluminium for vacuum equipment, and the upper side wall 18, looping around the central axis A and the etching compartment 31, which is made of aluminum oxide ceramics to enable inductive coupling from coil 9 to the etching compartment 31 where the inductively coupled plasma (ICP) is ignited. A coil 9 is looped around the upper sidewall and is connected with its first end 9′ to MF-supply 10, and with its second end 9″ to ground. A vacuum gauge 26 is attached to the lower sidewall 18′ to control pumping speed in dependency of the process parameters set.
Wafers 27 can be fed and discharged through a substrate handling opening 28—shown in dashed lines—to the “static” pedestal 11, which means that the pedestal is not moved in a vertical direction before a loading or discharging operation takes place. For loading and unloading movable (see vertical double arrow) pins 54 are used to receive the substrate 27 and to allow the fingers from the handler to lift the substrate from the pedestal. During the process pins 54 stay retracted in the pedestals 11, 11′ surface (not shown). As an additional feature a back gas supply 23, comprising a back gas reservoir 24, e.g. with Ar or Ne, and a back gas inlet valve 25 can be foreseen with at least one feedthrough to a channel-structure 39 having a high flow resistance in the surface of the pedestal 11 or the ESC, as far an ESC is used instead of mechanical clamping, to better heat or cool the substrate 27 under vacuum conditions. The channel-structure 39 may be e.g. cobweb or labyrinth like and thereby lead from a central feedthrough, or especially for wafers having diameters of 25 mm or more, be lead from several feedthroughs to the outer circumference and all areas of the pedestal or ESC 14. Due to the contact pressure produced by mechanical clamps or the ESC 14, with reference to the process pressure, a higher back gas pressure can be applied to the uncoated reverse side of the wafer 27 without disturbing leakage to the etching compartment 31.
With reference to a plasma treatment device 1 having a static chuck, e.g. a plasma etching device for at least one plate shaped substrate, such an embodiment of an inventive device may comprise the following features:
With reference to further embodiments and examples of a plasma etching device comprising a static chuck operated with lift pins, it is referred to WO 2017/215806 which is hereby integrated by reference in its entirety.
A further embodiment of an ICP-etch apparatus 1 is shown in
Further on
Langmuir probe 40 as used for plasma-diagnostic measurements can be seen to be placed slightly above the pedestal 11 and the wafer, whereby the probe tip could be positioned flexible from a peripheral zone outward a projected circumference of the pedestal 11 up to the center of the plasma round axis A as displayed by horizontal double arrow. Of course, such measurements have been made only with test cycles to avoid any pollution of a wafer surface during production due to dust formed on the surface of the measurement equipment.
With reference to a plasma etching device 1 having a dynamic, which is a movable, pedestal, such a device may comprise a vacuum chamber 2 and within said vacuum chamber:
Said metal connectors may comprise plate shaped connectors and may be one of rigid and of resilient.
With reference to further embodiments and examples of a plasma etching device comprising a dynamic chuck, it is referred to WO 2017/207144 which is hereby integrated by reference in its entirety.
It should be mentioned that all features as shown or discussed in connection with only one of the embodiments of the present invention and not further discussed with other embodiments can be seen to be features well adapted to improve the performance of other embodiments of the present invention too, as long such a combination cannot be immediately recognized as being prima facie inexpedient for the man of art, as for instance using a movable metal tubular arrangement with a static pedestal. Therefor with the exception as mentioned all combinations of features of certain embodiments can be combined with other embodiments where such features are not mentioned explicitly and form part of the present invention.
For processes in the CLN300E equipment in general Argon was used as a process gas at low pressure of 0.1 Pa or high pressure of 0.5 Pa for etching of oxides or metal oxides. Therefor an Argon flow of about 5 sccm (low pressure) via the central gas inlet has been set. However, when state of the art etching processes using Ar gas only where performed on ITO full face (100%) coated semiconductors, particle performance was very poor as shown in
In the following process parameters where changed by tempering the shields 13, 13′ and the pedestal 11 with a fluid having a temperature slightly above 100° C. before the etching started so that a substrate surface temperature could be adjusted at 100±10° C. during the whole process with the help of an IR-measurement device used to control the heating and cooling means by the process control unit of the device, which switched the heating and cooling system from heating to cooling in the moment when excessive process heat has been induced by the RF- and MF-sources at the beginning of the etching process. Additionally, a methane portion of 10% to the Ar-flow has been used with the process gas. Thereby particle situation could be influenced in a very positive direction as shown in
However further experiments not discussed in detail here have been performed with separate heating and cooling means 16, 16′ and further heating means for the shields 13′ and 13″. Thereby substrate temperature could be lift even to a higher level to speed up the etching process and shield temperature could be held on a more constant level over a series of etching processes and loading and idle time between to minimize flaking of due to different CET between shield material and redeposited ITO layers or islands.
An additional positive effect could be seen when applying supplementary cooling means 29, 29′ to run lower shields 12 of the second electrode as a cool trap with about −30° C., therewith further minimizing the in film adders count of etched wafers.
A simplified mechanism of ITO etch and particle prevention could be therefore understood by the following basic steps:
As it can be easily seen the “ion-etching” step 3) and “reactive etching” step 4) are competing. Without ion etching however the process would be too slow. Also an etching process by radicals only will not provide a vertical etch profile under the etch mask which is in this case photoresist. On the other side reactive etching is in particular attacking less dense material, which is in particular prone to form particles. The reactive etching process by radicals also takes place on the chamber walls. To achieve low particle levels the process parameters are adjusted in a way to achieve the lowest deposition on the chamber walls.
Conditioning of the etching compartment by sputtering of pasting material like aluminium or titanium after a certain number (wafer count) of ITO etch processes, which is known as “pasting”, can also be used to decrease particle adders. This is common practice especially for etch processes on substrates comprising polymers on the surface. Such tests have been performed immediately after an etching process had been run with Ar gas. Thereby the particle count could be decreased below the specified level of 30 adders (not shown here). Pasting processes can also be applied by using in-situ pasting during the ITO etching process, when pasting material can be etched from parts of the pedestal made or coated with such material, e.g. an aluminium or titanium ring round the circumference of a wafer, and re-deposited on the shields. Alternatively pasting can be performed between a certain number of etching processes (wafer count) by etching pasting disks or wafers, made or coated from/with pasting material. With pasting processes, as an example the same parameters can be applied as with preceding etching processes with Ar only, whereby the kit life of the shields 12, 13 can be extended. At the same time the pasting parameter P{fPR_cov}=(No of produced wafers)/(No of pasting wafers), can be chosen much higher, e.g. by a factor 25 to 1'000 when applying inventive processes compared to state of the art ones, which altogether gives a considerably higher productivity and less rejection rate.
As ITO etch rate is enhanced by temperature the pedestal should be hold at temperatures above RT to 100° C. For this purpose also ESCs can be used to keep the wafer temperature close to pedestal temperature which can be further improved by back gas application as described above. In cases that a thicker ITO layer must be removed and substrates with photoresist masks are used, which have a temperature limit of 120° C., intense cooling of the wafer and pedestal may be required. Further on shield temperature can be adjusted to a temperature from −40 to +150° C. to avoid thermal cycling of the shields and thereby prevent particle generation based on mismatch between material CTE with tempered shields of the 3rd electrode to avoid layer formation and/or cooled shields of the 2nd electrode to trap volatile particles and dust.
Further on the following features and process parameters alone or in combination seem to foster low particle plasma etch processes combined with a high etching rate:
| Number | Date | Country | Kind |
|---|---|---|---|
| 00992/18 | Aug 2018 | CH | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2019/071674 | 8/13/2019 | WO | 00 |
