Patent Application
20060189045
This Utility Patent Application claims priority to German Patent Application No. DE 10 2005 001 902.1, filed on Jan. 14, 2005, which is incorporated herein by reference.
The present invention lies in the technical field of semiconductor components and relates in particular to a method for fabricating a sublithographic contact structure in a memory cell.
Phase change materials are regarded by experts as a basic material for a new, promising type of nonvolatile memory cells. Phase change materials can be brought—by heating—to different phase states which differ from one another in terms of their optical properties (in particular reflectivity) and electrical properties (in particular electrical resistance). The different phase states can be assigned different logic values, so that information items can be stored in memory cells based on phase change materials by supplying heat and can be read out again whilst utilizing the optical or electrical properties.
Suitable phase change materials are, in particular, chalcogenides, that is to say alloys containing at least one element from main group VI (chalcogenes) of the periodic table. With regard to the electrical properties, chalcogenides are advantageously distinguished in particular by the fact that their electrical resistance changes by a number of orders of magnitude if a change in the phase state between the amorphous phase and the crystalline phase is induced.
In memory cells based on phase change materials (called phase change memory cells or PC memory cells hereinafter), it is practical for a phase change to be induced by an electrical heating pulse (Joule heat). If the phase change material of the memory cell is in a high-resistance amorphous state, then it can be converted into a low-resistance crystalline state if a heating pulse heats the material above the crystallization temperature thereof and causes it to crystallize in the process. This operation is generally referred to as “writing to” (or “programming”) the memory cell. The reverse operation, in which the phase change material of the memory cell is converted from the low-resistance crystalline state to the high-resistance amorphous state, is realized by heating the phase change material beyond the melting point and subsequently quenching it by rapid cooling into the amorphous state. This is generally referred to as “erasing” the memory cell.
A typical construction of a PC memory cell of the bottom contact type is shown schematically in
As has already been explained further above, the phase state of a memory cell can be read out electrically, inter alia, a read voltage being applied to the memory cell. In order to ensure that the read voltage does not effect unintentional reprogramming of the memory cell, the current Iread through the memory cell which results from the read voltage must be significantly smaller than the programming current Iset or erase current Ireset. The following relationship Iread<<Iset<Ireset holds true in this case.
One essential disadvantage of such PC memory cells resides in the fact that relatively high currents have to be applied for the write operation, and in particular for the erase operation, in order to heat the phase change medium beyond the crystallization temperature and, respectively, the melting point.
In order to solve this problem, it has primarily been attempted hitherto to reduce the volume to be programmed by means of reducing the contact area between the electrodes and the phase change material, since the currents required for writing and erasure generally scale with the volume to be programmed. However, limits are imposed on this undertaking by the minimum dimensions that can be achieved photolithographically. With the optical (UV)-lithographic techniques available at the present time, it is possible, as is known to the person skilled in the art, to achieve a minimum lithographic dimension (F) of only approximately 50 nm. However, much smaller minimum dimensions would be desirable for reducing the maximum current for writing to or erasing the memory cells.
The present invention provides a method for fabricating a sublithographic contact structure in a memory cell in a semiconductor component. In one embodiment, the method includes forming a trench structure having first spacers on walls of the trench structure, a first sublithographic dimension being formed in a region between the first spacers situated on mutually opposite walls in at least one direction parallel to a wafer surface. The insulator layer is etched in a region between the first spacers situated on mutually opposite walls for forming a first passage hole, the first spacers being used as an etching mask. A layer made of an electrically conductive material is deposited at least over the first passage hole and partially etching back the layer made of the electrically conductive material in the first passage hole forming a first contact electrode. A layer made of a resistance change material is deposited over the first passage hole and partially etching back the resistance change material in the first passage hole forming a resistance change material zone.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
The present invention provides a method for fabricating a sublithographic contact structure by means of which it is possible to realize a memory cell which can be switched between two states having a mutually different electrical resistance using comparatively small electric currents. With regard to mass production of such memory components, a method of this type is intended to be able to be carried out simply and cost-effectively.
According to one embodiment, the invention provides a method for fabricating a sublithographic contact structure of a resistance change material memory cell having a resistance change material and first and second contact electrodes adjoining the resistance change material.
The method includes providing a semiconductor wafer processed by front-end-of-line (FEOL) processing known to a person skilled in the art. In this case, the semiconductor wafer has at least one electrical connecting contact (e.g. “plug”) connected to an active structure (e.g., transistor, in particular MOS field effect transistor) on one of its two opposite surfaces parallel to one another. The connecting contact may be produced in a conventional manner for example from W, TiW, TiSiN, TaSiN or TiAlN. Hereinafter, “the wafer surface” always means that surface of the semiconductor wafer which is provided with the connecting contact.
Afterward, a first insulator layer made of a first insulating, dielectric material is deposited on the wafer surface at least over the connecting contact. Although further insulating layers may be present in the semiconductor component, here the expression “first insulator layer” means that layer made of an insulating, dielectric material which is deposited on the semiconductor wafer at least over the electrical connecting contact thereof. The insulator layer may comprise SiO2 or SiN, by way of example.
A trench structure is thereupon formed in the first insulator layer, trench structure being equipped with a bottom that is preferably essentially parallel to the wafer surface and walls that are essentially perpendicular to the wafer surface. In this case, the trench structure is positioned at least partially over the electrical connecting contact.
In a first embodiment of the method according to the invention, the trench structure may be formed such that firstly an etching stop layer, e.g. comprising SiN, is deposited on the first insulator layer, and it is subsequently patterned by application of conventional exposure technology for the purpose of forming an etching mask. Afterward, the first insulator layer is partially etched with the aid of the etching mask for the purpose of forming a trench structure.
As an alternative to this, in a second embodiment of the method according to the invention, the trench structure may be formed in such a way that firstly an etching stop layer is deposited on the first insulator layer and it is patterned in a conventional manner for the purpose of forming an etching mask. The first insulator layer is then etched as far as the connecting contact with the aid of the etching mask for the purpose of forming a passage hole, a second insulator layer made of a second dielectric material, which is different from the first dielectric material, thereupon being deposited at least over the passage hole and being partially etched back in the passage hole for the purpose of forming a trench structure. The second embodiment of the method according to the invention has an advantage over its first embodiment that the properties of the second dielectric can be chosen in a desired manner, to be precise independently of the properties of the first dielectric. According to the invention, it is preferred, for example, to choose the thermal conductivity of the second dielectric material to be lower than the thermal conductivity of the first dielectric material, so that, in a particularly advantageous manner, the sublithographic contact structure formed within the second dielectric can be provided with surroundings that inhibit the dissipation of heat. This measure contributes appreciably to reducing the power loss and lowering the maximum current consumption.
Irrespective of which of the above embodiments was carried out, in the method according to the invention a first layer made of a spacer material is thereupon deposited at least over the trench structure. In this case, the spacer material is to be chosen such that it can fulfill a function as an etching stop layer. Accordingly, the spacer material may comprise SiN, by way of example. The layer made of the spacer material is subsequently etched back anisotropically as far as the bottom of the trench structure in a direction essentially perpendicular to the wafer surface, the anisotropic etching-back of the spacer material layer having the effect that first spacers remain on the walls of the trench structure, as is explained in more detail further below. In this case, the thickness or lateral dimension, that is to say dimension of the spacer layer material in a direction parallel to the wafer surface, is chosen such that a first sublithographic dimension is formed in a region between the first spacers situated on mutually opposite walls in at least one direction parallel to the wafer surface. In other words, there is at least one distance between the first spacers on mutually opposite walls of the trench structure which has a sublithographic dimension.
As a further process, the insulator layer is etched at least in the region between the first spacers situated on mutually opposite walls as far as the connecting contact for the purpose of forming a first passage hole, the first spacers being used as an etching mask.
A layer made of an electrically conductive material is then deposited at least over the first passage hole and partially etched back in the first passage hole in order thereby to form a first contact electrode.
In this embodiment, the first contact electrode is preferably configured in the form of a heating electrode, that is to say includes an electrically conductive material having a higher electrical resistance than the resistance change material that is in an electrical contact therewith.
In order to fabricate the sublithographic contact structure, in one method according to the invention, a layer made of a resistance change material is furthermore deposited at least over the trench structure and is partially etched back in the first passage hole for the purpose of forming a resistance change material zone. Afterward, a layer made of an electrically conductive material is deposited at least on the resistance change material zone for the purpose of forming a second electrode. Usually, the layer made of an electrically conductive material is additionally removed outside the trench structure, which may be effected by means of chemical mechanical polishing, by way of example.
The method according to the invention makes it possible to fabricate a sublithographic contact structure in a resistance change material memory cell by using the spacers on the trench structure walls as an etching mask to form a first passage hole having at least one sublithographic dimension in a direction parallel to the wafer surface, in which the sublithographic contact structure is then formed by depositing and etching back the different layers in stack form. In this way, a contact area is produced between the first contact electrode and the resistance change material, and a contact area is produced between the second contact electrode and the resistance change material, with at least one sublithographic dimension in a direction parallel to the wafer surface.
In accordance with a embodiment of the two above embodiments of the method according to the invention, after depositing the layer made of an electrically conductive material and partially etching back this layer in the first passage hole for the purpose of forming the first contact electrode, a layer made of a resistance change material is deposited at least over the passage hole and afterward both the first spacers and the resistance change material situated between the latter in the trench structure are removed, for example by etching. Afterward, a second layer made of a spacer material, which is intended to serve as an etching mask and may accordingly comprise SiN, by way of example, is deposited at least over the trench structure and etched back anisotropically until the resistance change material is uncovered in a direction essentially perpendicular to the wafer surface, spacer layer material remaining on the walls of the trench structure, said material forming second spacers which form a second sublithographic dimension in at least one direction parallel to the wafer surface. In this embodiment, the second sublithographic dimension is advantageously different from the first sublithographic dimension, which can be achieved in a simple manner by choosing the layer thickness of the second deposited spacer material layer to be different from the layer thickness of the first deposited spacer material layer. Furthermore, a layer made of an electrically conductive material is deposited on the resistance change material for the purpose of forming a second contact electrode on the trench structure, which material is usually removed outside the trench structure by chemical mechanical polishing, by way of example. The deposition and etching-back of the second spacer material layer has the advantageous effect that the size of the contact area between the second contact electrode and the resistance change material can be formed independently of the size of the contact area between the first contact electrode and the resistance change material and can thus be adapted to different requirements in a desired manner. Thus, the second sublithographic dimension may for example and preferably be smaller than the first sublithographic dimension, so that the contact area between the second contact electrode and the resistance change material is smaller than the contact area between the first contact electrode and the resistance change material.
In accordance with a further particularly advantageous variant of the method according to the invention, after depositing the layer made of an electrically conductive material on the resistance change material for the purpose of forming the second contact electrode, firstly the first and second spacers and the electrically conductive material situated between the latter are partially etched back. Afterward, in a direction essentially parallel to the wafer surface, the spacers on the walls of the trench structure are partially etched back isotropically (e.g. by wet-chemical etching) for the purpose of increasing the distance between the spacers situated on opposite walls in a direction parallel to the wafer surface. In other words, the partial isotropic etching-back effects a partial removal of the spacers from the trench structure walls, thereby enlarging the region between the spacers situated on opposite walls of the trench structure, thereby partially uncovering the surface of the second dielectric in the trench structure from above. A selective isotropic etching of the second dielectric material is subsequently carried out, which may be effected wet-chemically, by way of example. In this case, the etching attack takes place on the partially uncovered surface of the second dielectric material, the second dielectric material advantageously and preferably being completely removed. In other words, the selective removal of the second dielectric material uncovers the sublithographic contact structure constructed from a layer stack, a gap arising between the layer stack of the sublithographic contact structure, in particular the second contact electrode, and the spacer material. A third insulator layer made of a third dielectric material is then deposited conformally at least in the region of the trench structure, which has the effect that the region laterally with respect to the layer stack of the sublithographic contact structure is filled with the third dielectric material until the gap between the layer stack of the sublithographic contact structure and the spacer material has grown over. Once the gap has grown over, the deposited third dielectric material thereupon grows only above the layer stack. The final step involves additionally forming an electrically conductive connection to the second contact electrode in the third insulator layer. Since, in this variant of the second embodiment of the method according to the invention, the original volume of the second dielectric material which has been partially or completely etched away is no longer completely filled with the third dielectric material, so that an enclosed cavity arises, it is possible, in an extremely advantageous manner, to produce an excellent thermal insulation of the sublithographic contact structure on account of the cavity structure. In this way, the power loss of the memory cell can be significantly reduced and the maximum current for switching and erasing the memory cell can be lowered in a desired manner.
According to the invention, it may furthermore be advantageous if the trench structure has at least one minimum dimension that can be achieved photolithographically in at least one direction.
In accordance with a further embodiment, the invention provides a method for fabricating sublithographic contact structures in memory cells in a semiconductor component, in which firstly provision is made of a front-end-of-line (FEOL) finished processed semiconductor wafer with at least two electrical connecting contacts each connected to an active structure on one of its two opposite surfaces. An insulator layer made of a dielectric material is thereupon deposited on the semiconductor wafer at least partially over the connecting contacts, followed by formation of an etching mask on the insulator layer and etching of the dielectric as far as the first connecting contacts for the purpose of forming a first passage hole. A layer made of an electrically conductive material is then deposited and partially etched back in order to form a first contact electrode. Furthermore, a layer made of a resistance change material is deposited and partially etched back in the first passage hole. Next, a layer made of an electrically conductive material is deposited and partially etched back in the first passage hole for the purpose of forming a second contact electrode. A layer made of a spacer material is then deposited, which layer is intended to serve as an etching mask and may accordingly comprise SiN, by way of example, and is subsequently etched back anisotropically in the passage hole until the resistance change material is uncovered, spacer layer material remaining on the walls of the passage hole, and first spacers being formed which have a sublithographic dimension in at least one direction parallel to the wafer surface. Afterward, the second contact electrode, the resistance change material zone and the first contact electrode (stack comprising the two contact electrodes and the resistance change material) are etched as far as the connecting contacts, the spacer layer material being used as an etching mask.
Embodiments of the method according to the invention advantageously makes it possible to simultaneously form a plurality of sublithographic contact structures by virtue of the spacers with a sublithographic distance in a direction parallel to the wafer surface serving as an etching mask and the layer sequence below the spacer layer material producing the sublithographic contact structure. In this case, it may be advantageous if the first passage hole has at least one minimum dimension that can be achieved photolithographically in at least one direction.
According to the invention, the expression “sublithographic dimension” as is used here means a linear dimension which is smaller than the dimension that can be achieved with the optical (UV)-lithographic methods, which at the present time is approximately 50 nm. However, this expression is intended generally to encompass all linear dimensions which are smaller than the achievable minimum feature size (usually abbreviated to “F”) which can be fabricated by means of the technology used.
Resistance change material in the sense of the present invention is to be understood to be any material which is suitable for assuming at least two states having mutually different resistance values in response to selected (determinable) energy pulses, for example electrical heating pulses. The at least two states having a different electrical resistance can in this case be assigned to different structural phase states, such as an amorphous phase state or a crystalline phase state, so that switching between the states having a different electrical resistance is accompanied by a change in the phase state. In principle, however, it is also possible that the at least two states having a different electrical resistance may be different within a single phase state. Typical materials which are suitable and preferred as resistance change material for use in the method according to the invention are phase change materials, such as, in particular, chalcogenide alloys.
The first contact electrode and/or the second contact electrode of the memory cell may generally be produced from a suitable electrode material known to the person skilled in the art, which electrode material is for example W, TiN, Ta, TaN, TiW, TiSiN, TaSiN, TiON and TiAIN. The insulator layer is advantageously produced from an insulating dielectric material, for example SiO2, SiN or a so-called low-K material (material having a low dielectric constant).
Firstly, the sequence of
A first insulator layer 6 made of a first insulating dielectric material, for example SiO2, is firstly deposited on the surface of a semiconductor wafer (not specifically illustrated) at least over a connecting contact 5 connected to an active structure of the semiconductor wafer. An etching stop layer 7 made of SiN, for example, is then deposited on the first insulator layer 6 (
The anisotropic etching method used in the method according to the invention will now be described schematically with reference to the sequence of
Reference shall now be made to the sequence of
In the second embodiment of the method according to the invention, firstly a first insulator layer 6 made of a first insulating dielectric material, for example SiO2, is deposited on the surface of a semiconductor wafer (not specifically illustrated) at least over a connecting contact 5 connected to an active structure of the semiconductor wafer. An etching stop layer 7 made of SiN, by way of example, is then deposited on the first insulator layer 6, and is patterned in a known manner for the purpose of forming an etching mask 42. A first passage hole 21 having a form that is for example rectangular or a form that is for example round in plan view is thereupon etched in the first insulator layer 6 over the connecting contact 5 (
Reference will now be made to
In this embodiment, after depositing the layer made of an electrically conductive material and partially etching back this layer in the second passage hole 23 for the purpose of forming the first contact electrode 13 and after depositing the resistance change material at least over the second passage hole 23 (see
Reference will now be made to the sequence of
Reference shall now be made to the sequence of
Accordingly, provision is firstly made of a front-end-of-line (FEOL) finished processed semiconductor wafer (not specifically illustrated) with at least two electrical connecting contacts 30, 31 each connected to an active structure on one of its two opposite surfaces. An insulator layer 32 made of a dielectric material is thereupon deposited on the semiconductor wafer at least partially over the connecting contacts 30, 31, followed by the deposition of an etching stop layer 33 (
Merely for the sake of completeness, it should be mentioned that after the fabrication of the sublithographic contact structure in accordance with the methods of the invention, it is possible to carry out further processes of a back-end-of-line processing for producing further structures, such as insulator layers and metal wiring planes.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2005 001 902.1 | Jan 2005 | DE | national |
