The present invention relates to a semiconductor structure including a conductive line in a redistribution layer (RDL). Several protrusions are disposed over at least a portion of the conductive line and are configured to interface with a connector disposed over the conductive line or a passivation surrounding the conductive line.
Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming increasingly smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, wafer level chip scale packaging (WLCSP) is widely used for manufacturing. Numerous manufacturing steps are implemented within such small semiconductor devices.
However, the manufacturing of semiconductor devices in a miniaturized scale is becoming more complicated. An increase in the complexity of manufacturing semiconductor devices may cause deficiencies, such as poor electrical interconnection, development of cracks or delamination of components. As such, there are many challenges for modifying the structure and manufacturing of semiconductor devices.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.
One aspect of the present disclosure provides a semiconductor structure comprising a substrate including a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; and a redistribution layer (RDL) disposed over the first passivation and the pad, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line, wherein the conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, the land portion includes a plurality of first protrusions protruded away from the first passivation.
In some embodiments, the plurality of first protrusions are exposed from the second passivation.
In some embodiments, the semiconductor structure further includes a conductive member disposed between the substrate and the land portion of the conductive line.
In some embodiments, the land portion includes a plurality of second protrusions protruded towards the substrate and surrounded by the first passivation.
In some embodiments, the plurality of first protrusions are disposed over the plurality of second protrusions respectively.
In some embodiments, the plurality of first protrusions are vertically aligned with the plurality of second protrusions respectively.
In some embodiments, the plurality of first protrusions are interposed between the plurality of second protrusions respectively.
In some embodiments, the semiconductor structure further includes a connector disposed over the land portion.
In some embodiments, the connector is interfaced with the plurality of first protrusions.
In some embodiments, the plurality of first protrusions are protruded into the connector.
In some embodiments, the plurality of first protrusions are surrounded by the second passivation.
Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure which includes providing a substrate; disposing a pad over the substrate; disposing a first passivation over the substrate to partially cover the pad; disposing a conductive material over the first passivation and the pad to form a conductive line electrically connected to the pad; disposing a second passivation over the first passivation to partially cover the conductive line; and forming a plurality of first protrusions over the conductive line exposed from the second passivation.
In some embodiments, the plurality of first protrusions are formed by etching, laser ablation, drilling or electroplating.
In some embodiments, the method further includes disposing a patterned mask including a plurality of openings over the conductive line; disposing the conductive material within the plurality of openings to form the plurality of first protrusions; and removing the patterned mask.
In some embodiments, the method further includes disposing a patterned mask including a plurality of openings over the first passivation; removing portions of the first passivation exposed from the patterned mask to form a plurality of recesses over the first passivation; removing the patterned mask; and disposing the conductive material within the plurality of recesses to form a plurality of second protrusions protruded from the conductive line towards the substrate.
In some embodiments, the method further includes disposing a connector over the conductive line exposed from the second passivation and surrounding the plurality of first protrusions.
In some embodiments, the conductive material is disposed by electroplating or sputtering.
In some embodiments, the method further includes disposing a conductive member over the substrate.
Another aspect of the present disclosure provides a semiconductor structure comprising a substrate including a conductive via; a first passivation disposed over the substrate and exposing a portion of the conductive via; a conductive line disposed over the first passivation and electrically connected to the conductive via; and a second passivation disposed over the conductive line and exposing a portion of the conductive line, wherein the portion of the conductive line exposed from the second passivation includes a plurality of first protrusions protruded away from the first passivation.
In some embodiments, the conductive line includes a plurality of second protrusions protruded towards the substrate and surrounded by the first passivation.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures.
The following description of the disclosure accompanies drawings, which are incorporated in and constitute a part of this specification, and illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
References to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. Indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.
The present disclosure is directed to a semiconductor structure including a conductive line in a redistribution layer (RDL). At least a portion of the conductive line comprises several protrusions protruded from the conductive line for improving an adhesion between the conductive line and other components of the semiconductor structure (for example, a connector, a passivation or the like) or relieving a stress over the semiconductor structure. In order to make the present disclosure completely comprehensible, detailed steps and structures are provided in the following description. Obviously, implementation of the present disclosure does not limit special details known by persons skilled in the art. In addition, known structures and steps are not described in detail, so as not to limit the present disclosure unnecessarily. Preferred embodiments of the present disclosure will be described below in detail. However, in addition to the detailed description, the present disclosure may also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, and is defined by the claims.
A semiconductor structure includes several components stacking over and interfaced with each other. For example, a connector (such as a bump, a pillar, a post or the like) is disposed over and coupled with a portion of a conductive line, or the conductive line is disposed over a passivation. Since components include different kinds of materials, an adhesion between components may not be sufficient. Therefore, delamination of components or poor electrical connection between components may occur. Furthermore, upon disposing the connector over the conductive line, a stress or a force is acted over the conductive line and may cause damage to the connector and the conductive line as well as components under the conductive line. As such, cracks may be developed in the connector or the conductive line. The cracks may even propagate into the components under the conductive line.
In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a conductive line in a redistribution layer (RDL). The conductive line is surrounded by a passivation. The conductive line includes a land portion for receiving a connector. The land portion includes several protrusions protruded from the conductive line. The protrusions are configured to improve an adhesion between the conductive line and the connector or between the conductive line and the passivation. The protrusions are also configured to relieve a stress over the conductive line, internal to the semiconductor structure or developed during manufacturing. As such, delamination of components of the semiconductor structure and cracks developing in the semiconductor structure can be minimized or prevented. Thus, the reliability of the semiconductor structure can be improved.
In some embodiments, the substrate 101 is fabricated with a predetermined functional circuit thereon. In some embodiments, the substrate 101 includes several conductive traces and several electrical components, such as transistors and diodes, connected by the conductive traces. In some embodiments, the substrate 101 is a semiconductive substrate. In some embodiments, the substrate 101 is a wafer. In some embodiments, the substrate 101 includes semiconductive material such as silicon, germanium, gallium, arsenic, and combinations thereof. In some embodiments, the substrate 101 is a silicon substrate. In some embodiments, the substrate 101 is in a quadrilateral, rectangular, square, polygonal or any other suitable shapes.
In some embodiments, the substrate 101 includes a first surface 101a and a second surface 101b opposite to the first surface 101b. In some embodiments, the first surface 101a is a front side or an active side where the circuits or electrical components are disposed thereon. In some embodiments, the second surface 101b is a back side or an inactive side.
In some embodiments, the pad 102 is disposed over the substrate 101. In some embodiments, the pad 102 is disposed over or within the first surface 101a of the substrate 101. In some embodiments, the pad 102 is electrically connected to a circuitry or an electrical component in the substrate 101. In some embodiments, the pad 102 is electrically connected with a circuitry external to the substrate 101 so that the circuitry in the substrate 101 can electrically connect to the circuitry external to the substrate 101 through the pad 102. In some embodiments, the pad 102 is configured to receive a conductive structure. In some embodiments, the pad 102 is a die pad or a bond pad. In some embodiments, the pad 102 includes gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.
In some embodiments, the passivation 104 is disposed over the substrate 101 and a periphery of the pad 102. In some embodiments, the passivation 104 partially covers the pad 102; as such, a portion 102a of the pad 102 is exposed from the passivation 104. In some embodiments, the passivation 104 surrounds the pad 102. In some embodiments, the passivation 104 is configured to provide an electrical insulation and a moisture protection for the substrate 101 so that the substrate 101 is isolated from an ambient environment.
In some embodiments, one or more conductive members 103 are disposed over the substrate 101. In some embodiments, the conductive members 103 are disposed over the first surface 101a of the substrate 101. In some embodiments, the conductive members 103 are electrically connected to the circuitry or electrical components in the substrate 101. In some embodiments, the conductive members 103 are extended over the substrate 101. In some embodiments, the conductive member 103 is adjacent to the pad 102. In some embodiments, the conductive members 103 are adjacent to each other. In some embodiments, the conductive members 103 are arranged parallel to each other. In some embodiments, the conductive members 103 are spaced from each other at a consistent distance (pitch).
In some embodiments, the conductive member 103 is a conductive trace, metallic line, conductive pad, conductive pillar, conductive layer or the like. In some embodiments, the conductive member 103 includes copper, gold, silver, nickel, solder, tin, lead, tungsten, aluminum, titanium, palladium and/or alloys thereof.
In some embodiments, the first passivation 104 is disposed over the substrate 101. In some embodiments, the first passivation 104 is disposed over the first surface 101a of the substrate 101. In some embodiments, the first passivation 104 covers the conductive members 103 and partially covers the pad 102. In some embodiments, a portion of the pad 102 is exposed from the first passivation 104. In some embodiments, the first passivation 104 includes a first hole 104a disposed over the pad 102 and exposing the portion of the pad 102. In some embodiments, the portion of the pad 102 is configured to receive a conductive structure or electrically connect to a circuitry external to the substrate 101.
In some embodiments, the first passivation 104 includes a single layer of dielectric material or several layers of dielectric material stacking over each other. In some embodiments, the first passivation 104 is formed with dielectric materials, such as silicon oxide, silicon oxynitride, silicon nitride, polymer, polyimide, polybenzoxazole (PBO), polyimide-iso-indroquinazalinedione (PIQ) or the like.
In some embodiments, the RDL 105 is disposed over the first passivation 104. In some embodiments, the RDL 105 includes a conductive line 105a extending over the first passivation 104 and a second passivation 105b partially covering the conductive line 105a. In some embodiments, the RDL 105 re-routes a path from the pad 102 so as to redistribute I/O terminals of the substrate 101.
In some embodiments, the conductive line 105a is disposed over or conformal to the first passivation 104. In some embodiments, the conductive line 105a electrically connects to the pad 102 or the substrate 101. In some embodiments, the conductive line 105a includes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.
In some embodiments, the conductive line 105a includes a via portion 105c coupled with the pad 102 and a land portion 105d disposed over at least one of the conductive members 103. In some embodiments, the via portion 105c is disposed over the pad 102. In some embodiments, the via portion 105c is extended within the first passivation 104 towards the pad 102. In some embodiments, the via portion 105c extends through a portion of the first passivation 104 towards the pad 102. In some embodiments, the via portion 105c is disposed over and electrically connected to the pad 102. In some embodiments, the via portion 105c is coupled with the portion of the pad 102 exposed from the first passivation 104.
In some embodiments, the land portion 105d is extended over the first passivation 104. In some embodiments, the land portion 105d is electrically connected to the pad 102 through the via portion 105c. In some embodiments, the land portion 105d is configured to receive a conductive structure or electrically connect to a circuitry external to the substrate 101 through the via portion 105c or the pad 102.
In some embodiments, the second passivation 105b is disposed over the first passivation 104. In some embodiments, the conductive line 105a is surrounded by the second passivation 105b. In some embodiments, the second passivation 105b exposes a portion of the conductive line 105a. In some embodiments, the via portion 105c is disposed within or covered by the second passivation 105b, and the land portion 105d is exposed from the second passivation 105b. In some embodiments, the second passivation 105b includes a second hole 105f disposed over the land portion 105d and exposing at least a portion of the land portion 105d
In some embodiments, the second passivation 105b includes a single layer of dielectric material or several layers of dielectric material stacking over each other. In some embodiments, the second passivation 105b is formed with dielectric materials, such as silicon oxide, silicon oxynitride, silicon nitride, polymer, polyimide, polybenzoxazole (PBO), polyimide-iso-indroquinazalinedione (PIQ) or the like.
In some embodiments, the land portion 105d includes several first protrusions 105e protruded from the land portion 105d and away from the first passivation 104. In some embodiments, the first protrusions 105e stand upright over the land portion 105d. In some embodiments, the first protrusions 105e are extended orthogonal to the land portion 105d. In some embodiments, the first protrusions 105e are surrounded by the second passivation 105b. In some embodiments, the first protrusions 105e are exposed from the second passivation 105b.
In some embodiments, the first protrusion 105e is disposed above or aligned with one of the conductive members 103. In some embodiments, the first protrusion 105e is not aligned with any one of the conductive members 103. In some embodiments, the first protrusion 105e is disposed over and between two adjacent conductive members 103. In some embodiments, the first protrusions 105e are spaced from each other at a consistent or inconsistent distance. In some embodiments, the first protrusions 105e are at equal height to each other or at different heights from each other.
In some embodiments, a vertical cross section (from a view as shown in
In some embodiments, the connector 106 is disposed over the land portion 105d. In some embodiments, the connector 106 is interfaced with the first protrusions 105e. In some embodiments, the first protrusions 105e are protruded into the connector 106. In some embodiments, the first protrusions 105e are surrounded by the connector 106. In some embodiments, the connector 106 is electrically connected to the land portion 105d. In some embodiments, the connector 106 is protruded from the land portion 105d or the second passivation 105b. In some embodiments, the connector 106 is at least partially surrounded by the second passivation 105b or is at least partially disposed within the second hole 105f. In some embodiments, the connector 106 is configured to bond with a conductive structure, a chip or a package.
In some embodiments, the connector 106 is in a cylindrical, spherical or hemispherical shape. In some embodiments, the connector 106 is a solder joint, a solder bump, a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, a microbump or the like. In some embodiments, the connector 106 is a conductive pillar or post.
In some embodiments, the land portion 105d includes the first protrusions 105e protruded from the land portion 105d. The first protrusions 105e are configured to improve an adhesion between the land portion 105d and the connector 106, or relieve a stress over the conductive line 105a when the connector 106 is disposed over the land portion 105d. Therefore, delamination of the conductive line 105a or development of cracks within the connector 106, the conductive line 105a, the first passivation 104 or the second passivation 105b can be minimized or prevented.
In some embodiments, the first passivation 104 includes several recesses 104b indented into the first passivation 104 towards the substrate 101. In some embodiments, the recesses 104b are disposed over at least one of the conductive members 103.
In some embodiments, the land portion 105d includes the first protrusions 105e protruded towards the connector 106 and the second protrusions 105g protruded towards the first passivation 104. In some embodiments, the first protrusions 105e are disposed over the second protrusions 105g. In some embodiments, the land portion 105d is in a ripple or wavy shape. In some embodiments, the second protrusions 105g are protruded into the first passivation 104 from the land portion 105d towards the substrate 101 and are surrounded by the first passivation 104. In some embodiments, the second protrusions 105g are disposed within the recesses 104b, respectively. In some embodiments, the second protrusions 105g are disposed over at least one of the conductive members 103. In some embodiments, the second protrusions 105g are extended orthogonal to the land portion 105d.
In some embodiments, a vertical cross section (from a view as shown in
In some embodiments as shown in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, the second protrusion 105g is disposed above one of the conductive members 103. In some embodiments, a distance D between the second protrusion 105g and the conductive member 103 is substantially greater than zero. In some embodiments, the distance D is substantially greater than 1 μm.
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, the conductive via 107 is extended through the substrate 101. In some embodiments, the first passivation 104 is disposed over the substrate 101. In some embodiments, a portion 107a of the conductive via 107 is exposed from the first passivation 104. In some embodiments, the RDL 105 is disposed over the substrate 101. In some embodiments, the RDL 105 is disposed over the second surface 101b of the substrate 101. In some embodiments, a conductive line 105a of the RDL 105 is disposed over the first passivation 104 and electrically connected to the conductive via 107. In some embodiments, a second passivation 105b of the RDL 105 is disposed over the conductive line 105a and exposing a portion of the conductive line 105a. In some embodiments, the portion of the conductive line 105a exposed from the second passivation 105b includes several first protrusions 105e protruded away from the first passivation 104. In some embodiments, the conductive line 105a includes several second protrusions protruded towards the substrate 101 and surrounded by the first passivation 104.
In the present disclosure, a method of manufacturing a semiconductor structure (100 or 200) is also disclosed. In some embodiments, the semiconductor structure (100 or 200) can be formed by a method 300 of
In step 301, a substrate 101 is provided or received as shown in
In step 302, a pad 102 is disposed over the substrate 101 as shown in
In some embodiments, several conductive members 103 are disposed over the substrate 101 as shown in
In step 303, a first passivation 104 is disposed over the substrate 101 as shown in
In step 304, a first patterned mask 401 is disposed over the first passivation 104 as show in
In step 305, several portions of the first passivation 104 exposed from the first patterned mask 401 are removed to form several recesses 104b over the first passivation 104 as shown in
In step 306, the first patterned mask 401 is removed as shown in
In step 307, a conductive material is disposed within the recesses 104b to form several second protrusions 105g as shown in
In step 308, a portion of the first passivation 104 disposed over the pad 102 is removed to form a first hole 104a and expose a portion of the pad 102 as shown in
In step 309, a conductive material is disposed over the first passivation 104 and the pad 102 to form a conductive line 105a as shown in
In step 310, a second passivation 105b is disposed over the first passivation 104 to partially cover the conductive line 105a as shown in
In step 311, several first protrusions 105e are formed over the conductive line 105 exposed from the second passivation 105b as shown in
In some embodiments as shown in
In some embodiments, the first protrusions 105e are formed before the disposing of the second passivation 105b. In some embodiments, the step 311 is performed before the step 310. In some embodiments as shown in
In some embodiments, the second passivation 105b is disposed over the conductive line 105 after the formation of the first protrusions 105e as shown in
In step 312, a connector 106 is disposed over the conductive line 105 exposed from the second passivation 105b as shown in
One aspect of the present disclosure provides a semiconductor structure including a substrate including a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a conductive member disposed over the first surface; a first passivation disposed over the first surface, covering the conductive member and partially covering the pad; and a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line, wherein the conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion disposed over the conductive member, the land portion includes a plurality of first protrusions protruded away from the first passivation
Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure which includes providing a substrate; disposing a pad over the substrate; disposing a conductive member over the substrate; disposing a first passivation over the substrate to cover the conductive member and partially cover the pad; disposing a conductive material over the first passivation and the pad to form a conductive line electrically connected to the pad; disposing a second passivation over the first passivation to partially cover the conductive line; and forming a plurality of first protrusions over the conductive line exposed from the second passivation.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This patent application is a divisional application of and claims priority to U.S. patent application Ser. No. 15/229,882, filed on Aug. 5, 2016, which is incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
4042954 | Harris | Aug 1977 | A |
4051508 | Sato et al. | Sep 1977 | A |
5134460 | Brady et al. | Jul 1992 | A |
5404045 | Mizushima | Apr 1995 | A |
5559366 | Fogal | Sep 1996 | A |
5592736 | Akram | Jan 1997 | A |
5656858 | Kondo et al. | Aug 1997 | A |
5686762 | Langley | Nov 1997 | A |
5986346 | Katoh | Nov 1999 | A |
6103552 | Lin | Aug 2000 | A |
6291897 | Wark | Sep 2001 | B1 |
6297563 | Yamaha | Oct 2001 | B1 |
6307160 | Mei et al. | Oct 2001 | B1 |
6335561 | Imoto | Jan 2002 | B2 |
6400021 | Cho | Jun 2002 | B1 |
6415974 | Jao | Jul 2002 | B2 |
6441487 | Elenius | Aug 2002 | B2 |
6468892 | Baker et al. | Oct 2002 | B1 |
6489229 | Sheridan et al. | Dec 2002 | B1 |
6552433 | Chou et al. | Apr 2003 | B1 |
6566762 | Baker et al. | May 2003 | B1 |
6596628 | Magara | Jul 2003 | B2 |
6621164 | Hwang | Sep 2003 | B2 |
6670222 | Brodsky | Dec 2003 | B1 |
6717263 | Sawai | Apr 2004 | B2 |
6841872 | Ha | Jan 2005 | B1 |
6864578 | Angell | Mar 2005 | B2 |
6875682 | Liu et al. | Apr 2005 | B1 |
7015590 | Jeong | Mar 2006 | B2 |
7129111 | Tsai | Oct 2006 | B2 |
7196000 | Lee | Mar 2007 | B2 |
7214604 | Kim | May 2007 | B2 |
7233067 | Takano | Jun 2007 | B2 |
7271497 | Joshi et al. | Sep 2007 | B2 |
7300864 | Ma | Nov 2007 | B2 |
7358608 | Ohsumi | Apr 2008 | B2 |
7682959 | Lin et al. | Mar 2010 | B2 |
7863740 | Ke | Jan 2011 | B2 |
7888257 | Antol | Feb 2011 | B2 |
7932171 | Joshi et al. | Apr 2011 | B2 |
7977789 | Park | Jul 2011 | B2 |
8097491 | Hsu | Jan 2012 | B1 |
8120176 | Shin | Feb 2012 | B2 |
8253248 | Ke et al. | Aug 2012 | B2 |
8304904 | Lin et al. | Nov 2012 | B2 |
8354750 | Wang et al. | Jan 2013 | B2 |
8434041 | Chen et al. | Apr 2013 | B2 |
8476764 | Huang et al. | Jul 2013 | B2 |
8637986 | Masuda | Jan 2014 | B2 |
8642462 | Sterrett et al. | Feb 2014 | B2 |
8643150 | Xu et al. | Feb 2014 | B1 |
8901736 | Shen et al. | Dec 2014 | B2 |
8906798 | Wang et al. | Dec 2014 | B2 |
8912668 | Chen | Dec 2014 | B2 |
9013038 | Chen | Apr 2015 | B2 |
9184144 | Bao | Nov 2015 | B2 |
9245833 | Chen | Jan 2016 | B2 |
9362243 | Yu | Jun 2016 | B2 |
9379075 | Chen | Jun 2016 | B2 |
9548282 | Lin | Jan 2017 | B2 |
9673158 | Wang | Jun 2017 | B2 |
9716071 | Ryu | Jul 2017 | B2 |
9761549 | Lin | Sep 2017 | B2 |
9793243 | Lu | Oct 2017 | B2 |
9953954 | Ji | Apr 2018 | B2 |
20010011761 | Imoto | Aug 2001 | A1 |
20020137304 | Yih | Sep 2002 | A1 |
20030222353 | Yamada | Dec 2003 | A1 |
20040178481 | Joshi | Sep 2004 | A1 |
20040197979 | Jeong | Oct 2004 | A1 |
20040238955 | Homma et al. | Dec 2004 | A1 |
20050017375 | Ko et al. | Jan 2005 | A1 |
20050173806 | Matsubara | Aug 2005 | A1 |
20050208751 | Oh | Sep 2005 | A1 |
20060043156 | Debelius | Mar 2006 | A1 |
20060055032 | Chang | Mar 2006 | A1 |
20070015312 | Tsai | Jan 2007 | A1 |
20070020906 | Chiu | Jan 2007 | A1 |
20070108619 | Hsu | May 2007 | A1 |
20070207608 | Wang | Sep 2007 | A1 |
20070290343 | Harada | Dec 2007 | A1 |
20090079094 | Lin | Mar 2009 | A1 |
20090127695 | Kim | May 2009 | A1 |
20090160052 | Yang et al. | Jun 2009 | A1 |
20090166859 | Yuan | Jul 2009 | A1 |
20090174052 | Sogawa et al. | Jul 2009 | A1 |
20090283903 | Park | Nov 2009 | A1 |
20100013082 | Lin | Jan 2010 | A1 |
20100270672 | Shiraki | Oct 2010 | A1 |
20110063815 | Lu | Mar 2011 | A1 |
20110186987 | Wang et al. | Aug 2011 | A1 |
20110291262 | Shen et al. | Dec 2011 | A1 |
20120205812 | Sutardja | Aug 2012 | A1 |
20130015575 | Lin et al. | Jan 2013 | A1 |
20130020711 | Bao | Jan 2013 | A1 |
20130043583 | Wu | Feb 2013 | A1 |
20130069235 | Huang | Mar 2013 | A1 |
20130109169 | Wang et al. | May 2013 | A1 |
20130140691 | Bao | Jun 2013 | A1 |
20130187269 | Lin | Jul 2013 | A1 |
20130228897 | Chen | Sep 2013 | A1 |
20130277833 | Baek et al. | Oct 2013 | A1 |
20130277838 | Yu | Oct 2013 | A1 |
20140061898 | Chen | Mar 2014 | A1 |
20140061900 | Park | Mar 2014 | A1 |
20140077356 | Chen | Mar 2014 | A1 |
20140124929 | Lin | May 2014 | A1 |
20140203430 | Sterrett et al. | Jul 2014 | A1 |
20140252610 | Chen | Sep 2014 | A1 |
20140312512 | Choi | Oct 2014 | A1 |
20150021758 | Tsai | Jan 2015 | A1 |
20150037936 | Shen et al. | Feb 2015 | A1 |
20150091191 | Chen | Apr 2015 | A1 |
20150130084 | Liao | May 2015 | A1 |
20150214170 | Chen | Jul 2015 | A1 |
20150228593 | Lee | Aug 2015 | A1 |
20150243613 | Chen | Aug 2015 | A1 |
20150340329 | Yu | Nov 2015 | A1 |
20160079148 | Chang | Mar 2016 | A1 |
20160276178 | Han | Sep 2016 | A1 |
20160284639 | Chen | Sep 2016 | A1 |
20160351518 | Chen | Dec 2016 | A1 |
20160365326 | Cho | Dec 2016 | A1 |
20170025371 | Chen | Jan 2017 | A1 |
20170084558 | Seo | Mar 2017 | A1 |
20180082963 | Lin | Mar 2018 | A1 |
20180114763 | Lin | Apr 2018 | A1 |
20180114764 | Lin | Apr 2018 | A1 |
Number | Date | Country |
---|---|---|
1759480 | Apr 2006 | CN |
100565857 | Dec 2009 | CN |
102263067 | Nov 2011 | CN |
102339770 | Dec 2012 | CN |
2023384 | Feb 2009 | EP |
2006287048 | Oct 2006 | JP |
200536030 | Nov 2005 | TW |
201332073 | Aug 2013 | TW |
201539656 | Oct 2015 | TW |
Number | Date | Country | |
---|---|---|---|
20180114763 A1 | Apr 2018 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 15229882 | Aug 2016 | US |
Child | 15851186 | US |