Patent Application
20110147910
The present disclosure is related to a method and apparatus for packaging a stacked microelectronic die in a thin, small-outline package.
Microelectronic devices are consistently becoming more powerful and smaller because there is intense market pressure to produce reliable, high-performance electronic products in small sizes (e.g., portable computers, cell phones, smart phones, music/video players, etc.). As such electronic products shrink, the available space for microelectronic devices within the electronic products also decreases. Standards for sizing the microelectronic devices provide useful guidelines to ensure interoperability between manufacturers and to ease communication between vendors and manufacturers. One standard governing semiconductors and other solid-state equipment is set forth by the Joint Electron Device Engineering Council (“JEDEC”). The JEDEC standard relates to the size, shape, and other features of microelectronic devices and packaging. Although the JEDEC standard provides the benefits of interoperability, a consistent challenge is to maximize the capabilities of the microelectronic device within the package sizes defined by the standard.
Standards, such as the JEDEC standards, govern the size and shape of the encapsulant 112 and the package 100. The standards regulate a joint area 114 between the lead frame 110 and the encapsulant 112, and the thicknesses of critical dimensions 116, 117, and 118 of the encapsulant 112 at various positions around the dies 102 and 104. The downset 113 limits the size of the dies 102 and 104 within the parameters of a given standard package size because conventional downsets 113 cause the lower die 104 to be closer to a lower portion or sidewall of the encapsulant 112. The dies 102 and 104, more specifically, must be small enough to maintain a minimum of one or more of the critical dimensions 116, 117 and/or 118 of the encapsulant 112. Limiting the lateral dimensions of the dies 102 and 104 necessarily limits the capabilities of the device because fewer components can fit in the package 100 and still meet the standards.
Specific details of several embodiments of the new technology are described below with reference to microelectronic device configurations and associated methods of manufacturing. Typical microelectronic device packages include microelectronic circuitry or components (e.g., integrated circuitry), micro-fluidic devices, and other components manufactured on microelectronic substrates. Micromachines and micromechanical devices are included within this definition because they are manufactured using technology similar to that used in the fabrication of integrated circuits. The term “microfeature substrate” or “die” is used throughout to include semiconductor substrates and other types of substrates upon which and/or in which semiconductor devices or other types of microelectronic devices or micromechanical devices and other features are fabricated. Suitable materials for dies can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), nonconductive pieces (e.g., various ceramic substrates), or conductive pieces. Microfeature dies can also include one or more layers (e.g., conductive, semiconductive, and/or dielectric) that are situated upon and/or within one another. These layers can include or form a wide variety of electrical components, mechanical components, and/or systems of such components (e.g., integrated circuits, memory devices, processors, imagers, light emitting diodes, micromechanical systems, etc.). The term “surface” can encompass planar and nonplanar surfaces of a semiconductor substrate with or without patterned and nonpatterned features. A person skilled in the relevant art will also understand that the new technology may have additional embodiments and that the new technology may be practiced without several of the details of the embodiments described below with references to
In several embodiments of the new technology, a microelectronic device includes a first die comprising an integrated circuit, a first active face, and an inactive surface opposite the first active face. The first active face includes a plurality of first terminals electrically connected to the integrated circuit of the first die. The microelectronic device also includes a second die comprising an integrated circuit and second active face. The second active face includes a plurality of second terminals electrically connected to the integrated circuit of the second die. The first die and the second die are positioned with the first active face and the second active face facing one another. The microelectronic device also includes an encapsulant molded around the first die, the second die, and a lead frame. The lead frame has a proximal portion positioned between the first active face and the second active face and electrically connected to at least one of the first die and the second die. The lead frame also includes a transition portion protruding from the encapsulant and sloping toward the first die, and a distal portion configured to connect with a host device.
In still other embodiments, a method for packaging a microelectronic device in accordance with the new technology includes mounting a first die to a lead frame, and mounting a second die to at least one of the first die or the lead frame. The first die and the second die have active surfaces that face one another. The method further includes encapsulating the first die, the second die, and at least a portion of the lead frame, wherein the lead frame extends from between the first active surface and the second active surface and protrudes from the encapsulant.
The microelectronic device 200 can also have a lead frame 220 having a distal portion 222, a transition portion 224, and a proximal portion 226 relative to the first and second dies 202 and 204. The proximal portion 226 (or proximal end 226) of the lead frame 220 is positioned between the dies 202 and 204 and electrically connected to the first die 202 and/or the second die 204. An encapsulant 230 is molded or otherwise formed around the dies 202 and 204 and the proximal portion 226 of the lead frame 220. In some embodiments a section of the transition portion 224 is also positioned within the encapsulant 230. The proximal portion 226 interior to the encapsulant has no downset; rather, the lead frame 220 extends from between the dies 202 and 204 laterally outwardly and continues outside the encapsulant 230. In some embodiments, a section of the proximal portion 226 of the lead frame 220 extends from between the dies 202 and 204 in a medial plane 232 generally parallel to the planes defined by the active faces 206 and 208. The proximal portion 226 of the lead frame 220 can extend in the medial plane 232 almost until the exterior surface of the encapsulant. The transition portion 224 curves away from the medial plane 232 and continues beyond a distal plane 234 defined generally by a lower surface 236 of the encapsulant 230. As shown in
Several embodiments of the lead frame 220 can accordingly have a first surface 240 and a second surface 242, and each of the surfaces 240 and 242 can have one convex portion 244 and one concave portion 246. For the first surface 240, the convex portion 244 is nearer to the encapsulant 230 than the concave portion 246; for the second surface 242, the concave portion 246 is nearer to the encapsulant 230 than the convex portion 244. In some embodiments, the convex portion 244 and concave portion 246 have generally the same radius of curvature. In other embodiments, these portions can have compound curvatures along the length of the lead frame 220. As shown in
Several of the embodiments in accordance with the new technology provide a package structure that allows the dies of a microelectronic device to be bigger and therefore contain more components than conventional systems. As explained above, conventional lead frames with downsets limit the lateral dimension of the dies because the space occupied by the downset reduces the space within a given package size for the dies; this in turn limits the capabilities of the microelectronic device because the smaller dies have fewer components. Several embodiments of the configuration shown in
Selected embodiments of the microelectronic device 300 can include a lead frame 312 attached to the active surface of one of the first die 302 or the second die 304. The lead frame 312 comprises several electrically conductive lines between terminals 316 on the dies 302 and 304 and a host component. In some embodiments, the lead frame 312 can be positioned adjacent to and/or connected to the first die 302; in other embodiments the lead frame 312 can be positioned adjacent to and/or connected to the second die 304. Or, in still other embodiments, the lead frame 312 can be attached to both the first die 302 and the second die 304. The lead frame 312 can be connected to the dies 302 or 304 electrically, mechanically, or both mechanically and electrically.
When the lead frame 312 is attached to the second die 304, the microelectronic device 300 can include wirebonds 314 that extend from the lead frame 312 to corresponding terminals 316 on the second die 304. The lead frame 312 can have sufficient thickness to operate as desired without permitting the lead frame 312 or the wirebonds 314 to contact the first die 302. Also, the interconnecting elements 310 can be configured to space the dies 302 and 304 apart from each other by a sufficient distance to position the lead frame 312 and the wirebonds 314 between the first die 302 and the second die 304. The dies 302 and 304, the interconnecting elements 310, the lead frame 312, and the wirebonds 314 together provide many electrical paths between the dies 302 and 304 and an external host device. The device also has an encapsulant 320 molded or otherwise formed over the dies 302 and 304, the wirebonds 314, and at least a portion of the lead frame 312.
According to several embodiments, the microelectronic device 300 includes a lead frame 312 that does not have a downset. The lead frame 312 includes individual leads that have a proximal portion 321, a transition portion 322, and a distal portion 324 that are
In further embodiments, a microelectronic device includes a first die with a first active surface comprising a plurality of electric terminals, and a second die having a second active surface comprising a plurality of electric terminals. The first die and the second die are positioned face-to-face such that the first active surface faces the second active surface. The microelectronic device further includes an encapsulant surrounding the first die and the second die, and a lead frame protruding from the encapsulant. The lead frame is connected to at least one of the first die and the second die and has an interior portion within the encapsulant positioned between the first active surface and the second active surface. The interior portion has no downset.
In several other embodiments of the new technology, a microelectronic device comprises two dies that each have an active surface. The two dies are arranged such that the active surfaces face each other. The device also includes an encapsulant material that encases the two dies and a lead frame having leads with proximal portions positioned between the two dies and electrically connected to at least one of the dies. The lead frame has no downset such that the proximal portions of the leads extend laterally outwardly from between the two dies through the encapsulant material. In other embodiments, the new technology includes a microelectronic device comprising a first die having a first active surface and a second die having a second active surface. The first and second dies are positioned face-to-face such that the first and second active surfaces face one another. The device also includes an encapsulant surrounding the first and second dies, and a lead frame having leads with proximal portions connected to at least one of the first and second dies and distal portions extending from the encapsulant. The proximal portions of the leads are between the first and second active surfaces.
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Unless the word “or” is associated with an express clause indicating that the word should be limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list shall be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list.
Also, it will be appreciated that specific embodiments described above are for purposes of illustration and that various modifications may be made without deviating from the invention. Aspects of the disclosure described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments of the disclosure may have been described in the context of those embodiments, other embodiments may also exhibit such advantages, but not all embodiments need necessarily exhibit such advantages to fall within the scope of the disclosure. Accordingly, the present invention is not limited to the embodiments described above, which were provided for ease of understanding; rather, the invention includes any and all other embodiments defined by the claims.
