This invention relates generally to the field of semiconductor devices, and more particularly, to the field of processing of semiconductor devices using high-k dielectric films.
A reduction in the gate oxide thickness for CMOS (complementary metal oxide semioconductor) devices is necessary to improve the speed of the devices. However, when the thickness of the gate oxide is decreased, the leakage currents generally increases. Therefore, new materials are currently being investigated to replace the current gate oxide for CMOS devices. Materials that are under consideration include metal oxides, metal silicates, as well as metal silicon oxynitrides, collectively referred to as high-k (high dielectric constant) dielectrics. These materials, due to scaling issues, are required to be ultra-thin, on the order of 10's of angstroms.
Metal silicon oxynitrides are especially attractive for this purpose due to their increased dielectric constant over silicates, their reduction in phase separation over pure silicates as well as their amorphous nature. These materials provide excellent device performance and reliability. In particular, one such metal silicon oxynitride receiving widespread attenttion is HfSiON.
In a typical method of forming a high-k dielectric material over silicon, an interfacial layer of SiOx results after post-deposition anneal. This interfacial layer limits the scaling of the high-k material. One method that has been proposed to reduce the interfacial layer, has been to nitridize the silicon substrate prior to the high-k dielectric material deposition. The result of this nitridization has been to merely reduced the interfacial layer thickness and not remove it. It is clear that this approach cannot meet the scaling requirements for future generations of CMOS devices.
In yet another proposed method to integrate high-k dielectric materials while minimizing the interfacial layer, an oxide has been either deposited or grown over the silicon substrate and then etched back to a reduced thickness and followed by a high-k dielectric material deposition. Again, this approach limits the scalability of the overall high-k integration and only serves to minimize the interfacial layer thickness.
Therefore a need exists to successfully integrate the high-k materials while preserving the quality of the interface near the silicon substrate as well as maintaining scaling capabilities.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
Rather than attempt a removal of oxide over the silicon, incorporation of the oxide into the process is performed. In one aspect, a high quality oxide is deposited on a silicon substrate. The oxide then has a layer of metal nitride deposited over the high quality oxide and the resulting stack is annealed. The anneal serves to create a metal silicon oxynitride layer which has improved scalability and reliablity over conventional gate oxides. The full process is better understood by reference to the FIGs. and the following description.
Layer 14 can also be an oxynitride. If the layer 14 is an oxynitride, either thermal growth or deposition can be used. In a similar case to the layer 14 being an oxide, the oxynitride can either be thermally grown or deposited to a thickness of 50-60 Å or to 10 Å depending on the subsequent processing steps.
After the oxide or oxynitride layer 16 achieves a thickness of less than 15 Å, a layer 18 of metal oxide or metal nitride is deposited as shown in
The metal oxide or metal nitride layer 18 is then annealed as shown in
In the case where metal nitride layer 18 is over an oxide or oxynitride layer 16, an alternative anneal ambient can include argon or other inert gas. Additionally, the gas anneal temperature, in this case, need not be greater than 1000° C. in order to form the metal silicon oxynitride layer 22 in
The unreacted metal oxide or metal nitride layer 18 is then removed as shown in
An optional anneal 24 can then be used to improve the metal silicon oxynitride film quality as shown in
Further processing would then be used to build a final semiconductor device as shown in
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Certain materials were described and these may be varied. As further alternatives, hafnium oxide was described as the exemplary metal oxide but other high-k dielectrics may be used such as zirconium oxide or other metal oxides such as lanthanum aluminum oxynitride may also benefit from this process. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprise”, “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms “a” or “an”, as used herein, are defined as one or more than one.
Moreover, the terms “front”, “back”, “top”, “bottom”, “over”, “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.