Patent Grant
11978712
Electronics can be divided into a simple hierarchy consisting of devices such as integrated circuit (IC) chips, packages, printed circuit boards (PCB), and systems. The package is the interface between an IC chip and a PCB. IC dies are made from semiconductor materials such as silicon. Dies are then assembled into semiconductor packages such as quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), three dimensional integrated circuits (3DIC), wafer level packages (WLP), or package on package (PoP) devices, using wire bonding (WB), tape automated bonding (TAB), or flip chip (FC) bumping assembly techniques. The packaged die is then attached either directly to a PCB or to another substrate as the second level packaging.
3DIC technologies are known as vertical interconnect packaging technologies as they exploit the vertical dimension of the chip to reduce interconnect length and to achieve greater integration efficiency. The techniques for 3DIC package include wire-bonding, micro-bumps, through-vias, and more. A silicon interposer can be used to form a 3DIC package, where the interposer provides die-to-die interconnections for dies mounted on the interposer. For example, two dies may be bonded above each other by face-to-face or face-to-back stacking, with the lower die being coupled to the interposer by connectors such as micro-bumps. Alternatively, multiple dies may also be mounted in parallel above an interposer, and coupled to the interposer by connectors such as micro-bumps.
Semiconductor packages equipped with wireless data and communication systems comprise various RF (radio frequency) transmitting structures, which sometimes are built on chip or in-package. Electromagnetic RF waves or signals are conveyed through the packages or devices by conductive structures referred to as transmission lines. Transmission lines, as an example, may be used for interconnecting individual electrical elements together in a Monolithic Microwave Integrated Circuit (MMIC), and for interconnecting MMICs together within microwave Multi Chip Modules (MCMs).
In general, a transmission line includes at least two electric conductors or lines wherein one of the lines forms a ground (also referred to as “ground plane”) and the other forms a signal transmission line. The signal transmission line is variously arranged and combined with one or more ground planes or ground lines to form different types of conductive transmission lines such as microstrip, coplanar waveguide (CPW), grounded coplanar waveguide (GCPW) transmission lines to serve various RF signal applications. The signal transmission lines and ground conductors or planes are generally supported by some type of insulating substrate or material such as a dielectric.
As semiconductor technology continues to advance and chip package size shrinks, such as by employing 3DIC die stacking, the distance between metal layers in the conductive CMOS (complementary metal-oxide semiconductor) structure becomes smaller, leading to increasingly larger capacitance between the metal layers and reduced performance of RF devices. In addition, designing and fabricating transmission lines on-chip in a single chip or die becomes increasingly difficult with shrinking die packages in advanced semiconductor manufacturing technology nodes like the 20 nm process. Methods and apparatus are needed for designing and fabricating transmission lines with improved performance.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments of the present disclosure provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.
As will be illustrated in the following, methods and apparatus for forming a semiconductor device package with transmission lines using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. A signal transmission line may be formed using a micro-bump line above a device. A ground plane may be formed using a redistribution layer (RDL) within a device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at a bottom device and top device above and below the micro-bump lines to form parts of the ground planes. Transmission lines so formed have lower resistance, and save the areas occupied by the transmission lines.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, or connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “above” or “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,”—when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
As illustrated in
The RDL 480, the micro-bump line 470 separated from the RDL 480 by the insulator layer 371, and the UBM line 390 under the micro-bump line 470 form the transmission line 490, where the RDL 480 is the ground plane, and the micro-bump line 470 and the UBM line 390 form the signal transmission line. In some alternative embodiments, the UBM line 390 may not exist and the micro-bump line 470 alone is placed on the insulator layer 371 to act as the signal transmission line.
The device 301 may be an interposer comprising a substrate, with through vias formed within the substrate, and a plurality of contact pads, passivation layers, insulator layers, RDLs, and a UBM layer. Alternatively, the device 301 may be a part of a chip or an integrated circuit (IC) die, which may be a back or front side of a die. When the device 301 is a part of a die, the die 601 is placed on the IC device 301, which will be further coupled to an interposer by connectors such as micro-bumps to form a package such as a 3DIC package. In the case when the device 301 is a part of a die, it may be called as a bottom die, and the die 601 may be called a top die. When the device 301 is the back of a die, then the package 100 is formed by face-to-back stacking of the dies 301 and 601. When the device 301 is the front side of a die, then the package 100 is formed by face-to-face stacking of the dies 301 and 601. Alternatively, the device 301 may be a package substrate without through vias, any or all of the layers described above. These devices and any other suitable devices may alternatively be used and are fully intended to be included within the scope of the present embodiments.
The substrate 302 for the device 301 may be, e.g., a silicon substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate, used to provide support for the device 301. However, the substrate 302 may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide a suitable protection and/or interconnection functionality. These and any other suitable materials may alternatively be used for the substrate 302. There may be a plurality of active or passive components, such as transistors, capacitors, resistors, and the like, formed within the substrate 302, which are not shown in
A plurality of TVs 303 may be formed through the substrate 302. The TVs 303 may be formed by applying and developing a suitable photoresist, and then etching the substrate 302 to generate TV openings. The openings for the TVs 303 may be formed to extend into the substrate 302 to a depth at least greater than the eventual desired height. Accordingly, the depth may be between about 1 μm and about 700 μm below the surface on the substrate 302. The openings for the TVs 303 may have a diameter of between about 1 μm and about 100 μm. Then the openings for the TVs 303 may be filled by a barrier layer and a conductive material, using a process such as chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), sputtering or metal organic chemical vapor deposition (MOCVD). Excessive barrier layer and excessive conductive material outside of the openings for the TVs 303 may be removed through a grinding process such as chemical mechanical polishing (CMP). Afterwards, a thinning of the second side of the substrate 302 may be performed by a planarization process such as CMP or etching, in order to expose the openings for the TVs 303 and to form the TVs 303 from the conductive material that extends through the substrate 302. A dielectric layer 311 may be formed on the substrate 302. The dielectric layer 311 may be a representation of a plurality of sub-layers such as inter-metal dielectric layers with various metal layers embedded.
A plurality of contact pads 321 may be formed on the dielectric layer 311. Contact pads 321 may be made with aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other electrically conductive material. The deposition of contact pads 321 uses an electrolytic plating, sputtering, physical vapor deposition (PVD), or electroless plating process. The size, shape, and location of the contact pads 321 are only for illustration purposes and are not limiting. The plurality of contact pads 321 may be of the same size or of different sizes.
A passivation layer 341 may be formed over the substrate 302, the dielectric layer 311, and above the contact pads 321 for structural support and physical isolation. The passivation layer 341 may be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material. Openings of the passivation layer 341 may be made by removing a portion of the passivation layer 341 using a mask-defined photoresist etching process to expose the contact pads 321. The size, shape, and location of the openings made are only for illustration purposes and are not limiting.
An insulator layer 361, such as a polymer layer 361, may be formed over the passivation layer 341 and over the passivation layer opening to cover the contact pads 321. An opening of the insulator layer 361 may be formed to expose the contact pads 321. The openings of the insulator layer 361 may be made by removing a portion of the insulator layer 361 using a mask-defined photoresist etching process to expose the contact pads 321. The size, shape, and location of the opening made are only for illustration purposes and are not limiting.
The RDLs 480 and 489 may be formed above the insulator layer 361. The RDL 489 may cover the exposed contact pads 321, while the RDL 480 may not be connected to any contact or conductor within the insulator layers 361 or 371. Instead, the RDL 480 acts as a ground plane for the transmission line 490. While illustrated in
Another insulator layer 371 may be formed on the RDLs 480 and 489, which may be the top layer and surface layer of the device 301. An opening of the insulator layer 371 may be formed to expose the RDL 489 while the RDL 480 may be covered by the insulator layer 371. The openings of the insulator layer 371 may be made by removing a portion of the insulator layer 371 using a mask-defined photoresist etching process to expose the RDL 489. The size, shape, and location of the opening made are only for illustration purposes and are not limiting. The insulator layer 371 may be formed of a polymer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used. Formation methods include spin coating or other commonly used methods. The thickness of the insulator layer 371 may be between about 5 μm and about 30 μm, for example. The dimensions recited throughout the description are merely examples, and will change with the down-scaling of integrated circuits.
An UBM layer may comprise an UBM pad 391 and an UBM line 390. The UBM pad 391 may be formed around the opening of the insulator layer 371 and connected to the RDL 489. The UBM line 390 is formed in parallel to the RDL 480, and separated from the RDL 480 by the insulator layer 371. The UBM pad 391 and UBM line 390 may be formed of copper or copper alloys, which may include silver, chromium, nickel, tin, gold, and combinations thereof. Additional layers, such as a nickel layer, a lead-free pre-solder layer, or the combinations thereof, may be formed over the copper layer. The UBM pad 391 and UBM line 390 may have a thickness of between about 1 μm and about 20 μm. The UBM pad 391 may be called a contact pad as well.
The device 301 described above may merely be an example of an embodiment. There may be many other variations different from what is illustrated in
The die 601 may be packaged with the device 301 through the micro-bump layer, while the gap between the die 601 and the device 301 is covered by an underfill 571. The die 601 is connected to the connectors 603, which are placed on the micro-bump 485 within the micro-bump layer.
Connectors 603 may be used to provide connections between the micro-bump 485 and the die 601. The connectors 603 may be contact bumps such as micro-bumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the connectors 603 are tin solder bumps, the connectors 603 may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc., to a preferred thickness of about 100 μm. Once a layer of tin has been formed above the structure, a reflow may be performed in order to shape the material into the desired bump shape.
The underfill 571 may be used between the die 601 and the device 301 to strengthen the attachment of the die 601 to the device 301 and to prevent the thermal stresses from breaking the connections between the die 601 and the device 301. Generally, the material for the underfill 571, such as organic resin, is selected to control the coefficient of thermal expansion and the shrinkage of underfill 571. Initially, liquid organic resin is applied that flows into the gap between the die 601 and the surface of the device 301, which subsequently cures to control the shrinkage that occurs in underfill during curing.
The micro-bump layer may comprise the micro-bump 485, and the micro-bump line 470, where the micro-bump 485 is used to connect to other die such as the die 601, and the micro-bump line 470 is a part of the transmission line 490. The micro-bump line 470, and the micro-bump 485 may be formed at the same time with little or no additional cost, may be of a similar height, and may be made of similar materials. The height of the micro-bump layer may be defined by the height of the micro-bump 485, which may depend on the technology used in the package. For example, for current technology, the height of the micro-bump layer may be within the range of about 10 μm to about 50 μm, such as about 27 μm.
The micro-bump 485 may comprise a solder bump 471 formed above a Cu layer 475. An optional Ni layer 473 may be in between the solder bump 471 and the Cu layer 475. The solder bump 471 may comprise an electrically conductive solder material, e.g., Sn, Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof, or combinations of other electrically conductive material. For example, the solder bump 471 may be a Cu/SnAg solder bump. The micro-bump 485 may be formed by initially forming a Cu layer 475 through methods such as sputtering, evaporation, electroplating, printing, solder transfer, or ball placement, to a thickness of, e.g., about 15 μm, followed by forming a Ni layer 473, and finally followed by forming a solder layer 471 such as lead-free solder SnAg, formed in sequence using the same or similar method for each layer. Then a reflow is performed in order to shape the solder layer 471 into the desired bump shape shown as the solder bump 471. Any suitable method of producing the micro-bump 485 may alternatively be utilized. For example, the micro-bump 485 may be manufactured using the Controlled Collapse Chip Connection New Process (C4NP).
The micro-bump 485 may be placed on an UBM pad 391 of the device 301, sometimes referred to herein as a contact pad. The UBM pad 391 may fill an opening or partially filling an opening of an insulator layer such as an insulator layer 371. The UBM pad 391 may be further connected to a metal layer such as a RDL 489 or a contact pad 321 under the UBM pad 489 within the device 301. The micro-bump 485 may be of a height size from about 10 μm to about 50 μm. With the continuous reduction of feature sizes and package sizes, the sizes in embodiments may become smaller than the ones described above. On the other hand, the micro-bump 485 may be of a bigger size such as a size of a flip-chip bump or a package bump as well, depending on the particular applications of interest.
The micro-bump line 470 may be made of substantially similar materials as the materials used for the micro-bump 485. The micro-bump line 470 may be placed on the UBM line 390, which is in parallel to the RDL 480. The RDL 480, the micro-bump line 470 separated from the RDL 480 by the insulator layer 371, and the UBM line 390 under the micro-bump line 470 form the transmission line 490, where the RDL 480 is the ground plane, while the micro-bump line 470 and the UBM line 390 form the signal transmission line.
As illustrated in
The micro-bump line 470 may be of a rectangle shape with a width from around 10 μm to about 100 μm. The micro-bump line 470 may have a narrow, wide, or tapered shape. The body of the micro-bump line 470 may be of a substantially constant thickness. The micro-bump line 470 may be of other shapes such as a circle, an octagon, a rectangle, an elongated hexagon with two trapezoids on opposite ends of the elongated hexagon, an oval, a diamond, in top views.
In some embodiments, it is desirable for performance of the transmission line 490 that width of the ground plane line 480 to be about 1.5 times width of signal transmission line, which is the width of the micro-bump line 470. For better performance, it is further desirable that the width of the ground plane line 480 to be approximately 2 times width of signal transmission line 470 in some embodiments. Furthermore, the width is dependent on the distance between the ground plane line 480 and the signal transmission line 470, which is filled by insulator layer 371, or some other dielectric layer or substrate. As the distance between the ground plane line 480 and the signal transmission line 470 increases, the corresponding width of the signal transmission line 470 increases. In some embodiment, the width of the signal transmission line 470 may ideally be approximately 27.6 microns for a distance between the ground plane line 480 and the signal transmission line 470 of 20 microns.
A simplified view of the package 100 in
Another embodiment of the transmission line 490 is shown in
Another embodiment of the transmission line 490 is shown in
Another embodiment of the transmission line 490 is shown in
Microstrip transmission lines shown in
As illustrated in
As shown in
Alternatively, as shown in
Alternatively, as shown in
The device 301 and device 601 may comprise a substrate 302 and an insulator layer 371 on the substrate 302. There may be other layers of the device 301 and the device 601 not shown, such as the passivation layer, UBM layer, and contacts. The micro-bump lines 470, 484, and 482 are formed above the device 301 as one micro-bump layer. The device 301 may be an interposer, a part of a chip or an integrated circuit (IC) die, which may be the back or front side of a die, or a package substrate. Similarly, the device 601 may be an interposer, a part of a chip or an integrated circuit (IC) die, which may be the back or front side of a die, or a package substrate. These devices and any other suitable devices may alternatively be used and are fully intended to be included within the scope of the present embodiments.
Another embodiment of the transmission line 490 is shown in
A variant of CPW transmission line is formed when a ground plane is provided on the opposite side of the dielectric, which is called a finite ground-plane coplanar waveguide (FGCPW) transmission line, or more simply, a grounded coplanar waveguide (GCPW) transmission line.
As illustrated in
The micro-bump lines 470, 484, and 482 and the RDL 480 form the GCPW transmission line 490, where the micro-bump lines 484 and 482 are a pair of ground planes, the RDL 480 is a third ground plane, while the micro-bump line 470 is the signal transmission line. The micro-bump lines 470, 484, and 482 are all on the same plane, atop a dielectric medium such as the insulator layer 371 and separated by the underfill 571. Alternatively, as shown in
Alternatively, as shown in
Alternatively, a three dimensional view of the GCPW transmission line 490 of
In an embodiment, a device is provided. The device includes a first substrate, a first insulator layer over the first substrate, a redistribution layer over the first insulator layer, the redistribution layer comprising a first redistribution line and a second redistribution line, a second insulator layer over the redistribution layer, and a micro-bump layer over the second insulator layer, the micro-bump layer comprising a micro-bump line and a micro-bump structure, wherein the micro-bump line is laterally above the first redistribution line and the micro-bump structure contacts the second redistribution line, wherein the micro-bump line and the micro-bump structure comprise a same one or more layers. A second substrate is coupled to the micro-bump structure, and an underfill is interposed between the second insulator layer and the second substrate, the underfill completely separating the micro-bump line and the second substrate.
In an embodiment, a method of forming a semiconductor device is provided. The method includes forming a first redistribution layer over a first substrate, the first redistribution layer comprising a first redistribution line and forming a first insulator layer over the first redistribution layer. A first micro-bump line, a second micro-bump line, a third micro-bump line, and a micro-bump are formed, wherein the first micro-bump line, the second micro-bump line, and the third micro-bump line extend over the first insulator layer, wherein the micro-bump extends through an opening in the first insulator layer to the first redistribution line, wherein the first micro-bump line, the second micro-bump line, the third micro-bump line, and the micro-bump comprise same layers of same materials, wherein the second micro-bump line is interposed between the first micro-bump line and the third micro-bump line, the first micro-bump line and the third micro-bump line being coupled to ground, the second micro-bump line being a signal transmission line.
In an embodiment, a method of forming a semiconductor device is provided. The method includes forming a first insulator layer over a first substrate, forming a first redistribution layer over the first insulator layer, the first redistribution layer comprising a first redistribution line and a second redistribution line, forming a second insulator layer over the redistribution layer, and forming an opening in the second insulator layer, the opening exposing the second redistribution line. A micro-bump line and a micro-bump connector are simultaneously formed, wherein the micro-bump line extends over the first redistribution line in a plan view and the micro-bump connector extends through the opening to the second redistribution line.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
This application is a continuation application of U.S. application Ser. No. 16/390,218, filed Apr. 22, 2019, now U.S. Pat. No. 10,840,201, entitled “Methods and Apparatus for Transmission Lines in Packages,” which is a divisional application of U.S. application Ser. No. 14/875,448, filed Oct. 5, 2015, now U.S. Pat. No. 10,269,746, entitled “Methods and Apparatus for Transmission Lines in Packages,” which is a continuation application of U.S. application Ser. No. 13/750,814, filed Jan. 25, 2013, now U.S. Pat. No. 9,171,798, entitled “Methods and Apparatus for Transmission Lines in Packages,” each application is incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4939568 | Kato et al. | Jul 1990 | A |
| 5726502 | Beddingfield | Mar 1998 | A |
| 6404062 | Taniguchi et al. | Jun 2002 | B1 |
| 6501169 | Aoki et al. | Dec 2002 | B1 |
| 6614325 | Kocin | Sep 2003 | B1 |
| 6727118 | Lasky et al. | Apr 2004 | B2 |
| 6879492 | Alcoe et al. | Apr 2005 | B2 |
| 7145411 | Blair et al. | Dec 2006 | B1 |
| 7402901 | Hatano et al. | Jul 2008 | B2 |
| 7619489 | Mizuno | Nov 2009 | B2 |
| 7759212 | Lin et al. | Jul 2010 | B2 |
| 7977783 | Park et al. | Jul 2011 | B1 |
| 8013449 | Lin et al. | Sep 2011 | B2 |
| 8138857 | Ding et al. | Mar 2012 | B2 |
| 8227904 | Braunisch et al. | Jul 2012 | B2 |
| 8279025 | Cho | Oct 2012 | B2 |
| 8358009 | Furumiya et al. | Jan 2013 | B2 |
| 8896094 | Yen et al. | Nov 2014 | B2 |
| 9000586 | Do et al. | Apr 2015 | B2 |
| 9035457 | Lin et al. | May 2015 | B2 |
| 9041215 | Yu et al. | May 2015 | B2 |
| 9064705 | Lu et al. | Jun 2015 | B2 |
| 9087840 | Lin et al. | Jul 2015 | B2 |
| 9159650 | Yoshioka et al. | Oct 2015 | B2 |
| 9198284 | Sakuma | Nov 2015 | B2 |
| 10269746 | Kuo | Apr 2019 | B2 |
| 20030038331 | Aoki et al. | Feb 2003 | A1 |
| 20030060035 | Kimura | Mar 2003 | A1 |
| 20030193078 | Chungpaiboonpatana et al. | Oct 2003 | A1 |
| 20040026782 | Anzai | Feb 2004 | A1 |
| 20040089946 | Wen | May 2004 | A1 |
| 20040155728 | Cheung | Aug 2004 | A1 |
| 20050006760 | Terui | Jan 2005 | A1 |
| 20050017357 | Iida | Jan 2005 | A1 |
| 20050176233 | Joshi et al. | Aug 2005 | A1 |
| 20050233571 | Tao et al. | Oct 2005 | A1 |
| 20060079025 | Kripesh et al. | Apr 2006 | A1 |
| 20070080416 | Yoshioka et al. | Apr 2007 | A1 |
| 20070096313 | Chou | May 2007 | A1 |
| 20070241844 | Kim et al. | Oct 2007 | A1 |
| 20080054460 | Hung | Mar 2008 | A1 |
| 20080079103 | Liao | Apr 2008 | A1 |
| 20080111253 | Salzman | May 2008 | A1 |
| 20080293232 | Kang | Nov 2008 | A1 |
| 20090166849 | Jao | Jul 2009 | A1 |
| 20090170242 | Lin et al. | Jul 2009 | A1 |
| 20090236738 | Shim | Sep 2009 | A1 |
| 20090249610 | Ding et al. | Oct 2009 | A1 |
| 20090283905 | Huang et al. | Nov 2009 | A1 |
| 20090315633 | Ding et al. | Dec 2009 | A1 |
| 20090321948 | Wang et al. | Dec 2009 | A1 |
| 20100214041 | Cho | Aug 2010 | A1 |
| 20120018885 | Lee et al. | Jan 2012 | A1 |
| 20120077314 | Park et al. | Mar 2012 | A1 |
| 20120126417 | Chiu | May 2012 | A1 |
| 20130107484 | Sakuma | May 2013 | A1 |
| 20130200511 | Banijamali | Aug 2013 | A1 |
| Number | Date | Country |
|---|---|---|
| 1945817 | Apr 2007 | CN |
| 102027633 | Apr 2011 | CN |
| 10022449 | Jan 1998 | JP |
| 11195730 | Jul 1999 | JP |
| 2000235979 | Aug 2000 | JP |
| 2001156209 | Jun 2001 | JP |
| 2004079579 | Mar 2004 | JP |
| 2004266117 | Sep 2004 | JP |
| 2005032782 | Feb 2005 | JP |
| 2007103848 | Apr 2007 | JP |
| 2007123740 | May 2007 | JP |
| 2007134359 | May 2007 | JP |
| 2008103387 | May 2008 | JP |
| 2009218841 | Sep 2009 | JP |
| 10-2006-0100263 | Sep 2006 | KR |
| 20120014952 | Feb 2012 | KR |
| 10-2012-0018810 | Mar 2012 | KR |
| 10-2012-0032254 | Apr 2012 | KR |
| Entry |
|---|
| Nomiyama, Y. et al., “Low-Impedance and High-Q Transmission Line for mmw VCO,” IEEE Workshop on Signal Propagation on Interconnects, 2009, SPI 09, Department of Physical Electronics, Tokyo Institute of Technology, 4 pages. |
| Tesson, Oliver et al., “Electro-Magnetic Modeling and Design of Through Silicon Vias Based Passive Interposers for High Performance Applications up to the V-Band,” International Journal on Advances in Systems and Measurements, vol. 5, No. 1 & 2, 2012, http://www.iariajournals.org/systems_and_measurements/. |
| Veenstra, H. et al., “60GHz VCOs with Transmission Line Resonator in a 0.25 μm SiGe BiCMOS Technology,” IEEE Radio Frequency Integrated Circuits Symposium 2008, Philips Research, Eindhoven, The Netherlands, pp. 119-122. |
| Number | Date | Country | |
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| 20210082848 A1 | Mar 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14875448 | Oct 2015 | US |
| Child | 16390218 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16390218 | Apr 2019 | US |
| Child | 17098602 | US | |
| Parent | 13750814 | Jan 2013 | US |
| Child | 14875448 | US |
