Method of making buffer layers for III-V devices using solid phase epitaxy

Information

  • Patent Grant
  • 4952527
  • Patent Number
    4,952,527
  • Date Filed
    Friday, February 19, 1988
    37 years ago
  • Date Issued
    Tuesday, August 28, 1990
    34 years ago
Abstract
A new III-IV buffer material is described which is produced by low temperature growth of III-V compounds by MBE that has unique and desirable properties, particularly for closely spaced, submicron gate length active III-V semiconductor devices, such as HEMT's, MESFET's and MISFET's. In the case of the III-V material, GaAs, the buffer is grown under arsenic stable growth conditions, at a growth rate of 1 micron/hour, and at a substrate temperature preferably in the range of 150 to about 300.degree. C. The new material is crystalline, highly resistive, optically inactive, and can be overgrown with high quality III-V active layers.
Description
Claims
  • 1. A method of making an intermediate optically inert, electrically insulating crystalline layer of GaAs material on a substrate for growth thereon of high quality crystalline films comprising the steps of:
  • (a) forming in a chamber said crystalline layer of GaAs material by low temperature molecular beam deposition at less than 300.degree. C. of a flux of Ga and As molecular beam specie on a surface of a substrate formed of III-V materials;
  • (b) subjecting said layer to a heat treatment in an ambient containing arsenic;
  • (c) forming a thin stabilizing layer over said heat treated layer to minimize out diffusion of the arsenic.
  • 2. The method of claim 1 wherein the low temperature is in the range of 150-300.degree. C.
  • 3. A method of making GaAs device on a structure comprising the steps of:
  • (a) forming in a chamber, a crystalline buffer layer of GaAs material by low temperature molecular beam deposition at below 300.degree. C. of a flux of Ga and As materials on a surface of a substrate formed from the group comprising III-V materials;
  • (b) subjecting said layer to a heat treatment in an ambient containing arsenic;
  • (c) forming a thin stabilizing layer of GaAs material over said heat treated layer to minimize out diffusion of the arsenic;
  • (d) forming said GaAs device on said stabilizing layer.
  • 4. The method of claim 3 wherein the active device is a MESFET.
  • 5. The method of claim 3 wherein the GaAs device is formed in a crystalline active layer grown on said stabilizing layer.
  • 6. The method of claim 5 wherein the buffer layer has a resistivity of greater than 10.sup.7 ohm-cm.
  • 7. A method of making an intermediate buffer structure for growth thereon of high quality crystalline electro-optical films comprising the steps of:
  • (a) in a chamber, forming a crystalline buffer layer of thickness greater than 300.degree. .ANG. of material by low temperature molecular beam deposition at less than 300.degree. C. of a flux of Ga and As molecular beam specie on a surface of a substrate, which surface is comprised of materials from the same III-V group of materials as in the buffer layer;
  • (b) subjecting said buffer layer to a heat treatment at less than 900.degree. C. in an ambient containing arsenic;
  • (c) forming a thin stabilizing layer over said heat treated layer to minimize out diffusion of the arsenic; thereby to produce a stable buffer layer which is optically inert and electrically insulating.
  • 8. The method of claim 1 wherein the low temperature in step (a) is in the range of 150-300.degree. C. and the inert treatment in step (b) occurs at a temperature less than 900.degree. C.
  • 9. The method of claim 7 wherein the substrate is formed of semi-insulating GaAs.
  • 10. A method of making a III-V device on a substrate comprising the steps of:
  • (a) forming a buffer layer of III-V material by low temperature molecular beam deposition at less than 300.degree. C. of a flux of III-V molecules on said GaAs substrate in a chamber;
  • (b) subjecting said layer to a heat treatment in an ambient containing As;
  • (c) forming a thin stabilizing layer of III-V material over said heat treated layer to minimize out diffusion of the As;
  • (d) forming said III-V device on said stabilizing layer.
GOVERNMENT RIGHTS

The U.S. Government has rights in this invention pursuant to U. S. Air Force Contract No. F19628-85-C-0002. Semiconductor compounds of the III-V materials and alloys thereof; such as the compounds gallium arsenide (GaAs) and indium phosphide (InP) and the alloy aluminum gallium arsenide (AlGaAs) have unusual optoelectronic properties which make them attractive for many applications; ranging from microwave devices to optoelectronic devices. Among these applications is the use of such materials to make devices for high-speed logic integrated circuits and for microwave integrated circuits. The Schottky-barrier gate metal-semiconductor-field-effect transistor (MESFET) is a typical device used in these integrated logic circuits. The MESFET is a three terminal device consisting of a source, gate and drain. The source and drain terminals form low resistance contacts to a channel whose conduction is controlled by the depletion field of a Schottky-barrier gate. The conducting channel, which is placed on a semi-insulating (SI) substrate, may be formed either by ion implantation into the semi-insulating material, or by epitaxially growing the active layer on semi-insulating material. A number of problems associated with MESFET devices and circuits are attributed to the SI substrate. Such problems include backgating (or sidegating), hysteresis in the dependence of the drain-source current I.sub.ds upon drain-source voltage V.sub.ds, light sensitivity, low output resistance R.sub.d, low source-drain breakdown voltage BV.sub.SD, and low output power gain at RF frequencies. Among these problems, backgating is the most significant for both digital and analog circuit applications. In addition to these problems, increased subthreshold leakage current, threshold voltage shifts, and the inability to fully pinch-off the device for large V.sub.ds can occur as the gate length of MESFET's is reduced to submicron dimensions. Also, R.sub.d and BV.sub.SD are further decreased as the gate length is reduced. These problems are called short-channel effects and the characteristics of the layer underlying the active region can have a profound influence on them. Backgating or sidegating is the change of I.sub.ds in a MESFET as a result of a voltage applied to the substrate or an adjacent, add nominally isolated, contact pad (sidegate). Even though the sidegate and MESFET may be physically separated, as by mesa etching, the interaction may still arise because the substrate is of finite resistivity and charge can accumulate at the interface between the active layer and the substrate. In response to changes in voltage on the substrate or adjacent devices, the substrate conducts enough current to modulate the interface space-charge region. When this interfacial depletion region widens into the active channel, the device current is reduced. A buffer layer is often inserted between the active layer and the substrate to alleviate the problem of backgating. To reduce backgating and other substrate related effects, the buffer layer should provide an increase in bulk resistivity. A number of possible buffer layers have been suggested, including undoped GaAs, AlGaAs, and superlattice (GaAs/AlGaAs) buffers. Heretofore such buffer layers have met with only limited success. The invention comprises a crystalline buffer layer of III-V material or an alloy thereof and a process for growing such a layer on a substrate by molecular beam epitaxy (MBE) at low substrate temperatures. The buffer layer thus grown is optically inert or inactive, that is, the electrical conductivity of the material is substantially insensitive to light and the material is substantially non-luminescent. Furthermore, the layer is electrically insulating. After the buffer layer is grown to a suitable thickness, the outer surface is reconstructed and stabilized to enable good quality crystal growth of subsequent layers. Reconstruction is achieved by annealing in an ambient containing the more volatile of the III-V species, i.e., for GaAs the ambient is As; for InP the ambient is P. The function of stabilization is to prevent or minimize out-diffusion of the more volatile specie from the low temperature buffer layer. This may be achieved by providing a careful choice of initial regrowth temperature, to produce a buffer stabilizing layer over the low temperature buffer layer. Alternatively, a buffer stabilizing layer of material, which is capable of preventing out-diffusion, may be grown over the low temperature buffer layer.

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