Patent Application
20070269930
Novel features believed characteristic of the present disclosure are set forth in the appended claims. The disclosure itself, however, as well as a preferred mode of use, various objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings. The functionality of various circuits, devices or components described herein may be implemented as hardware (including discrete components, integrated circuits and systems-on-a-chip ‘SoC’), firmware (including application specific integrated circuits and programmable chips) and/or software or a combination thereof, depending on the application requirements. Similarly, the functionality of various mechanical elements, members, and/or components for forming modules, sub-assemblies and assemblies assembled in accordance with a structure for an apparatus may be implemented using various materials and coupling techniques, depending on the application requirements.
Traditional tools and methods for underfilling may be inadequate to ensure a void free assembly, and may result in producing over encapsulated and/or under encapsulated fillets resulting in a higher stress concentration. In addition, the traditional tools and methods for underfilling may be inadequate to handle backflow and bleed of the underfill, which may be undesirable. The backflow of the underfill may cover other substrate components such as chip capacitors. The backflow may also result in a reduced underfill being unable to completely fill the gap, thereby causing voids, and/or resulting in smaller underfill fillet. Bleed may result in localized material property differentials that may be undesirable for package reliability. This problem may be addressed by an improved system and method for performing an underfilling operation to fabricate semiconductor devices. According to an embodiment, in an improved system and method for underfilling a gap disposed between a substrate and a die, a selective surface of the substrate is treated by a plasma source. A matching surface of the die may be treated by the plasma source. The treating results in a roughening of the selective surface and the matching surface. The roughening improves wetting of an underfill on the selective surface and the matching surface compared to a non-treated surface. The underfill is dispensed to substantially fill the gap disposed between the selective surface and the matching surface of the die. The underfill is substantially contained within the gap by the wetting, which reduces the backflow and the bleed of the underfill.
The following terminology may be useful in understanding the present disclosure. It is to be understood that the terminology described herein is for the purpose of description and should not be regarded as limiting.
Ball grid array (BGA)—A type of chip package type that enables direct mounting of the chip to a substrate or printed circuit board via solder balls or bumps. The solder balls or bumps are arranged in a grid-style array and found on the underside of the chip to make the electrical connection to the outside.
Flip Chip (FC)—A technique to surface mount a chip or die on to a substrate (or a board) by flipping and directly connecting the chip or die to the substrate without using traditional wire bonding technique. The direct connection is typically via solder balls or conductive bumps. The gap between the chip and the substrate is underfilled with a polymeric material. A FC package configuration includes at least one semiconductor chip or die mounted in an active surface-down manner over a substrate (or another semiconductor chip) electrically and mechanically coupled to the same by means of the conductive bumps.
Chip scale package (CSP)—A chip package in which the total package size is no more than 20% greater than the size of the die within.
The present disclosure provides the tools and methods for dispensing underfill material uniformly and substantially without backflow and bleed in a flip chip assembly. The uniform distribution of the underfill advantageously minimizes the thermomechanical stress and improves reliability of an electronic assembly as described with reference to
A surface area of the substrate 120, where a flow of the underfill 150 is desired, is described as a selective surface 152. The selective surface 152 is in direct contact with the underfill 150. Similarly, a surface area of the die 110, where a flow of the underfill 150 is desired, is described as a matching surface 154, which may be substantially the same as the active surface 112. The matching surface 154 is in direct contact with the underfill 150. In the depicted embodiment, the selective surface 152 is greater than the matching surface 154, the matching surface 154 being disposed above the selective surface 152. Thus, the gap 140 is formed between two surfaces that include the selective surface 152 of the substrate 120 and the matching surface 154 of the die 110.
A plurality of contact pads 116 are disposed on the active surface 112. In a particular embodiment, the plurality of contact pads 116 are preferably made of aluminum, copper-doped aluminum, or copper and a combination or refractory metal layer such as titanium or tungsten, and noble metal layer such as palladium, gold, or platinum. The underfill 150 is preferably made of a polymeric material having an adhesive property that mechanically couples the die 110 (having a low CTE) to the substrate 120 (having a high CTE), including any solder joints or other conductive structures therebetween.
The die 110 is mounted on the substrate 120 integral with interconnections and a plurality of terminal pads 122, yet spaced apart by the gap 140. The substrate 120 preferably includes a printed circuit board made of FR-4 or a glass-epoxy laminate, and the plurality of terminal pads 122 are preferably composed of solder-wettable copper. The die 110 is attached by reflowable solder bumps 130, which extend across the gap 140 and connect the plurality of contact pads 116 on the die 110 to a corresponding one of the plurality of terminal pads 122 on the substrate 120 both electrically and mechanically. Preferably, tin or a tin alloy (such as tin/indium, tin/bismuth, tin/lead) of a desirable melting temperature is chosen for the solder bumps 130 to accomplish the reflow at a practical temperature. Solder bumps 130 may often be referred to as “solder balls” or simply as “bumps”. For silicon packages, a protective “soldermask” (not shown) may be made of a variety of insulating materials including polymers such as polyimide. Although the die 110 is shown to be mounted as a flip chip, other types of mounting such as upright with wire bonding are also contemplated. In a particular embodiment, the semiconductor device assembly 100 may be packaged as at least one of a chip scale package (CSP) and a ball grid array (BGA) package.
Plasma is a well-known and useful tool/technology used in various applications such as in the fabrication and packaging of semiconductor devices. Typical applications may include activation and cleaning of surfaces prior to wire bonding or die attachment, resin-flow-out removal, and wafer cleaning. Additionally, surface modification and/or surface roughening of materials by plasma treatment is well-known for enhancing adhesion in underfill processes. In simplistic terms, a plasma source may be generated by applying electrical power across a pair of electrodes to a gas, the gas and the electrodes being enclosed in a plasma chamber. An object that is to receive plasma treatment is placed in the chamber, near one of the electrodes. The gas selected and the amount of electrical power provided may determine the effects of the plasma treatment on the object.
In a particular embodiment, the selective surface 152 of the substrate 120 is plasma treated (not shown), preferably prior to the reflow and underfilling processes, to advantageously improve the wetting of the underfill on the selective surface 152 compared to a non-treated surface (e.g., surface that has not received the plasma treatment). In an embodiment, the matching surface 154 of the die 110 may be plasma treated (not shown) as an option, preferably prior to the reflow and underfilling processes, to advantageously improve the wetting of the underfill on the matching surface 154 compared to the non-treated surface.
In a particular embodiment, the plasma treatment may be provided to selective areas or surfaces such as the selective surface 152 and the matching surface 154 by masking off areas or surfaces of the substrate 120 and the die 110, where a flow of the underfill 150 is not desired. The masked off areas are thereby substantially protected from the plasma treatment. The object that is to receive the plasma treatment, e.g., the substrate 120 and the die 110 with the masked off areas, is placed in the plasma chamber. After receiving the plasma treatment, the object is removed from the plasma chamber and the mask and/or the protective covering is also removed. The use of the mask thereby enables providing plasma treatment to selective areas or surfaces of the substrate 120 and the die 110.
The objective of providing the plasma treatment to selective areas of the die 110 and/or the substrate 120 is to substantially enhance the flow of the underfill 150 within a desired fillet geometry zone (e.g., the gap 140) while substantially restricting the outward flow of the underfill 150 from the desired fillet geometry zone, which includes the selective surface 152. Thus, by restricting the outward flow, the undesirable backflow and bleed of the underfill 150 is substantially minimized. Since only the selective surface 152 and the matched surface 154 have been treated with plasma, the underfill 150 preferentially wets and flows easier within the plasma treated area, thus forming the controlled fillet geometry. The plasma treatment of the selective surface 152 and the matching surface 154 also cleans and activates both of these surfaces, thereby further improving the wetting and the flow. The plasma treatment results in increasing surface energy and/or decreases contact angle of the selective surface 152 and the matching surface 154 compared to the non-treated surface. The increasing surface energy and/or decreasing contact angle reduce the possibility of the backflow and bleed of the underfill 150.
In a particular embodiment, after the plasma treatment of the surfaces that form the desired fillet geometry zone (e.g., the gap 140), the underfill 150 is dispensed between the selective surface 152 and the matching surface 154 from one or more sides of the die 110 to uniformly fill the gap 140 without a substantial bleed and/or backflow of the underfill 150. Matching the volume of the gap 140 and of the dispensed underfill 150 substantially reduces the formation of voids. That is, the dispensing of the underfill 150 having a matching volume as the gap 140 is substantially contained within the gap 140, and hence within the selective surface 152 that is plasma treated. Due to surface tension, a small portion of the underfill 150 extends from an edge of the inactive surface 114 to an edge of the selective surface 152 to form a meniscus, thereby covering a side of the die 110 and the gap 140. Upon dispensing of the predefined volume, the underfill 150 (or the precursor) is heated, polymerized and “cured” to form the encapsulant.
The surface area 260 of the substrate 220 that is selected for the application of the flow inhibitor layer 290 is complementary to the selective surface 152 of the substrate 120. That is, surface area that was excluded from being plasma treated as described with reference to
As described earlier with reference to
In an embodiment, the dispensing of the underfill 250 to fill the gap 240 is substantially the same as underfilling of the semiconductor device 100 described with reference to
Various steps described above may be added, omitted, combined, altered, or performed in different orders. For example, the step 310 may include a plurality of sub-steps. Additional detail of the plurality of sub-steps included in the step 310 is described with reference to
Various steps described above may be added, omitted, combined, altered, or performed in different orders. For example, the step 410 may include one or more sub-steps such as applying a mask to protect the selective portion of the surface area from being covered by the underfill flow inhibitor layer.
Although illustrative embodiments have been shown and described, a wide range of modification, change and substitution is contemplated in the foregoing disclosure and in some instances, some features of the embodiments may be employed without a corresponding use of other features. Those of ordinary skill in the art will appreciate that the hardware and methods illustrated herein may vary depending on the implementation. For example, while certain aspects of the present disclosure have been described in the context of flip chip mounting, those of ordinary skill in the art will appreciate that the processes disclosed are capable of being used for assembly of semiconductor devices using different types of mounting techniques including conventional mounts with wire bonding.
The methods and systems described herein provide for an adaptable implementation. Although certain embodiments have been described using specific examples, it will be apparent to those skilled in the art that the invention is not limited to these few examples. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or an essential feature or element of the present disclosure.
The above disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
