Patent Application
20240421139
The disclosed technologies relate to semiconductor electronic devices and modules.
Currently, typical power semiconductor devices, including devices such as transistors, diodes, power MOSFETs and insulated gate bipolar transistors (IGBTs), are fabricated with silicon (Si) semiconductor material. More recently, wide-bandgap materials (e.g., III-N) have been considered for power devices due to their superior properties. III-Nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages, and provide very low on-resistance with fast switching times and low power losses. In order to reduce the cost of GaN power devices and compete with incumbent silicon power devices, GaN power devices are typically fabricated on electrically conductive or semi-conductive silicon substrates (i.e., GaN-on-Silicon), which are easily compatible with existing silicon fabrication facilities.
Electronic modules containing two or more semiconductor devices fabricated on conductive or semi-conductive substrates, such as silicon, are typically assembled on a direct bonded copper board (i.e., a DBC) or a printed circuit board (PCB) with an isolation layer (typically a ceramic layer such as AlN), to ensure electrical isolation between the semiconductor devices. This electrical isolation is required for proper operation of the modules.
A cross sectional view of the prior-art is illustrated in
The module 100 includes a board 12 which can be, for example, a direct bonded copper (DBC) substrate or a printed circuit board (PCB), which can be a base substrate for the module. In general, the package base 11 can be considered to include the layer to which to the package cover 10 is attached, and any layers further from the board 12 (but not the board 12 itself or layers closer to the board 12).
For the purpose of simplicity, board 12 of module 100 is a DBC substrate. A DBC substrate is formed by direct bonding of pure copper in a high temperature melting and diffusion process to a ceramic insulator such as AlN or Al2O3. The DBC substrate 12 includes an insulating layer 14 (e.g., ceramic, AlN, or Al2O3), between a bottom metal layer 13 (e.g., copper or nickel) and a top metal layer (e.g., copper or nickel). The top metal layer is patterned into at least a first portion 15, a second portion 16, a third portion 17, a fourth portion 18, and a fifth portion 19. Portions 15-19 are each electrically isolated from one another by a trench 25 formed through the top metal layer of DBC 12.
Module 100 further includes a first semiconductor device 20 and a second semiconductor device 30, where either device 20 or 30 can be, for example, a vertical or lateral FET, IGBT, MOSFET, JFET, HEMT or other appropriate device. In this embodiment, the first and second semiconductor devices 20 and 30 shown in
Module 100 further includes a second semiconductor device 30, which can be, for example, a lateral or vertical FET, IGBT, MOSFET, JFET, HEMT or other appropriate device. The second device 30 is formed on a conductive or semiconductive substrate 31 (e.g., Si, SiC or GaN). The second device 30 includes a second source electrode 32 and a second drain electrode 33 and is attached to the fourth portion of the top metal layer 18 with an adhesion layer 34 (e.g., solder, epoxy, or solder paste).
Connector 41 electrically connects the first drain electrode 22 to the first portion of the top metal layer 15. Connector 42 electrically connects the first source electrode 23 to the third portion of the top metal layer 17. Connector 43 electrically connects the second drain electrode 32 to the third portion of the top metal layer 17. Connector 44 electrically connects the second source electrode 33 to the fifth portion of the top metal layer 19. Connectors 41-44 can be formed of wire-bonds, copper clips, wire ribbons, etc. To insure electrical isolation of the first semiconductor device 20 and the second semiconductor device 30, the insulating layer 14 is used to isolate and separate the devices from the thermally conductive structural package base 11 within module 100. The thickness of insulator layer 14 can commonly be greater than 200 μm thick.
Described herein are integrated designs for lateral devices (e.g., GaN HEMT power transistors), for which an insulating substrate is used to integrate the device into the component packaging, or electronic module, to improve the thermal performance of the module. The term “device” will be used in general for any transistor, or switch, or diode when there is no need to distinguish between them.
In a first aspect, an electronic component is described. The electronic component includes and electronic component package including a high thermally conductive package base. The component further includes a first lateral III-N device including a first insulating substrate, the first lateral III-N device comprising a first side and a second side, where a first III-N material structure is on the first side of the first lateral III-N device. A second lateral III-N device including a second insulating substrate, the second lateral III-N device comprising a first side and a second side, where a second III-N material structure is on a first side of the second lateral III-N device. The second side of the first lateral III-N device is directly mounted and physically attached to the thermally conductive package base and the second side of the second lateral III-N device is directly mounted and physically attached to the thermally conductive package base.
In a second aspect, an electronic module is described. The module including a package, a high thermally conductive package base, and a substrate mounted to the package base. The substrate comprising a first metal layer on an insulating layer, the first metal layer including a first portion, a second portion, and a third portion. The substrate further including a first opening and a second opening, where the first metal layer and the insulating layer are removed in the first opening and the second opening to expose a top surface of the package base, and a first semiconductor device is mounted to the package base in the first opening, and second semiconductor device is mounted to the package base in the second opening.
In a third aspect, an electronic module is described. The electronic module includes a package, a thermally conductive package base, a high-side switch, a low-side switch, a high-voltage terminal, an output terminal, and a ground terminal. The high-side switch comprising a first III-N depletion-mode transistor and a first enhancement-mode transistor, and the low-side switch comprising a second III-N depletion-mode transistor and a second enhancement-mode transistor. A drain electrode of the first III-N depletion-mode transistor is electrically connected to the high-voltage terminal, a source electrode of the first enhancement-mode transistor is electrically connected to the output terminal, a drain electrode of the second III-N depletion-mode transistor is electrically connected to the output terminal, and a source electrode of the second enhancement-mode transistor is electrically connected to the ground terminal, where a substrate of the first and second III-N depletion-mode transistors is directly physically attached to the high thermally conductive package base.
Each of the devices, transistor, and modules described herein can include one or more of the following features. The insulating substrates can be a sapphire substrates. The first and second insulating substrates includes a backmetal layer, and the backmetal layer is attached to the package base using a thermally conductive solder, a thermally conductive epoxy, or a thermally conductive solder paste. A printed circuit board (PCB) can be within the component package, the PCB including an insulating layer, a first side, and a second side opposite the first side, where the first side of the PCB includes a first metal layer physically attached to the package base. The second side of the PCB can include a second metal layer, and the second metal layer includes at least a first portion, a second potion, and a third portion, where the first portion, the second portion, and the third portion are each electrically isolated from the other portions. The drain electrode of the first lateral III-N device is electrically connected to the first portion, the drain electrode of the second lateral III-N device is electrically connected to the second portion, the source electrode of the first lateral III-N device is electrically connected to the second portion, and the source electrode of the second lateral III-N device is electrically connected to the third portion. A first vertical MOSFET device, where the drain electrode of the MOSFET device is electrically connected and physically attached to the source electrode of the first lateral III-N device. A second vertical MOSFET device where the drain of the second MOSFET is electrically connected and physically attached to the source of the second III-N device. A resistor, capacitor, or IC is mounted to the second side of the PCB. The PCB is physically isolated from the package base. The device can be a high-voltage device with a breakdown voltage greater than 600V and an on-resistance of less than 15 mohm. The first portion of the first metal layer is connected to a high-voltage terminal, the second portion of the first metal layer is connected to an output terminal, and the third portion of the first metal layer is connected to a ground terminal. The high-side (first semiconductor device) and low-side (second semiconductor device) switches of the electronic module can form a half-bridge circuit. The high-side switch and the low-side switch can be encased in a single electronic package. The first and second III-N depletion-mode transistors are lateral GaN HEMT transistors. The first and second enhancement-mode transistors are vertical silicon MOSFET transistors.
As used herein, a “hybrid enhancement-mode electronic device or component”, or simply a “hybrid device or component”, is an electronic device or component formed of a depletion-mode transistor and an enhancement-mode transistor, where the depletion-mode transistor is capable of a higher operating and/or breakdown voltage as compared to the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor with a breakdown and/or operating voltage about as high as that of the depletion-mode transistor. That is, a hybrid enhancement-mode device or component includes at least 3 nodes having the following properties. When the first node (source node) and second node (gate node) are held at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage (i.e., a voltage larger than the maximum voltage that the enhancement-mode transistor is capable of blocking) applied to the third node (drain node) relative to the source node. When the gate node is held at a sufficiently positive voltage (i.e., greater than the threshold voltage of the enhancement-mode transistor) relative to the source node, current passes from the source node to the drain node or from the drain node to the source node when a sufficiently positive voltage is applied to the drain node relative to the source node. When the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The depletion-mode transistor can have a breakdown and/or maximum operating voltage that is at least two times, at least three times, at least five times, at least ten times, or at least twenty times that of the enhancement-mode transistor.
As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1 with 0≤w≤1, 0≤x≤1, 0≤y≤1, and 0≤z≤1. III-N materials, layers, or devices, can be formed or prepared by either directly growing on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, detaching from the original substrate, and bonding to other substrates.
As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.
As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications, especially power switching applications.
As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device which is optimized for high-voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the device is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that can be supplied by the circuit or power supply, and Vmax can for example be 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. For a bidirectional or four quadrant switch, the blocked voltage could be of any polarity less a certain maximum when the switch is OFF (±Vmax such as ±300V or ±600V, ±1200V and so on), and the current can be in either direction when the switch is ON.
As used herein, the terms “over,” “under,” “between,” and “on” refer to a relative position of one layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations are performed relative to a substrate without consideration of the absolute orientation of the substrate.
As used herein, an electrode refers to the metal layers within a device or transistor which are connected to either the source, gate or drain of the device. A “pad” such as a “source pad, drain pad, or gate pad” refer to the uppermost un-passivated portion of the electrode from the semiconductor material which is used to electrically connect the device or transistor to the package e.g., with solder, epoxy, wire-bonds and/or metal clips.
As used herein, a material with a high thermal conductivity is defined as a material with a thermal conductivity greater than 1 (one) as measured in watts per meter-kelvin.
The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Additional features and variations may be included in the implementations as well. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.
Due to the low cost of silicon substrates and the widely available processing equipment which is compatible with silicon, current industry commercialization efforts are largely focused on forming lateral III-N semiconductor devices (e.g., GaN/AlGaN HEMT devices) on semi-conducting or conducting silicon substrates. However, integration of multiple semiconductor devices formed on silicon substrates into a single electronic module needs electrical isolation between the devices, and therefore can suffer from poor thermal performance due to the required addition of electrical insulation boards between the power devices and the module package base. To insure electrical isolation of the multiple semiconductor devices, an insulating shim is used to isolate and separate the devices from the thermally conductive structural package base within the module. The thickness of insulating shim can commonly be greater than 200 μm thick. However, this introduces a significant thermal resistance between the semiconductor devices and the module package thermal pad and/or heatsink and leads to a degradation in module performance. Hypothetically the insulating shim could be instead replaced with a thin dielectric layer (e.g., SiN), but in this case high breakdown voltages (e.g., upwards of 1200V) would be difficult to achieve, and switching performance would be reduced due to multiple devices becoming capacitively coupled to the same thermally conductive package base. Also, back-gating cross-talk between devices will reduce performance, particularly for monolithically integrated devices such as those described in
Due to the recent success of the LED lighting market, the price of insulating substrates, such as sapphire substrates, has recently reduced. Furthermore, technologies to fabricate thin insulating substrates, such as sapphire substrates less than 100 μm thick, are now becoming available. Forming semiconductor devices, such as lateral GaN devices on insulating substrates, allows for novel module designs and layout considerations that are not possible with semiconductor devices formed on conductive or semi-conductive substrates such as silicon, silicon carbide, or gallium nitride substrates, due to the inherent semi-conducting properties. This provides opportunities to further improve module performance while simultaneously reducing packaging complexity of III-Nitride devices and transistors formed on insulating substrates.
Described herein are integrated designs for lateral devices (e.g., III-N HEMT devices), for which insulating substrates are used to integrate the devices into the electronic component packaging (e.g., electronic module) in order to improve the electrical and thermal performance. This simultaneously reduces packaging complexity and overall cost of module assembly. As used herein, a lateral device is defined as a semiconductor device for which the source electrode and the drain electrode are formed on the same side of the device substrate.
A cross sectional view of electronic module 200, is illustrated in
Module 200 includes a first semiconductor device 220 and a second semiconductor device 230, which either device 220 or 230 can be, for example, a lateral FET, IGBT, MOSFET, JFET, HEMT or other appropriate device. For simplicity, it is assumed that the first and second semiconductor device 220 and 230 are high power III-N HEMT devices capable of blocking voltages greater than 600V. The first device 220 includes a III-N HEMT material structure 225 formed (e.g., grown in a metal organic chemical vapor deposition reactor) on a first side of an insulating device substrate 221 (e.g., a sapphire substrate). The first device 220 further includes a first backside metallization layer 225a formed on, e.g., directly contacting, a second side of the insulating device substrate 221. The first device 220 includes a first source electrode 222 and a first drain electrode 223 formed on a first side of the device 220. A second side of the device 220 (opposite the first side of device 220), e.g., the metallization layer 225a, is directly mounted and physically attached to the thermally conductive structural package base 211 (i.e., without the use of an isolation and/or insulating shim between the first device and the package base) using an adhesion layer 224 (e.g., solder, epoxy, or solder paste which is thermally reflowed with the first backside metallization layer). The thermal reflow may result in the metallization layer 225a and the adhesion layer 224 to form an alloyed portion. Although a metal layer 213 can be used for other devices on the base 211, the first and second devices 220, 230 can be attached to the base 211 without such an intervening layer. In addition, there is no intervening insulating layer (e.g., ceramic, AlN, or Al2O3 shim) to electrically isolate the first device 220 from the package base 211.
Module 200 further includes a second semiconductor device 230, which can be, for example, a lateral FET, IGBT, MOSFET, JFET, HEMT or other appropriate device. For simplicity, we can assume the second semiconductor device 230 is a high power III-N HEMT devices capable of blocking voltages greater than 600V. The second device 230 includes a III-N HEMT material structure 235 formed on a first side of an insulating device substrate 231 (e.g., sapphire). The second device 230 further includes a second backside metallization layer 235a formed on, e.g., directly contacting, a second side of the insulating device substrate 231. The second device 230 further includes a second source electrode 232 and a second drain electrode 233 formed on a first side of the device 230. A second side of device 230 (opposite the first side of device 230), e.g., the metallization layer 235a, is directly mounted and physically attached to the thermally conductive structural package base 211 (i.e., without the use of an isolation and/or insulating shim between the first device and the package base) using an adhesion layer 234 (e.g., solder, epoxy, or solder paste which is thermally reflowed with the second backside metallization layer). There is no intervening insulating layer (e.g., ceramic, AlN, or Al2O3 shim) or bottom metal layer to electrically isolate the second device 230 from the package base 211.
Referring back to
The first and second device 220 and 230, respectively, can be high power semiconductor devices with a high breakdown voltage, for example, greater than 600V or even greater than 1200V. They can be configured into several different common circuitry topologies. For example, the first device 220 can be a low-side transistor, and the second device 230 can be a high-side transistor, and the first and second devices can be configured into a half-bridge circuit. Alternatively, the first and second devices 220 and 230 can be configured to operate as a bi-directional switch (commonly referred to as a Four-Quadrant Switch or FQS). In addition, the module 200 and all subsequently described modules withing this specification may not be limited to only two devices, such that the configurations of the modules described herein can serve as a basic building block which can be expanded or multiplied as need to fit the designers requirements. For example, any module described herein may include two or more low-side transistors connected in parallel or two or more high-side transistors connected in parallel. Furthermore, the devices described herein may be configured to form a three-phase inverter. The circuits and modules described herein may include additional electronic components such as capacitors, resistors, inductors, driving transistors, and diodes as needed to safely and effectively operate the circuit.
Devices fabricated on insulating device substrates (e.g., sapphire substrates) can include a backside metallization layer (such as layer 225a and 235a), for example, a Ti/Ni/Ag layer under the insulating device substrate. This backside metallization layer is used to physically attach (e.g., with solder or epoxy) the device to the component packaging or the thermally conductive structural package base. The backside metallization layer reacts with the solder or epoxy during a thermal reflow process to create the adhesion layers 224 and 234.
The module 200 further includes a substrate board 212 which can be, for example, a direct bonded copper (DBC) substrate formed by direct bonding of pure copper in a high temperature melting and diffusion process to a ceramic insulator such as AlN or Al2O3 or a printed circuit board (PCB), although PCBs have the advantage of lower manufacturing costs. For the purpose of simplicity, board 212 of module 200 is a PCB. The PCB 212 includes a backmetal layer 213 which is physically attached to the thermal conductive package base 211 with solder or epoxy.
The PCB 212 can have at least 3 portions. In some implementations, the portions are formed by patterning the PCB to remove one or more regions of the PCB where the first and second devices 220 and 230 are located. For example, one or more apertures, e.g., two apertures 212a, 212b (one aperture for each of the devices 220 and 230), can be formed through the PCB 212. Removing these regions below the first semiconductor device 220 and the second semiconductor device 230 exposes a top surface of the thermally conductive package base 211 in the regions where the substrate 212 is removed.
The first portion of the PCB 212 includes an insulating layer 214a (e.g., ceramic, AlN, or Al2O3), between a bottom metal layer 213 (e.g., copper or nickel) and a top metal layer 215 (e.g., copper or nickel). The top metal layer 215 of the first portion of PCB 212 can be configured to be connected to a ground node of module 200. The second portion of the PCB 212 includes an insulating layer 214b between a bottom metal layer 213 and a top metal layer 217. The top metal layer 217 of the second portion of PCB 212 can be configured to be connected to an output node of module 200. The top metal layer 217 of the second portion of PCB 12 can be formed between the first device 220 and the second device 230. The third portion of the PCB 212 includes an insulating layer 214c, between a bottom metal layer 213 and a top metal layer 219. The top metal layer 219 of the third portion of PCB 212 can be configured to be connected to a high-voltage node of module 200. Top metal portions 215, 217, and 219 are each electrically isolated from one another. For example, PCB 212 can be a single continuous substrate (such as the substrate 12 in
Alternatively, portions of the insulating layer 14 (and optionally, the backmetal layer 13) that extend laterally beyond the top metal portions 215, 217, and 219 can also be removed. Removal of portions of the PCB 212 to electrically isolate the top metal portions 215, 217, and 219 can be performed as part of the same etching operation that forms the openings in the PCB where the first and second devices 220 and 230 are located. Alternatively, PCB 212 can be made up of at least 3 discrete portions and assembled into module 200 around the first and second semiconductor devices 220 and 230, respectively. In this case the bottom metal layer and insulating layer of the regions 214a, 214b, 214c would be separated by gaps.
Referring back to
To insure electrical isolation between the first semiconductor device 220 and the second semiconductor device 230, the insulating substrates 221 and 231 of the first and second semiconductor devices are used to electrically isolate and separate the active regions of the devices (i.e., the III-N HEMT structures 225 and 235) from the conductive structural package base 211 within the module 200. The insulating substrates 221 and 231, for example, can be thinned down, e.g., by polishing or etching, to a thickness less than 200 μm, or less than 100 μm. Such small thickness leads to lower thermal resistance between the device active region and the module package base, thus reducing the overall junction-to-case thermal resistance of the module. This improves thermal dissipation, reduces the power losses, and expands the maximum rating of the module (such as max rated DC current). However, if the insulating substrates 221 and 231 are excessively thinned, the breakdown voltage is reduced, negative back-gating effects are increased, and switching interference (i.e. cross-talk) between the multiple devices is increased. As such, the minimum insulating substrate thickness should be greater than 50 μm. Layers 224/234 can be engineered to match the thermal expansion coefficient between the module package base 211 and the substrate to improve robustness and reliability during thermal cycling.
The first device 220 can be a low-side transistor, and the second device 230 can be a high-side transistor, and the first and second devices can be configured into a half-bridge circuit. In a half-bridge circuit, the top metal layer 219 is connected to a high-voltage terminal. The high-voltage terminal is configured to be connected to a high-voltage power supply. The top metal layer 217 is connected to an output terminal. The top metal layer 215 is connected to a ground terminal. The ground terminal is configured to be connected to a circuit ground.
Module 400 is similar to module 200 of
Referring to
Module 402 of
Module 404 of
Although not shown for simplicity, the modules 200, 300, 400, 402, 404 of
Integrated device 620 is connected to the thermally conductive structural package base 511 with adhesion layer 624, which can be similar to adhesion layer 224 previously described in
A first advantage of reverse-side circuitry is reduced parasitic inductances. In fact, the connection of the top-side device 620 with the back-side components 726 can have much smaller stray inductance than the connection between the power device and components placed on the board through wire-bonds and/or clips and/or ribbon bonds and/or board traces. Therefore, back-side circuitry can help reduce power losses and EMI due to stray inductances, and can enable higher operating frequencies. A second advantage of reverse-side circuitry is a more compact design with less usage of area on the board, therefore leading to system miniaturization, desired in applications with stringent requirements on size, for example integrated motor drives, and miniaturized, distributed Internet-of-Things devices and systems.
Furthermore, it may be desirable to have separate independent insulating PCB layers configured to the first and second power devices. As shown in module 802 of
A module 804 shown in
Furthermore, it may be desirable to have separate independent insulating PCB layers configured to the first and second power devices. As shown in module 806 of
Module 900 includes a first high-side switch 230, and second high-side switch 230′, and a third high-side switch 230″. Module 900 further includes a first low-side switch 220, a second low-side switch 220′, and a third low-side switch 220″. The drain electrodes (233/233′/233″) of the high-side switches (230/230′/230″) are each connected to the top metal layer 219. The source electrode 232 of the first high-side switch 230 and drain electrode 223 of first low-side switch 220 are each connected to the top metal layer 217. The source electrode 232′ of the second high-side switch 230′ and drain electrode 223′ of second low-side switch 220′ are each connected to the top metal layer 217′. The source electrode 232″ of the third high-side switch 230″ and drain electrode 223″ of third low-side switch 220″ are each connected to the top metal layer 217″. The source electrodes (222/222′/222″) of the low-side switches (220/220′/220″) are each connected to the top metal layer 215. The input gates electrodes of the high-side switches (230/230′/230″) are respectfully connected to the top metal layers (218/218′/218″). The input gates electrodes of the low-side switches (220/220′/220″) are respectfully connected to the top metal layers (216/216′/216″). Each of the insulating substrates of the high-side switches and low-side switches of module 900 are physically mounted to the package base of 911 of module 900 through a via portion of PCB 912 where the insulating layer 914 has been removed or is otherwise not present.
Although not shown for simplicity. Any of the modules 400, 402, 404, 500, 502, 504, 600, 700, 800, 802, 804, 806, or 900 can included a low-voltage enhancement mode device configured similar to device 320 shown in
Although not shown for simplicity, all the modules described herein contain module leads which extend outside of the package case and are configured to be connected to external circuitry. These module leads can be power terminals, gate drive terminals, ground terminals, or any other package lead required for proper operation. In addition, all the modules described herein can be connected to a heat sink. The heat sinks can be externally connected. Depending on the heat sink configuration, the modules described herein can be either top-side cooled, or bottom-side cooled.
A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Accordingly, other implementations are within the scope of the following claims.
This application is a National Stage Application under 35 U.S.C. § 371 and claims the benefit of International Application No. PCT/US2022/082182, filed Dec. 21, 2022, which claims the benefit under 35 U.S.C. § 119 (e) of priority to Provisional Application No. 63/292,905, filed on Dec. 22, 2021. The disclosure of each of the foregoing applications is incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2022/082182 | 12/21/2022 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63292905 | Dec 2021 | US |
