Patent Application
20210175178
Various features relate to packages that include an integrated device, but more specifically to a package that includes a double-sided redistribution portion.
Various features relate to packages that include an integrated device, but more specifically to a package that includes a double sided redistribution layer (RDL) portion.
One example provides a package comprising a first integrated device, a first encapsulation layer, a redistribution portion, a second integrated device and an encapsulation layer. The first encapsulation layer encapsulates the first integrated device. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first encapsulation layer are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second encapsulation layer is coupled to the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device.
Another example provides an apparatus that that includes a first integrated device, a first means for encapsulation configured for encapsulating the first integrated device, a redistribution portion, a second integrated device and a second means for encapsulation. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first means for encapsulation are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second means for encapsulation is coupled to the second surface of the redistribution portion. The second means for encapsulation is configured for encapsulating the second integrated device.
Another example provides a method for fabricating a package. The method provides a first integrated device. The method forms a first encapsulation layer over the first integrated device. The method forms a redistribution portion over the first integrated device and the first encapsulation layer. The method of forming the redistribution portion includes forming a plurality of redistribution interconnects. The method couples a second integrated device to a second surface of the redistribution portion. The method forms a second encapsulation layer over the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device.
Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.
In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
The present disclosure describes a package that includes a first integrated device, a first encapsulation layer, a redistribution portion, a second integrated device and an encapsulation layer. The first encapsulation layer encapsulates the first integrated device. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first encapsulation layer are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second encapsulation layer is coupled to the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device. The redistribution portion has a thickness that is thinner than package substrates, which allows the package to be thinner and have a more compact form factor.
As shown in
The redistribution portion 202 may include a double-sided redistribution portion, where integrated device(s) may be coupled to both surfaces (e.g., top surface, bottom surface) of the redistribution portion 202. The redistribution portion 202 includes a first surface (e.g., top surface) and a second surface (e.g., bottom surface). The redistribution portion 202 includes at least one dielectric layer 220 and a plurality of redistribution interconnects 222. The plurality of redistribution interconnects 222 may include a U-shape interconnect and/or V-shape interconnect. The terms “U-shape” and “V-shape” shall be interchangeable. The at least one dielectric layer 220 may include a polymer. The plurality of redistribution interconnects 222 may have a minimum pitch and a minimum line and spacing (L/S). In some implementations, the minimum pitch for the plurality of redistribution interconnects 222 is in a range of approximately 100-200 micrometers (μm). In some implementations, the minimum line and spacing (L/S) for the plurality of redistribution interconnects 222 is in a range of approximately 5/5-20/20 micrometers (μm). The redistribution portion 202 may be thinner than other substrates that have the same number of metal layers. The thinner redistribution portion 202 allows the package 200 to be thinner and more compact than other packages that include substrates formed using non-redistribution layers fabrication processes. As an example, when a redistribution layer (RDL) fabrication process is used to fabricate the redistribution portion (e.g., 202), the thickness of each of the redistribution metal layers (on which redistribution interconnects 222 are formed) may be approximately 5-10 micrometers (μm). In contrast, interconnects for substrates that are fabricated using Semi-Additive Processing (SAP) or modified Semi Additive Processing (mSAP) for example, have a thickness that is approximately 15 micrometers (μm). The dielectric layer 220 may be considered as one dielectric layer 220. However, in some implementations, the process of forming the dielectric layer 220 may include forming several dielectric layers over one another. In some implementations, when a redistribution layer (RDL) fabrication process is used, each dielectric layer may have a thickness that is approximately 5-10 micrometers (μm). In contrast, when SAP or mSAP is used to form the dielectric layers of a substrate, each dielectric layer of the substrate is approximately 20-25 micrometers (μm).
The integrated device 204 is coupled to a first surface (e.g., top surface) of the redistribution portion 202. In particular, the integrated device 204 may be directly coupled to one or more redistribution interconnects from the plurality of redistribution interconnects 222, such that a coupling between the integrated device 204 and the redistribution interconnect is free of solder interconnect. The integrated device 205 is coupled to the first surface of the redistribution portion 202. In particular, the integrated device 205 may be directly coupled to one or more redistribution interconnects from the plurality of redistribution interconnects 222, such that a coupling between the integrated device 205 and the redistribution interconnect is free of solder interconnect. The integrated device 204 and the integrated device 205 may be co-planar to each other.
The passive device 210 is coupled to the first surface of the redistribution portion 202. In particular, the passive device 210 may be directly coupled to one or more redistribution interconnects from the plurality of redistribution interconnects 222, such that a coupling between the passive device 210 and the redistribution interconnect is free of solder interconnect. The passive device 212 is coupled to the first surface of the redistribution portion 202. In particular, the passive device 212 may be directly coupled to one or more redistribution interconnects from the plurality of redistribution interconnects 222, such that a coupling between the passive device 212 and the redistribution interconnect is free of solder interconnect. A passive device (e.g., 210, 212) may include a capacitor.
The encapsulation layer 208 may be coupled to the first surface of the redistribution portion 202 such that the encapsulation layer 208 at least partially encapsulates the integrated device 204, the integrated device 205, the passive device 210 and/or the passive device 212. The encapsulation layer 208 may be a first encapsulation layer. The encapsulation layer 208 may be a means for encapsulation. The encapsulation layer 208 may include a mold, a resin, an epoxy and/or polymer.
The integrated device 206 is coupled to a second surface (e.g., bottom surface) of the redistribution portion 202. The integrated device 206 is coupled to the redistribution portion 202 through a plurality of solder interconnects 260. In particular, the integrated device 206 is coupled to one or more redistribution interconnects from the plurality of redistribution interconnects 222, through the plurality of solder interconnects 260. The plurality of solder interconnects 260 may include copper pillars and/or solder interconnects. The integrated device 207 is coupled to the second surface of the redistribution portion 202. The integrated device 207 is coupled to the redistribution portion 202 through a plurality of solder interconnects 270. In particular, the integrated device 207 is coupled to one or more redistribution interconnects from the plurality of redistribution interconnects 222, through the plurality of solder interconnects 270. The plurality of solder interconnects 270 may include copper pillars and/or solder interconnects. The integrated devices 204, 205, 206 and 206 may share the same redistribution portion 202.
A plurality of solder interconnects 280 is coupled to the second surface of the redistribution portion 202. In particular, the plurality of solder interconnects 280 is coupled to redistribution interconnects from the plurality of redistribution interconnects 222.
The encapsulation layer 209 may be coupled to the second surface of the redistribution portion 202 such that the encapsulation layer 209 at least partially encapsulates the integrated device 206, the integrated device 207 and/or the plurality of solder interconnects 280. The size and/or shape of the plurality of solder interconnects 280 may vary with different implementations. The encapsulation layer 209 may be a second encapsulation layer. The encapsulation layer 209 may be a means for encapsulation. The encapsulation layer 209 may include a mold, a resin, an epoxy and/or polymer. The encapsulation layer 209 may be similar to the encapsulation layer 208. In some implementations, a surface (e.g., bottom surface) of the encapsulation layer 209 may be co-planar with a back side surface of the integrated device 206 and/or a back side surface of the integrated device 207.
The integrated device (e.g., 204, 205, 206, 207) may include a die (e.g., bare die). The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a GaAs based integrated device, a surface acoustic wave (SAW) filters, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon carbide (SiC) based integrated device, and/or combinations thereof.
Different implementations may couple different components and/or different numbers of components to the redistribution portion 202. Different implementations may use different interconnects to couple the package to a board 290.
The package 300 includes the redistribution portion 202, the integrated device 204, the integrated device 205, the integrated device 206, the integrated device 207, the encapsulation layer 208, the encapsulation layer 209, the passive device 210 and the passive device 212, as described above.
As shown in
The package 400 includes the redistribution portion 202, the integrated device 204, the integrated device 205, the integrated device 206, the integrated device 207, the encapsulation layer 208, the encapsulation layer 209, the passive device 210 and the passive device 212, as described above.
As shown in
Having described various packages with a double-sided redistribution portion, processes for fabricating a package that includes a double-sided redistribution portion will now be described below.
It should be noted that the sequence of
Stage 1, as shown in
Stage 2 illustrates a state after the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212 are placed over the adhesive layer 510 and the carrier 500. A pick and place method may be used to place the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212. Different implementations may place different devices and/or different number of devices over the adhesive layer 510 and the carrier 500.
Stage 3 illustrates a state after the first encapsulation layer 208 is formed over the adhesive layer 510 and the carrier 500, such that the first encapsulation layer 208 at least partially encapsulates the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212. The process of forming and/or disposing the first encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.
Stage 4 illustrates a state after another carrier 520 and another adhesive layer 530 are provided over the first encapsulation layer 208. The carrier 520 may be a substrate and/or a wafer. The carrier 520 may include glass and/or silicon. The carrier 520 may be a second carrier. The adhesive layer 530 may be disposed (e.g., formed) over the carrier 520. The adhesive layer 530 may be an adhesive film. Stage 4 also illustrates a state after the adhesive layer 510 and the carrier 500 are decoupled from the first encapsulation layer 208 and the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212.
Stage 5, as shown in
Stage 6 illustrates a state after cavities 541 are formed in the dielectric layer 540. An etching process (e.g., photo etching process) may be used to form the cavities 541. A photo etching process may be used when the dielectric layer 540 includes a photo imageable dielectric layer.
Stage 7 illustrates a state after a plurality of redistribution interconnects 542 is formed over the dielectric layer 540 and the cavities 541. Forming the plurality of redistribution interconnects 542 may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. Stage 7 illustrates an example of forming a redistribution layer (e.g., redistribution metal layer) for the redistribution portion 202. The plurality of redistribution interconnects 542 may be part of the plurality of redistribution interconnects 222.
Stage 8 illustrates a state after the dielectric layer 550 is formed over the plurality of redistribution interconnects 542 and the dielectric layer 540. The dielectric layer 550 may include polymer. The dielectric layer 550 may be similar to the dielectric layer 540.
Stage 9, as shown in
Stage 10 illustrates a state after a plurality of redistribution interconnects 552 is formed over the dielectric layer 550 and the cavities 551. Forming the plurality of redistribution interconnects 552 may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. Stage 10 illustrates an example of forming a redistribution layer (e.g., redistribution metal layer) for the redistribution portion 202. The plurality of redistribution interconnects 552 may be part of the plurality of redistribution interconnects 222.
Stage 11 illustrates a state after the dielectric layer 560 and a plurality of redistribution interconnects 562 are formed over the dielectric layer 550 and the plurality of redistribution interconnects 552. The dielectric layer 560 may include polymer. The dielectric layer 560 may be similar to the dielectric layer 550. Forming the dielectric layer 560 may include forming cavities in the dielectric layer 560, as described at Stages 6 and 9. An etching process (e.g., photo etching process) may be used to form the cavities in the dielectric layer 560. Forming the plurality of redistribution interconnects 562 may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. Stage 11 illustrates an example of forming a redistribution layer (e.g., redistribution metal layer) for the redistribution portion 202. The plurality of redistribution interconnects 562 may be part of the plurality of redistribution interconnects 222.
Stage 12, as shown in
Stage 12 may illustrate the redistribution portion 202 that includes the at least one dielectric layer 220 and the plurality of redistribution interconnects 222. The dielectric layers 540, 550, 560 and 570 may be represented by the at least one dielectric layer 220. Stage 12 illustrates that the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212 are coupled to a first surface of the redistribution portion 202. When the redistribution layer (RDL) fabrication process is used to fabricate the redistribution portion (e.g., 202), the thickness of each of the dielectric layers (e.g., 540, 550, 560, 570) may be approximately 5-10 micrometers (μm), and the thickness of each of the redistribution metal layers (on which redistribution interconnects are formed) may be approximately 5-10 micrometers (μm).
Stage 13 illustrates a state after the integrated device 206 and the integrated device 207 are coupled to a second surface of the redistribution portion 202. In particular, the integrated device 206 is coupled to redistribution interconnects 222 of the redistribution portion 202, through the plurality of solder interconnects 260. The integrated device 206 is coupled to redistribution interconnects 222 of the redistribution portion 202, through the plurality of solder interconnects 260. The integrated device 207 is coupled to redistribution interconnects 222 of the redistribution portion 202, through the plurality of solder interconnects 270.
Stage 14 illustrates a state after the plurality of solder interconnects 580 is coupled to the second surface of the redistribution portion 202. In particular the plurality of solder interconnects 580 is coupled to the redistribution interconnects 222.
Stage 15, as shown in
Stage 16 illustrates a state after cavities 590 are formed in the second encapsulation layer 209. A laser process or etching process may be used to form the cavities 590. The cavities 590 may be formed to expose the plurality of solder interconnects 580. The shape and/or size of the cavities 590 may vary with different implementations.
Stage 17, as shown in
Stage 18 illustrates a state after the adhesive layer 530 and the carrier 520 are decoupled from the first encapsulation layer 208. Stage 18 may include the package 200 that includes the redistribution portion 202, as described in
It should be noted that the sequence of
Stage 1, as shown in
Stage 2 illustrates a state after the plurality of ball interconnects 380 is coupled to the second surface of the redistribution portion 202. The plurality of ball interconnects 380 may be coupled to the plurality of redistribution interconnects 222 of the redistribution portion 202. The plurality of ball interconnects 380 may include copper balls and solder interconnects. A pick and a place process and a reflow process may be used to couple the plurality of ball interconnects 380 to the redistribution portion 202.
Stage 3 illustrates a state after the integrated device 206 and the integrated device 207 are coupled to a second surface of the redistribution portion 202. In particular, the integrated device 206 is coupled to redistribution interconnects 222 of the redistribution portion 202, through the plurality of solder interconnects 260. The integrated device 206 is coupled to redistribution interconnects 222 of the redistribution portion 202, through the plurality of solder interconnects 260. The integrated device 207 is coupled to redistribution interconnects 222 of the redistribution portion 202, through the plurality of solder interconnects 270.
Stage 4, as shown in
Stage 5 illustrates a state portion of the second encapsulation layer 209 is optionally removed. A grinding process may be used to remove portions of the second encapsulation layer 209. The portions of the second encapsulation layer 209 are removed such that a surface of the second encapsulation layer 209 is co-planar with a surface of the integrated device 206 and/or the integrated device 207.
Stage 6, as shown in
Stage 7 illustrates a state after the adhesive layer 530 and the carrier 520 are decoupled from the first encapsulation layer 208. Stage 7 may include the package 300 that includes the redistribution portion 202, as described in
It should be noted that the sequence of
Stage 1, as shown in
Stage 2 illustrates a state after the plurality of pillar interconnects 480 is coupled to the second surface of the redistribution portion 202. The plurality of pillar interconnects 480 may be coupled to the plurality of redistribution interconnects 222 of the redistribution portion 202. In some implementations, a deposition process (e.g., plating process, sputtering process) may be used to form the plurality of pillar interconnects 480 over the redistribution portion 202. In some implementations, a pick and a place process may be used to couple the plurality of pillar interconnects 480 to the redistribution portion 202. Solder interconnects may be used to couple the plurality of pillar interconnects 480 to the plurality of redistribution interconnects 222.
Stage 3, as shown in
Stage 4 illustrates a state after the second encapsulation layer 209 is formed over the second surface of the redistribution portion 202, such that the second encapsulation layer 209 at least partially encapsulates the integrated device 206, the integrated device 207, and/or the plurality of pillar interconnects 480. The process of forming and/or disposing the second encapsulation layer 209 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.
Stage 5, as shown in
Stage 6 illustrates a state after the adhesive layer 530 and the carrier 520 are decoupled from the first encapsulation layer 208. Stage 6 may include the package 400 that includes the redistribution portion 202, as described in
In some implementations, fabricating a package that includes a double-sided redistribution portion includes several processes.
It should be noted that the sequence of
The method provides (at 805) a carrier (e.g., 500) and an adhesive layer (510). The carrier 500 may be a substrate and/or a wafer. The carrier 500 may include glass and/or silicon. The carrier 500 may be a first carrier. The adhesive layer 510 may be disposed (e.g., formed) over the carrier 500. The adhesive layer 510 may be an adhesive film. Stage 1 of
The method places (at 810) integrated device(s) and passive device(s) over the adhesive layer and the carrier. For example, the method may perform a pick and place operation to place the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212 over the adhesive layer 510 and the carrier 500. Different implementations may place different devices and/or different number of devices over the adhesive layer 510 and the carrier 500. Stage 2 of
The method forms (at 815) a first encapsulation layer (e.g., 208) over the adhesive layer 510 and the carrier 500, such that the first encapsulation layer 208 at least partially encapsulates the integrated devices and the passive devices. For example, the first encapsulation layer 208 may be formed such that the first encapsulation layer 208 at least partially encapsulates the integrated device 204, the integrated device 205, the passive device 210 and the passive device 212. The process of forming and/or disposing the first encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 3 of
The method forms (at 820) a redistribution portion (e.g., 202) over the first encapsulation layer (e.g., 208), the integrated devices and the passive devices. A first surface of the redistribution portion may be formed and/or coupled to first encapsulation layer, the integrated devices and the passive devices. Forming the redistribution portion includes forming at least one dielectric layer (e.g., 220) and a plurality of redistribution interconnects (e.g., 222). Forming the plurality of redistribution interconnects 222 may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. Stages 5-12 of
The method couples (at 825) interconnects to a second surface of the redistribution portion (e.g., 202). Different implementations may couple different types of interconnects. In some implementations, the method couples (at 825) solder interconnects (e.g., 580, 280) to a second surface of the redistribution portion (e.g., 202). For example, the solder interconnects may be coupled to the redistribution interconnects 222. In some implementations, the method couples (at 825) ball interconnects (e.g., 380) to a second surface of the redistribution portion (e.g., 202). For example, the ball interconnects may be coupled to the redistribution interconnects 222. In some implementations, the method couples (at 825) pillar interconnects (e.g., 480) to a second surface of the redistribution portion (e.g., 202). For example, the pillar interconnects may be coupled to the redistribution interconnects 222. Stage 14 of
The method couples (at 830) integrated devices and passive devices to the second surface of the redistribution portion (e.g., 202). In some implementations, solder interconnects (e.g., 260, 270) may be used to couple integrated devices (e.g., 206, 207) and/or passive devices to the redistribution interconnects 222 of the redistribution portion 202. Stage 13 of
The method forms (at 835) a second encapsulation layer (e.g., 209) over the second surface of the redistribution portion 202, such that the second encapsulation layer at least partially encapsulates the integrated devices (e.g., 206, 207), the interconnects (e.g., 380, 480, 580). The second encapsulation layer may also at least partially encapsulate passive devices. The process of forming and/or disposing the second encapsulation layer 209 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 15 of
In some implementations, after the second encapsulation layer is formed, cavities may be formed in the second encapsulation, and/or solder interconnects (e.g., 280) may be provided over the interconnects (e.g., 380, 480, 580).
The method decouples (at 840) the adhesive layer (e.g., 530) and the carrier (e.g., 520) from the first encapsulation layer (e.g., 208), leaving the package (e.g., 200, 300, 400) that includes the redistribution portion 202. Stage 18 of
One or more of the components, processes, features, and/or functions illustrated in
It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. The term “encapsulating” means that the object may partially encapsulate or completely encapsulate another object. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1.
In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. An interconnect may include one or more metal components (e.g., seed layer+metal layer). In some implementations, an interconnect is an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal, ground or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form the interconnects. In some implementations, a chemical vapor deposition (CVD) process and/or a physical vapor deposition (PVD) process for forming the interconnects. For example, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.
Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.
The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.
