1. Field of the Invention
The invention relates in general to a package structure and a manufacturing method thereof, and more particularly to a package structure with several chips and a manufacturing method thereof.
2. Description of the Related Art
Recently, consumer electronics with less weight and smaller volume are developed to meet the market demands. Within the limited spaced of an electronic product, more semiconductor devices with various functions and more complex circuits need to be disposed to enhance the functionality of the electronic product. Normally, in the packaging process of the semiconductor device, a semiconductor chip is disposed on a substrate and electrically connected to the substrate through a wire-bonding process, a flip-chip process or other bonding processes subsequently, so that the inner microelectronic circuit can be electrically connected to the outer circuit through the contacts or pads on the substrate. However, along with the increment of the complexity of semiconductor chips, the number of electric contacts or pads increases accordingly. Thus the area of the substrate, in accordance with the volume of the semiconductor device, cannot be reduced effectively. In order to break the spatial limitation, a semiconductor device with multi-chip package structure is developed for applying in all kinds of integrated and multifunctional electronic products. In the semiconductor device with multi-chip package structure, different semiconductor chips are disposed and integrally packaged in a single package structure. As a result, the number of semiconductor devices in an electronic product can be reduced, and the space in the electronic product can be used more efficiently.
Nevertheless, during operation of the semiconductor device, electromagnetic radiation is inevitably generated when each semiconductor chip functions. Along with the miniature of the semiconductor device, the semiconductor chips in the multi-chip package structure keep a reduced distance compared to that in the traditional single-chip package structure. The interference between the semiconductor chips increases consequently. As a result, noise is raised, and the operation quality of the chips is degraded. These drawbacks hinder the semiconductor device from further reducing its size, and cause the overall quality of the electronic product not being guaranteed.
The invention is directed to a package structure and a manufacturing method thereof. A shielding plate is disposed between a first chip and a second chip for lowering the electromagnetic interference between the first chip and the second chip. As a result, the package structure has advantages such as high stability, high quality, small volume and low developing cost.
According to the present invention, a package structure including a substrate, a shielding plate, a first chip, a first sealant, a second chip and a second sealant is provided. The substrate has an upper surface and a lower surface. The shielding plate is disposed on the upper surface. The first chip disposed on the shielding plate is electrically connected to the substrate. The first sealant disposed on the upper surface encapsulates the shielding plate and the first chip. The second chip disposed on the lower surface is electrically connected to the substrate. The second sealant disposed on the lower surface encapsulates the second chip.
According to the present invention, another package structure including a package, a shielding plate, a supporting element, a second chip and a first sealant is provided. The package includes a first chip and a substrate to which the first chip is electrically connected. The shielding plate is disposed over the package. The supporting element is disposed under the shielding plate. The second chip is dispose on the shielding plate and electrically connected to the substrate. The first sealant disposed on the substrate encapsulates the shielding plate and the second chip.
The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Four embodiments are provided as follow to illustrate the present invention. The embodiments are different in the arrangement of the components in the package structure. However, the embodiments are used as examples, and the present invention is not limited thereto. Also, the embodiments are encompassed by the present invention. Furthermore, unnecessary components are not shown in the drawings for clarity.
Please refer to
Next, as shown in
Then, a first chip 15 is disposed on the shielding plate 13 and is electrically connected to the substrate 11 through wire bonding, as shown in
Afterwards, as shown in
Further, a second chip 17 is disposed on the lower surface 11b and electrically connected to the substrate 11 through wire bonding, as shown in
Thereon, as shown in
Furthermore, a solder ball 19 is disposed on the lower surface 11b. As shown in
Moreover, the shielding plate 13 in the present embodiment includes several holes or is provided with a spiral structure for example. The area of the shielding plate 13 is preferably greater than that of the first chip 15 and the second chip 17. On the other hand, the shielding plate 13 is made of single conductive material or includes several material layers. Please referring to
Please referring to
In the package structure and the manufacturing method thereof according to the first embodiment of the invention, the shielding plate 13 is disposed on the upper surface 11a of the substrate 11. Also, the first chip 15 is disposed on the shielding plate 13, and the second chip 17 is disposed on the lower surface 11b of the substrate 11. In other words, the shielding plate 13 is located between the first chip 15 and the second chip 17. Furthermore, the shielding plate 13 is electrically connected to a ground plane through the contact pad 11c, the conductive trace 12 and the solder ball 19. When the package structure 100 functions, the shielding plate 13 shields the first chip 15 and the second chip 17. The two chips are prevented from interfering with each other, so that the operation accuracy of the chips is increased. The stability of the product is increased greatly.
Please refer to
Next, as shown in
Afterwards, a shielding plate 44 is disposed on the supporting element 43, as shown in
Thereon, as shown in
Subsequently, a first sealant 47 encapsulating the shielding plate 44, the second chip 46 and the supporting element 43 is disposed on the substrate 41, as shown in
After, as shown in
In the present embodiment, the supporting element 43 is exemplified by the second sealant. However, anyone who has ordinary skill in the field of the invention can understand that the invention is not limited thereto. The supporting element 43 can be any object that separates the shielding plate 44 and the first chip 42. Please referring to
Besides, the first end 48a of the conductive trace 48 is electrically connected to the shielding plate 44 through the conductive element 45. The second end 48b of the conductive trace 48 is electrically connected to the solder ball 49. For example, the solder ball 49 is a grounding ball. The shielding plate 44 is preferably electrically conductive material and is electrically connected to a ground plane through the conductive element 45, the conductive trace 48 and the solder ball 49.
Furthermore, the materials of the shielding plate 44 and the solder ball 49 in the present embodiment are the same as those in the first embodiment of the invention and not described repeatedly. For example, the shielding plate 44 and the solder ball 49 includes several materials (as shown in
The package structure in the present embodiment and the package structure 400 in the second embodiment (as shown in
In the present embodiment, the step of providing the package further includes following steps. Please refer to
The manufacturing method of the package structure in the present embodiment further performs the step of disposing a supporting element. Please referring to
Afterwards, the adhesive film 58 is removed. Then, the steps of disposing the shielding plate, the second chip and first sealant are preformed. The steps of disposing the shielding plate, the second chip and first sealant in the present embodiment are the same as those in the second embodiment of the invention and not described repeatedly.
After the first sealant 47 is disposed on the substrate 51, the package structure 500 according to the third embodiment of the invention is accomplished. Please referring to
Please referring
Because the first chip 62 is disposed on the substrate 41 by flip-chip bonding and is electrically connected to the substrate 41 through several contacts 65 under the first chip 62, the shielding plate 44 may dispose on the first chip 62 directly; thus lowering both the cost and the volume of the package structure 600.
In the package structure and the manufacturing method thereof according to above embodiments of the invention, the shielding plate is disposed between the first chip and the second chip. As a result, the first chip and the second chip are shielded by the shielding plate, so that the two chips do not interfere with each other while operating. Further, the operation stability of the chips and the quality of the product are guaranteed. Besides that, the package structures according to the above embodiments of the invention can be manufactured simply by adding a shielding plate between the chips in the conventional package structures. That is, the manufacturing method of the package structure according to the embodiments of the invention is compatible with the conventional manufacturing method. Therefore, the cost for developing a new manufacturing process can be saved. Moreover, due to the shield of the shielding plate, the distance between the two chips can be further reduced, and the volume of the package structure can be decreased accordingly.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.