FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, in particular to RAM (Random Access Memory) having phase change storage element.
BACKGROUND OF THE INVENTION
Phase change memory (PCM) known as PRAM (Phase-change Random Access Memory) or Ovonic Unified Memory, is a type of non-volatile memory. PCM leverages the unique behavior of chalcogenide material which allows it to change structurally between crystalline and amorphous based on the controlled input of current. The crystalline and amorphous states each have dramatically different electrical resistivity and this forms the basis by which data is stored such as high resistance represents data “1” and low resistance represents data “0”. Chalcogenide is the same material utilized in re-writable optical media such as CD-RW and DVD-RW. In those instances, the material is manipulated optically instead of electrically.
PCM makes use of a mixture of germanium, antimony and tellurium called GST (Ge2Sb2Te5). Under high temperature (over 600° C.), the chalcogenide becomes liquid. Once cooled, it is frozen into an amorphous glass-like state and its electrical resistance is high. By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance.
The properties of chalcogenide glasses were first explored as a potential memory technology in the 1960s. However, some issues prevented commercialization of the technology. In the present invention, the memory circuit techniques will improve those issues, and the invented memory cell structure will overcome the current issues of the PCM. Before describing the present invention, there is a need to review the prior art of the PCM.
FIG. 1A illustrates the prior art of PCM using MOS access transistor and sense amplifier. PCM cell 110 is consisted of a resistive storage element 113 including chalcogenide material, one side of the cell is connected to the bit line 117, and the other side of the cell is connected to the drain 116 of the MOS transistor 112. The word line 111 is connected to the gate of MOS transistor, and the source 114 and the body 115 are stuck to ground. In order to access resistive storage element, MOS transistor 112 should be turned on by the word line 111. However, the turn-on resistance of the MOS transistor is relatively high. High turn-on resistance of the MOS transistor requires more current when write, and the read speed is very slow because the bit line capacitance should be discharged through the MOS access transistor. Furthermore, resistive storage element adds more resistance to the read path. This is one of the limitations of the MOS transistor as an access device for the PCM. The high resistive MOS transistor and another high resistive storage element are not a good combination to write and read. There is a prior art as “Architecture of a phase-change nonvolatile memory array”, U.S. patent application Ser. No. 6,816,404.
When read, the MOS access transistor discharges the bit line to ground, and the sense amplifier 119 compares the discharged voltage of the bit line 117 with VREF. The capacitance of the bit line would be very big because multiple memory cells are connected to a bit line which is connected to the resistive storage directly. It adds more capacitance to the bit line. Generally, the sense amplifier 119 needs the waiting time to sense the bit line, which time is the discharging time of the bit line. As shown in FIG. 1A, the discharging path of the bit line has a resistive storage 113 and a MOS transistor 112. The resistive storage has cell-to-cell, wafer-to-wafer variations, and MOS transistors vary as well. In this respect, there are so much variations in the input of the sense amplifier, which is an issue of the prior art of the memory cell and sense amplifier.
In FIG. 1B, in order to reduce the resistance of the access device, the p-n diode access device is proposed as “Ultra-high density storage device using phase change diode memory cells and methods of fabrication thereof”, U.S. patent application Ser. No. 6,979,838. The memory cell 120 has the diode access device 122. The diode 122 reduces the turn-on resistance when the diode line 121 is selected because the diode can flow the current through the whole junction while MOS transistor can flow the current through the shallow inversion layer. However, the capacitance of the bit line 124 is still very big, and the sense amplifier 125 should sense the voltage of the discharged bit line which has so much variation with the resistive storage 123.
Recently, there are proposals to use a p-n-p-n diode as a memory device, which is known as Shockley diode or thyristor, is a solid-state semiconductor device similar to two-terminal p-n diode, with an extra terminal which is used to turn it on. Once turned on, diode (p-n-p-n diode or n-p-n-p diode) will remain on conducting state as long as there is a significant current flowing through it. If the current falls to zero, the device switches off. Diode has four layers, with each layer consisting of an alternately p-type or n-type material, for example p-n-p-n and n-p-n-p. The main terminals, labeled anode and cathode, are across the full four layers, and the control terminal, called the gate, is attached to one of the middle layers. The operation of a diode can be understood in terms of a pair of tightly coupled transistors, arranged to cause the self-latching action.
Diodes are mainly used where high currents and voltages are involved, and are often used to control alternating currents, where the change of polarity of the current causes the device to automatically switch off; referred to as ‘zero cross operation’. The device can also be said to be in synchronous operation as, once the device is open, it conducts in phase with the voltage applied over its anode to cathode junction. This is not to be confused with symmetrical operation, as the output is unidirectional, flowing only from anode to cathode, and so is asymmetrical in nature. These properties are used control the desired load regulation by adjusting the frequency of the trigger signal at the gate. The load regulation possible is broad as semiconductor based devices are capable of switching at extremely high speeds over extremely large numbers of switching cycles.
In FIG. 1C, the schematic of diode is illustrated. It consists of four terminals, such that the anode 131 is connected to power supply or regulating node, the base 132 of p-n-p transistor 135 serves as the collector 132 of n-p-n transistor 134, the collector 133 of p-n-p transistor 135 serves as the base of n-p-n transistor 134 which is controlled by the voltage controller 136. In order to turn on diode and hold the state of turn-on, the voltage controller should raise the voltage from ground level to VF (forward bias, 0.6v˜0.8v for silicon). And the voltage controller 136 should supply the current 137, referred as the base current, which current depends on the characteristic of transistor 134 and 135. Once the base current 137 establishes the forward bias (VF), the collector 132 of n-p-n transistor 134 holds the current path 139 from the base of p-n-p transistor 135. After then, p-n-p transistor 135 is turned on because the base 132 has forward bias from the emitter 131. This makes the current path 138 which can keep the turn-on state. This is the holding state as long as the base has not so much leakage to drive the base voltage under forward bias (VF) even though the voltage controller 136 is open. To turn off diode, the voltage controller 136 should lower the voltage of the base of n-p-n transistor 134 under forward bias. To do so, the voltage controller 136 should (negatively) flow more current than the current path 138.
Diode can hold the states of turn-on or turn-off, but it has very high holding current to store ‘on’ state. There are prior arts to apply a diode itself to a memory device, such as, “High density planar SRAM cell using bipolar latch-up and gated diode breakdown”, U.S. patent application Ser. No. 6,104,045, and “Thyristor-type memory device” U.S. patent application Ser. No. 6,967,358 and “Semiconductor capacitively-coupled negative differential resistance device and its applications in high-density high-speed memories and in power switches”, U.S. patent application Ser. No. 6,229,161. These prior arts require very high holding current and multiple internal voltage generators, in order to use a diode itself as a holding device which becomes a memory cell. This is difficult approach and it needs high power internal voltage generators which flows high current. And high current flowing eventually raises operating temperature by “Joule heating”, which produces more junction leakage and gate leakage. Consequently, the data stored in diode can lose data quickly by those leakages.
Another approach in the present invention is that the diode replaces the MOS access device as a switching element, not holding device. However diode can not easily replace the MOS device as an access device because it has unidirectional current control characteristic and internal feedback loop. Now the present invention devotes to replace MOS transistor with a diode as an access device and a control methodology has been invented to control the diode for memory operation. Diode can work for the memory devices as a switching element, not a storage element. Furthermore, diode can replace sense amplifier as well, such that diode output makes information “on” or “off” which are digital values. It gives as many as advantages to design and fabricate it on the wafer.
The conventional MOS access transistor has a parasitic bipolar transistor where the base 115 in FIG. 1A controls the emitter/collector 114 and 116, where the base 115 serves as the body of the MOS transistor 112. During read and write cycle, the base 115 is at ground to prevent bipolar effect. The parasitic bipolar transistor is not wanted device in the conventional memories which is usually turned off by applying reverse bias voltage, but now adding one more terminal to the parasitic bipolar transistor in the conventional memory, a p-n-p-n diode (or n-p-n-p) can serve as an access device for the next generation memory devices with good performance and simple structure. In addition, chalcogenide material is used as a storage element, which exhibits non-volatile memory behavior combined with four-terminal diode access device.
SUMMARY OF THE INVENTION
In the present invention, diode-based memory including phase change storage element is described. The memory cell includes a resistive storage element and a p-n-p-n diode, which combination is less complicated to fabricate, compared to fabricating complex MOS device. Replacing MOS access transistor with a diode as a switching device in the memory cell, there are as many as advantages to configure memory arrays, which can simplify the memory cell structure with a few additional process steps. Diode need not be a high performance device nor have a high current gain, and diode can serve as a sense amplifier as well to detect the voltage of the storage node whether it is forward bias or not, then diode sends binary results to the bit line. However the operation of diode is not as simple as that of MOS transistor because it has internal feedback loop and unidirectional current control in nature even though it has almost no parasitic effects. In the present invention, the circuit methodology has been invented to use a diode as an access device.
Removing MOS device from the memory cell, the cell structure is simplified and new type of cell structures can be formed, which can reduce cell area dramatically with no performance degradation. And the present invention of memory can be implemented on the bulk and SOI wafer, which makes to integrate high density memory and control circuit on a chip.
The word line cuts off the holding current during standby. Thus there is no standby current in the memory cell, which realizes low power consumption. The low power consumption suppresses ‘Joule heating’, which may reduce gate delay and achieve high yield.
Various types of diode can be applied to form the memory cell, such as silicon including solid-state, amorphous and stretchable silicon, germanium, GaAs, SiGe, and metal-semiconductor diode (Schottky diode).
The memory operation is fast and stable. Diode output can be transferred to bit line quickly, because diode current is generally much higher than that of MOS transistor. The diode makes current with its whole junction area while MOS transistor makes current with inversion layer on the surface. The diode detects the storage node whether it is forward bias or not when the word line is asserted. Thus the diode serves as a sense amplifier which generates the current or not, and then the latch has a current mirror. The current mirror repeats the bit line current and latches the result, which realizes very fast latching operation which does not require waiting time for enabling the sense amplifier. Furthermore, replica delay circuits control the read path, which realize very fast read access and reduce the disturbance of the current pulse to the resistive storage element. The short current pulse can reduce the disturbance to the memory cell, which helps to store data for long time.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings which are incorporated in and form a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1A illustrates the prior art of the phase change memory including the MOS access transistor. FIG. 1B illustrates the prior art of the phase change memory including the p-n diode access device. FIG. 1C illustrates the p-n-p-n diode of the prior art.
FIG. 2A illustrates the schematic of the diode-based phase change memory and current mirror with p-n-p-n diode for the present invention. FIG. 2B illustrates the schematic of the diode-based phase change memory and current mirror with n-p-n-p diode for the present invention.
FIG. 3A illustrates the related schematic for the example configuration in order to explain the write operation of the present invention. FIG. 3B illustrates the related schematic for the example configuration in order to explain the read operation.
FIG. 4A illustrates the related schematic in order to explain the read “1” operation. FIG. 4B illustrates the related schematic in order to explain the read “0” operation.
FIG. 5A illustrates the related timing diagram how to control the resistor line (RL) when read. FIG. 5B illustrates the related I-V curve for reading data “1”, “0” and standby.
FIG. 6A illustrates the related schematic of the read path. FIG. 6B illustrates the related timing diagram of the read operation.
FIG. 7A illustrates the related schematic of the replica delay for generating the resistor line enable (RE) signal. FIG. 7B illustrates the related timing diagram of the FIG. 7A.
FIG. 8A illustrates the related schematic of the replica delay for generating the latch enable (LE) signal. FIG. 8B illustrates the related timing diagram of the FIG. 8A.
FIG. 9A illustrates the related schematic of the replica delay for generating the output enable (OE) signal. FIG. 9B illustrates the related timing diagram of the FIG. 9A.
FIG. 10A illustrates the related schematic of the write path. FIG. 10B illustrates the related timing diagram of the FIG. 10A.
FIG. 11A illustrates the cross sectional view of the related memory cell (FIGS. 2A and 2B) which is shown from the word line direction. FIG. 11B illustrates the cross sectional view of the related memory cell in FIG. 11A which is shown from the bit line direction.
FIG. 12A illustrates the alternative cross sectional view of the related memory cell (FIGS. 2A and 2B) which is shown from the word line direction. FIG. 12B illustrates the alternative cross sectional view of the related memory cell in FIG. 12A which is shown from the bit line direction. FIG. 12C illustrates the alternative top view of the related memory cell in FIG. 12A.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)
Reference is made in detail to the preferred embodiments of the invention. While the invention is described in conjunction with the preferred embodiments, the invention is not intended to be limited by these preferred embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, as is obvious to one ordinarily skilled in the art, the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so that aspects of the invention will not be obscured.
Detailed descriptions for the present invention are described as follows, which include the schematics, the timings and cross sectional views.
In FIG. 2A, diode-based phase change memory is illustrated. A p-n-p-n diode replaces MOS access transistor as an access device, wherein the emitter 202 of p-n-p Q1 is connected to the word line (WL) 201, the base 203 of p-n-p Q1 is connected to one side of the resistive storage element 207, the other side of the resistive storage element is connected to the resistor line (RL) 208, the collector 204 of p-n-p Q1 serves as the base of n-p-n Q2, the emitter 205 of n-p-n Q2 is connected to the bit line (BL) 206, There is a feedback loop wherein the collector 203 of n-p-n Q2 serves as the base 203 of p-n-p Q1 which serves as the storage node as well, and the collector 204 of p-n-p Q1 serves as the base 204 of n-p-n Q2. The storage node 203 is controlled by RL line 208, and the floating node 204 of n-p-n Q2 is around ground at starting point of the write and read cycle because BL line 206 is at ground level during standby, which sets up forward bias between the floating node 204 and the BL line 205. The floating node 204 quickly loses its charge through the forward bias of the diode connection during standby. Now it is easy to think the memory cell with the ground level of the floating node 204. The n-p-n Q2 is always turned off at the starting point of the write and read cycle. The memory cell is controlled by the storage node 203 which is connected to the resistive storage element.
The read circuit 210 in FIG. 2A generates the voltage output (VO). The conventional sense amplifier is replaced with the current sink 212 and the current mirror 213. The switch 211 is turned on when read. The memory cell detects the storage node and sinks the current when the storage element has high resistance (30K ohm˜1M ohm). However it does not sink the current when the storage element has low resistance (0.1K ohm˜3K ohm). More detailed memory operation will be explained as below.
In FIG. 2B, an alternative configuration is illustrated. The diode is consisted of the n-p-n-p, instead of p-n-p-n, wherein the emitter 252 of p-n-p Q1 is connected to the word line (WL) 251, the base 253 of p-n-p Q1 is connected to one side of the resistive storage element 257, the other side of the resistive storage element is connected to the resistor line (RL) 258, the collector 254 of p-n-p Q1 serves as the base of n-p-n Q2, the emitter of n-p-n Q2 is connected to the bit line (BL) 256. The read circuit 260 in FIG. 2B generates the voltage output (VO). The conventional sense amplifier is replaced with the current sink 262 and the current mirror 263. The switch 261 is turned on when read. The signals are moving reversely, compared to p-n-p-n diode as shown in FIG. 2A.
In FIG. 3A, the example array configuration is illustrated in order to explain the write operation. The memory cell 300 and 300′ are selected by the word line 301 which rises from ground to high level, and the resistor line 308 is floated from ground level by the control signal (not shown) before the word line rises. When the word line rises to high level, the selected memory cells are turned on, after then the resistor line 308 will rise from ground to around high level. If the bit line sinks high current and keeps strong ground level, the current path will be sustained. In order to reset the phase change material, the bit line sinks more current with short pulse, and to set the phase change material, the bit line sinks less current with long pulse. The unselected cells are not affected by the selected cells because the access diodes are turned off. More detailed operation will be explained as below (in FIGS. 10A and 10B).
In FIG. 3B, an example array configuration is illustrated in order to explain the read operation. The memory cell 350 and 350′ are selected by the word line 351. Those selected memory cells are turned on by the same procedure of the initial stage of the write cycle. The resistor line 358 keeps ground level during the rising time of the word line 351. After the selected cells are turned on, the resistor line 358 rises to around high level. During the rising of the resistor line 358, the input voltage of the p-n junction between the word line 351 and the storage node is determined, such that the current flow through the resistive storage can not affect the diode current path when the resistance value of the storage element is high, which is the case of the read “1” with high resistance value. The memory cell 350 shows the read “1”. In contrast, when the resistance value of the storage element is low, the current flow through the resistive storage element is much stronger than the base current from the emitter of the diode. As a result, the diode quickly turns off the current path because it can not sustain the forward bias between the emitter (the word line) and the base (the storage node). This is the case of the read “0” with low resistance value. The memory cell 350′ shows the read “0”. The unselected cells are not affected by the selected cells because the access diodes are turned off by lowering the word line.
In FIG. 4A, the detailed read “1” operation is illustrated. To read data “1”, the word line 401 rises from ground to high level. The resistor line 408 is floated by the control circuit (not shown) from ground level before the rising time of the word line. This is one of the circuit techniques to reduce the peak current from the word line (high) to the resistor line (ground). The word line 401 charges the storage node 403, and establishes the forward bias. The base current IBP of p-n-p Q1 is established and the collector current ICP is established as well. The collector current ICP pulls up the base 404 of the n-p-n Q2, which turns on the n-p-n Q2. There are no extra current paths because the resistor line 408 is floating. After the word line 401 establishes the current path of the diode, the resistor line 408 will rise to around high level. If the resistance of the storage element is high, the resistor line does not affect the storage node with weak resistive storage element. Thus the current path is sustained after the resistor line rises to around high level, which is read “1”.
In FIG. 4B, the detailed read “0” operation is illustrated. To read data “0”, the word line 451 rises from ground to high level. The procedure of the establishing forward bias is the same as read “1”. After establishing the current path of the diode, the resistor line 458 rises to around high level. When the resistive storage element stores low resistance, the voltage of storage node 453 is close to the resistor line 458 because the resistor line 458 pulls up the storage node 453 to around high level with low resistor. The established voltage between the emitter 452 and the base 453 is reduced by the resistive element. As a result, the forward bias voltage is reduced, and the voltage reaches below the threshold voltage (built-in voltage). Finally the diode is turned off. This process occurs during the rising time of the resistor line 458. Depending on the characteristics of the phase change material, the high voltage of the resistor line should be optimized. For example, the resistive storage element can be used below 0.6v. Otherwise the storage element can not display any resistive difference. In this case, the resistor line 458 is determined below the word line level, such as VRL=VWL−0.2v, where VRL is the voltage of the high level of the resistor line, VWL is the high level of the word line, where VRL voltage is determined that the phase change material exhibits the resistance difference at lower than 0.6V. This ensures that the resistance of the storage element determines the stored resistance at 0.5v with 0.1v margin, if the forward bias of the diode is 0.6v˜0.7v.
The relation between the current of storage element and the current of diode can be selected as follow, in order to turn off the diode when the stored resistance is low. IM (in FIGS. 4A and 4B) is the current of resistive storage element 457, which current is defined as IM=VM/RS, where the stored resistance RS is fixed after programming such as 3 Kohm, and VM is fixed 0.5v as explained in FIG. 4B, which is much lower than threshold voltage of GST cell. The diode will be fully turned off if the base-emitter current IBP is selected much lower than IM. For example, IBP is determined as one fifth of high current of storage resistance, such that IBP=⅕*IM=33 uA where IM=V/R=0.5v/3 Kohm=167 uA. The current IM (167 uA) can pull up the storage node strongly. In doing so, the storage node moves up and removes the forward bias toward the word line. Consequently, the current path is disappeared after losing the forward bias between the word line and the storage node. The read cycle will not change the GST material by the short current pulse and low voltage. The diode current is carefully selected by the operating voltage (word line voltage), the geometrical size of the shape and the concentration of the diode. All those values can be controllable in the memory design. And the programming pulse width is less than 150 ns. See “Electrothermal and phase-change dynamics in chalcogenide-based memories”, IEDM 2005.
In FIG. 5A, the read timing is illustrated. Before rising of the word line 451, the resistor line 458 is floated by the control circuit, and then the word line 451 rises to high level to read, which establishes the forward bias junction between the word line and the storage node as shown in FIG. 4A and 4B. The word line 451 will charge the floating storage node which is initialized at the ground level. The storage node will be pulled up by the forward bias, but it does not flow any current to the resistor line 458 because it is open. And the resistor line will stay at VDD-VF if the word line is at VDD, and the forward bias voltage is VF. During the charging the storage node, the forward bias voltage eventually establishes the current path from the word line to the bit line. After the word line 451 establishes the current path of the diode, the resistor line 458 is turned on and rises to around high level. During the rising time of the resistor line 458, the forward bias between the word line and the storage node is reduced and reached below the threshold or built-in voltage if the resistance of the storage element is low. As a result, the diode is turned off which is IOFF 456′ in FIG. 5A. In contrast, the diode keeps turn-on state which is ION 456 in FIG. 5A if the resistance of the storage is very high.
In FIG. 5B, the I-V curve of the memory cell is depicted. When reading data “1”, ION current flows through the diode during read cycle. On the contrary, when reading data “0”, the diode does not flow the current, which is IOFF current. And during standby, the word line is at ground level, which does not flow any current through the diode.
In FIG. 6A, the read path of the present invention is illustrated. The replica delays of the read path consecutively enable all the read circuits and finally complete the read cycle. It is important to use replica delays in the whole read path because the read pulse should be very short not to change the phase of the storage element. If the read pulse is very long, the current pulse may change the phase of the storage element. In the read path, there are three replica delays, such as the resistor line enable (RE), the latch enable (LE), and the output enable (OE). The first replica delay circuit 690 generates RE signal which enables the resistor line 658 after the word line 51 transitioned to high level. RE signal is inverted by the inverter 692′. And the inverted output enables the resistor line driver 692 which raises the resistor line 658 to high level. At the same time, RE signal is delayed by the second replica delay circuit 610 which generates LE signal to enable the latch. The third replica delay circuit 630 generates OE signal after LE signal is high. More detailed operation is explained as below.
Referring now FIG. 6B in view of FIG. 6A, the read timing of the present invention is illustrated. To read data, there is a sequence to enable the signals. Non-critical signals are enabled first, such as pre-charge true (PT), pre-charge bar (PB), read (RD) and column decoder output (CDT, COT, COB). Simultaneously, resistor line input (RI) is enabled, but RE signal is still low, which makes the resistor line (RL) floating. After all non-critical signals are ready, and then the word line rises to high level. With replica delay circuits, raising the word line enables the critical read path and finally completes the read cycle. Depending on the array size, the read path delay is determined. The word line (WL) enables the resistor line enable signal (RE), and RE signal enables RL signal, RL signal enables latch enable (LE), LE signal enables to latch data from the memory cell. If the resistive storage element has low resistance, the memory cell does not flow any current. It is shown in 675′ (IBL′) in FIG. 6B. The latch output is the pre-charged value which is controlled by PMOS 677 in the latch circuit 671 where PB signal pre-charges the latch node 678. The latch node 678 sustains the pre-charged value. If the resistive storage element has high resistance, the memory cell sinks the current through NMOS transistor 674. It is shown in IBL in FIG. 6B. The current mirror 675 will repeat the same amount of the current that the NMOS transistor 674 sunk. This realizes that the latch node 678 stores the memory cell data. During this period, the other transistors are disabled, such as COT=H, RD=H, LE=H, COB=H, PB=H, PT=L. The current mirror 675 is much stronger than the pull-up of the inverter 681. After latching data, the data is transferred to the inverter 679 and 680. The output 682 of the inverter 680 turns off the transistor 672, thus the current path is cut off. After the data is latched, OE signal turns on the transmission gate 683 and 684, where OEB signal is inverted from OE signal. The data output is transferred to the data bus 685. Moreover, OE signal finally lowers the word line (WL) as shown. Alternatively, NMOS transistor 674 and the current mirror 675 can be low threshold device in order to reduce operating voltage and make speed fast.
In FIG. 7A, the replica delay circuit for generating RE signal is illustrated. The delay circuit 790 includes the memory cell 791 which can be placed in the main memory cell area or placed in the control circuit area depending on the applications. The replica delay lines are WL, RL and BL. Those signals have similar RC loading to the main array block. After WL line rises to high level, the current path is established through WL line to BL line, which current path is set from WL line to the NMOS transistor 794. The other signals are ready before WL line is asserted, such that CDB=H, CDT=H, RD=H, PT=L, PB=H. The current mirror 795 repeats the amount of current that the memory cell flows. The latch node 797 is flipped by the current mirror 975 because PMOS 796 is turned off and the current mirror 795 is much stronger than the pull-up strength of the inverter 781. The latched output 797 is transferred to the inverter 798 and 780, and the output 782 of the inverter 780 turns off NMOS 792 which cuts off the current path. This can reduce the current consumption. The memory cell 791 is not required to be reset or set because RE signal is generated by the establishing of the current path regardless of the stored value. And RE signal is lowered by the PB and PT signal (PB=L, PT=H).
When the replica circuit is used to generate the delay signal, the delay signal may fail with the memory cell which is fabricated with very tight design rule. In order to avoid this issue, there are two approaches to implement the replica delay circuit. It is to use multiple columns and use OR operation. The latch output 799 and 783 (another replica column) can generate RE signal with OR gate 784. This means that RE signal works even though one of the delay circuits is failed. The another approach is to use similar circuit of the memory cell instead of using the real tight size of the memory cell, which requires usually additional delay for the margin because the delay signal is not exact replica delay. The present invention can be implemented with either way.
Referring now FIG. 7B in view of FIG. 7A, the RE timing of the present invention is illustrated. All the non-critical signals are ready at the time of the rising of PB and RI, such that CDB=H, CDT=H, RD=H, PB=H, PT=L, RI=H. After then, WL signal rises to high level, which WL signal establishes the current path with the forward bias. The current flows through NMOS 794, which current is IDL. The current mirror 795 repeats the current IDL′. The current mirror flips the latch node 797 and generates RE signal. As a result, RE signal rises to high level. And the RE signal is lowered by PMOS 796 when PB=L.
In FIG. 8A, the replica delay circuit for generating LE signal is illustrated. The delay circuit 810 includes the memory cell 811 which can be placed in the memory cell area or placed in the control circuit area depending on the applications. The replica delay lines are WL, RL and BL. Those signals have similar RC loading to the main array block. After RL line rises to high level, the memory cell is turned off by the resistive storage element which is programmed (required) with low resistance value. The current path is removed by the low resistive storage element through WL line to BL line, thus NMOS transistor 814 does not flow current. The other signals are prepared as same as RE delay circuit, and the NMOS 812 is always on. The current mirror 815 will stop to flow the current, which releases the node 816. The PMOS 817 and NMOS 815 consist of the source follower, wherein the PMOS 817 serves as an active load and the NMOS 815 serves as gain stage. Active load 817 receives the bias voltage VBP, hence the PMOS 817 is always turned on, but the strength of the pull-up is weaker than that of the pull-down NMOS 815. When the NMOS 815 is turned on, the output 816 of the source follower is logic “0”. In contrast, when the NMOS 815 is turned off, the output 816 of the source follower is logic “1” because the PMOS 817 pulls up the output node 816. After rising RL signal to high level, the output 816 transitions the output from ground to high level. And then the output 816 is transferred to the OR gate 822 through the wave-shaping inverters 818 and 819. The OR gate can receive multiple output 821 from the multiple replica delay circuits as explained above, in order to avoid the fail of the delay circuit.
Referring now FIG. 8B in view of FIG. 8A, the LE timing of the present invention is illustrated. The latch enable (LE) signal is generated as follow. After RE moved from ground to high level, RL signal is turned on and rises to high level (or slightly lower than high level). RL signal pulls the storage node by the resistive storage element, if the resistance of the storage element is very low, the storage node is very close to the RL level, which level is the lower than the forward bias for the p-n junction between the WL line and the storage node. As a result, the current path is turned off. This makes RLD signal high. The AND gate 823 with RE signal generates the LE signal to enable the latch.
In FIG. 9A, the replica delay circuit for generating OE signal is illustrated. The delay circuit 930 includes the memory cell 931 which can be placed in the memory cell area or placed in the control circuit area depending on the applications. The replica delay lines are WL, RL and BL. Those signals have similar RC loading to the main array block. After LE signal rises to high level, the current mirror 935 will repeat the amount of the current that the memory cell flows if the resistive storage element is programmed (required) high resistance value. The memory cell keeps flowing current after RL signal is at high level because the high resistive storage element can not affect the current flow. As a result, the latch node 938 is flipped by the current mirror 935 because PMOS 937 is turned off and the current mirror 935 is much stronger than the pull-up strength of the inverter 942. The latched output 938 is transferred to inverter 939 and 941. At the same time, the NMOS 932 is turned off by the latched output 943 which can reduce the current consumption. The OE signal is obtained after OR operation by the OR gate 945. The OR gate receives the latched output 940 and 944, where the multiple replica delay circuit may be used to avoid the fail of the OE signal.
Referring now FIG. 9B in view of FIG. 9A, the OE timing of the present invention is illustrated. The output enable (OE) signal is generated as follows. After LE moved from ground to high level, the current mirror repeats the amount of the current that the memory cell flows. As a result, the current mirror pulls down the latch node and generates the OE signal. Simultaneously, the OE signal turns off the current path to reduce the current consumption. And the OE signal turns on the transmission gate of the latch which makes to output the memory cell data to the data bus as shown in FIG. 6A, where OEB is inverted signal of the OE signal. Furthermore, the OE signal makes to complete the read cycle by closing the WL line.
In FIG. 10A, the write path of the present invention is illustrated. The selected memory cell 1050 is connected to the selected bit line 1051. The unselected memory cell 1060 is connected to the unselected bit line 1061 which keeps high level. The unselected memory cell does not flow any current even after WL is at high level. The write driver circuit is illustrated in 1019. Before the WL signal rises to high level to start writing, COT, WT signals are at high level, and the RL signal is floating. The procedure of raising the RL signal is the same as read cycle. The BR signal turns on two NMOS transistor 1053 and 1055, in order to sink more current when the RESET operation is selected. The BS signal turns on one NMOS transistor 1058 to sink SET current. The current sink circuit 1054, 1056 and 1059 are biased by VB which voltage is fixed. However, in some applications, the current sink circuit 1054, 1056 and 1059 may not be used to reduce area. After all signals are ready, the WL signal rises to establish the forward bias to the storage node and set up the current path. In order to write “1”, which is RESET, D1 signal is turned on before the WL signal rises. The current to RESET flows from the RL signal through the resistive storage element. Simultaneously, the word line flows current as well. To reduce the WL current, the WL driver may use the current limiter circuit (not shown). In most of applications, the resistance of the storage element is much higher than on-resistance of n-p-n transistor. In this manner, the applied voltage of the storage node is very close to the bit line which is near ground level, which helps to sustain the current path during write cycle. Alternatively the voltage level of the RL signal can be slightly lower than that of WL signal, in order to ensure the forward bias (or built-in voltage) between the WL line and the storage node during write cycle. After the write condition is set up, the RESET cycle is completed by the BR pulse width. In order to write “0”, which is SET, DO signal is turned on before the WL signal rises. The current to SET flows from the RL signal through the resistive storage element.
Referring now FIG. 10B in view of FIG. 10A, the write timing diagram of the present invention is illustrated. As explained in FIG. 10A, all the non-critical signals are ready before the WL signal rises. In order to write “1”, which is RESET, D1 signal is selected to high and DO is at low as shown in 1062. RESET current IR′ is sunk by the selection of the D1. In order to write “0”, which is SET, DO signal is selected to high and D1 is at low as shown in 1063. SET current IS′ is sunk by the selection of the DO. After writing, the read cycle can be applied to verify the written data (not shown). During RESET, GST material is melted by the short pulse and strong current which is controlled by BR signal as shown in FIG. 10B. Then the phase is changed to amorphous state which has high resistance state, while SET operation has long pulse and weak current which is controlled by BS signal as shown in FIG. 10B, then the phase is changed to crystalline state which has low resistance. There is a report for the pulse width and current during write operation as published. “Enhanced Write Performance of a 64 Mb Phase-Change Random Access Memory”, pp.48, 2005 IEEE International Solid-State Circuits Conference 2005. (For example, RESET operation has t=10 ns, I=600 uA and results in R=100 Kohms. SET operation has t=180 ns, I=200 uA˜400 uA and results in R=1.2 Kohms.)
Methods of Fabrication
Replacing MOS access transistor with a diode access device, the memory cell needs only a p-n-p-n diode (or n-p-n-p diode) and a chalcogenide storage element, which realize various types of memory cell structure, in order to fabricate on the bulk or SOI (Silicon-on-Insulator) wafer. The steps in the process flow should be compatible with the current CMOS manufacturing environment, as the prior arts, such as U.S. Pat. No. 6,891,747, U.S. Pat. No. 6,894,305, and U.S. Pat. No. 7,061,013. In this respect, there is no need of describing too much detailed process flow to form the memory cell, such as width, length, thickness, temperature, forming method or any other material related data. Instead of describing those details, the present invention focuses on illustrating the new memory cell structures which are practical and mass producible.
In FIG. 11A, the cross sectional view of the present invention including a diode access device is illustrated as an example cell structure. The word line 1151 is connected to the p-type region 1152 through the contact region 1161. The p-type region 1152 is attached to the n-type region 1153 which is the storage node and connected to the resistive storage element including the bottom contact 1157, the bottom-electrode-contact 1167, GST material 1177, top electrode 1187 and the resistor line 1158. The n-type region 1153 is attached to the p-type region 1154 as well. The p-type region 1154 is attached to n-type region 1155 and connected to the bit line 1156 through the contact region 1165 and other conduction layers. The memory cell can be isolated from the bulk 1199 by the insulation layer 1198. This cross section is seen from the word line direction.
In FIG. 11B, the cross sectional view is seen from the bit line direction. The n-type region 1153 is trenched on the bulk. Alternatively, the memory cell can be formed on the SOI wafer (not shown). Unlike MOS access device, the diode access device is easily formed because the diode does not require very thin oxide layer for forming gate.
In FIG. 12A, the fully vertical cross sectional view of the present invention including a diode access device is illustrated as an example embodiment. The word line 1251 is formed in the bottom, wherein the word line 1251 is connected to the p-type region 1252 through the contact region. The p-type region 1252 is attached to the n-type region 1253 which is the storage node and connected to the resistive storage element including the bottom contact 1263, the bottom-electrode-contact 1257, GST layer 1267, top electrode 1277 and the resistor line 1258 through conduction region 1268. The n-type region 1253 is attached to p-type region 1254 as shown in FIG. 12B. The p-type region 1254 is attached to n-type region 1255 and connected to the bit line 1256 through the contact region 1266 and other conduction layers. The memory cell can be isolated from the bulk 1299 by the insulation layer 1298. As a result, the memory cell area can be dramatically reduced. However, the cell-to-cell disturbance is more critical with the reduced distance because of the high programming heat. Eventually, there is a need to place cells with zigzag array as shown FIG. 12A. The distance between two adjacent cells will be increased as shown “d1” instead of “d0”. This cross section is seen from the word line direction. In FIG. 12B, the cross sectional view is seen from the bit line direction. In FIG. 12C, the top view of the memory cell is illustrated. And the memory cell can be formed on the substrate of the wafer by adding insulator 1298, or formed on SOI wafer. And the memory cell can be formed on the substrate of the wafer by adding insulator 1298, or formed on SOI wafer. The word line can be tungsten in order to stand the diode process, which diode can be formed from the high temperature polysilicon (HTPS), at 650-1000 Celsius, generally.
Alternatively, the word line can be aluminum or copper (300-500 Celsius), such that the diode access device can be formed from LTPS (Low Temperature Polysilicon), as published, U.S. Pat. No. 5,395,804, U.S. Pat. No. 6,852,577 and U.S. Pat. No. 6,951,793. LTPS has been developed for the low temperature process (500 Celsius or lower) on the glass in order to apply the display panel, according to the prior arts. Now the LTPS can be used as a diode for the memory access device. Generally, polysilicon diode can flow less current than single crystal silicon diode, but the polysilicon diode can flow more current than MOS transistor, because the diode can flow the current through the whole junction while the MOS transistor can flow the current through the shallow inversion layer by the gate electric field. In the present invention, LTPS-based diode is useful to form the diode-based memory cells with no very thin oxide layer, because the memory cell does not include MOS transistor. The metal layer under the diode does not degraded with low temperature process.
While the description here has been given for configuring the memory circuit and structure, alternative embodiments would work equally well with reverse connection such that first terminal is n-type and serves as the word line, the second terminal is the p-type and serves as the storage node, the third terminal is the n-type and floating, and the fourth terminal is the p-type and connected to the bit line.
The foregoing descriptions of specific embodiments of the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to explain the principles and the application of the invention, thereby enabling others skilled in the art to utilize the invention in its various embodiments and modifications according to the particular purpose contemplated. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents.
Patent Application
20070133250
