Claims
- 1. A multilayer pasaivation layer over metal interconnections on a substrate comprised of:
- a patterned metal layer forming metal lines for said metal interconnections on said substrate;
- a multilayer passivation layer on said patterned metal layer comprised of;
- a first silicon oxide layer on said patterned metal layer thereby providing a stress-release layer,
- a first silicon nitride layer on said first silicon oxide layer as a buffer layer to minimize cracking;
- a second silicon oxide layer on said first silicon nitride layer that fills and seals any remaining cracks and pinholes in said first silicon nitride layer;
- a second silicon nitride layer on said second silicon oxide layer that provides a main passivation layer to protect said metal lines from moisture and corrosive chemicals, and said second silicon nitride layer having a thickness of between about 2500 and 5000 Angstroms.
- 2. The structure of claim 1, wherein said first silicon oxide layer has a thickness of between about 200 and 500 Angstroms.
- 3. The structure of claim 1, wherein said first silicon nitride layer has a thickness of between about 200 and 500 Angstroms.
- 4. The structure of claim 1, wherein said second silicon oxide layer has a thickness of between about 500 and 1000 Anqstroms.
Parent Case Info
This is a division of patent application Ser. No. 08/891,910, filing date Jul. 14, 1997, now U.S. Pat. No. 5,851,603 A Method For Making A Plasma-Enhanced Chemical Vapor Deposited Sio.sub.2 /Si.sub.3 N.sub.4 Multilayer Passivation Layer For Semiconductor Applications, assigned to the same assignee as the present invention.
US Referenced Citations (4)
Foreign Referenced Citations (1)
Number |
Date |
Country |
63-028049 |
Feb 1988 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
891910 |
Jul 1997 |
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