Patent Application
20230230954
The present invention relates generally to etching, and more particularly to equipment and process technologies for catalyst influenced chemical etching.
In semiconductor device fabrication, etching refers to any technology that will selectively remove material from a thin film on a substrate (with or without prior structures on its surface) and by this removal create a pattern of that material on the substrate. The pattern may be defined by a mask that is resistant to the etching process. Once the mask is in place, etching of the material that is not protected by the mask can occur, by either wet chemical or by “dry” physical methods.
One type of etching is Catalyst Influenced Chemical Etching (CICE), which is a catalyst-based etching method that can be used to fabricate features in semiconductors, such as silicon, germanium, etc., where such features have high aspect ratios, low sidewall taper, low sidewall roughness, and/or controllable porosity. This method is used to create higher density and higher performance Static Random-Access Memory (SRAM) as well as low-loss waveguides.
Unfortunately, there are currently limitations in fabricating features in semiconductors using CICE.
In one embodiment of the present invention, a system for assembling fields from a source substrate onto a second substrate comprises the source substrate comprising a plurality of fields. The system further comprises a transfer chuck used to pick at least four of the plurality of fields from the source substrate in parallel to be transferred to the second substrate, where relative positions of the at least four of the plurality of fields is predetermined.
In another embodiment of the present invention, a transfer chuck comprises a rectangular array of adaptive chucking modules. The transfer chuck further comprises a variable pitch mechanism configured to change at least one of an X pitch or a Y pitch of the rectangular array of adaptive chucking modules.
In a further embodiment of the present invention, a transfer substrate comprises fields previously picked from a source substrate using a transfer chuck. The transfer substrate further comprises embedded structures that are compliant in a Z-direction.
In another embodiment of the present invention, a method for creating alignment marks in fields during singulation comprises creating the alignment marks in the fields during the singulation using an etching technique, where the etching technique comprises catalyst influenced chemical etching or deep reactive ion etching.
Furthermore, in another embodiment of the present invention, a method for preventing wandering of catalysts during catalyst influenced chemical etch (CICE) comprises providing a semiconducting material. The method further comprises patterning a catalyst on a surface of the semiconducting material, where the catalyst comprises one or more isolated features, where the one or more isolated features comprise a predetermined hole. The method additionally comprises exposing the patterned catalyst to an etchant, where the patterned catalyst and the etchant cause etching of the semiconducting material to form buttresses corresponding to the predetermined hole, where the buttresses prevent wandering of the catalyst during the CICE.
Additionally, in another embodiment of the present invention, a method for fabricating nanostructures comprises performing chemical influencing chemical etching on a polysilicon layer to create silicon structures. The method further comprises depositing one or more structural materials on the silicon structures, where the one or more structural materials are selected to enhance desired device properties. The method additionally comprises creating an access to the silicon structures. Furthermore, the method comprises removing the silicon structures selectively thereby leaving the one or more structural materials substantially the same.
In another embodiment of the present invention, a fluidic device comprises multilayer stacks of silicon micropillar and nanopillar arrays, where the silicon micropillar and nanopillar arrays are made using catalyst influenced chemical etching, and where the multilayer stacks are made by depositing films comprising polysilicon films and etching the polysilicon films using the catalyst influenced chemical etching.
In a further embodiment of the present invention, a method for curving one or more image sensors into spherical shapes comprises pressurizing a front side of the one or more image sensors using a transfer chuck to produce a curvature of the one or more image sensors.
The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the present invention that follows may be better understood. Additional features and advantages of the present invention will be described hereinafter which may form the subject of the claims of the present invention.
A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:
FIGS. 90A90D depict the cross-section views for forming superlattices with tone-reversal CICE and selective growth using the steps described in
As stated in the Background section, in semiconductor device fabrication, etching refers to any technology that will selectively remove material from a thin film on a substrate (with or without prior structures on its surface) and by this removal create a pattern of that material on the substrate. The pattern may be defined by a mask that is resistant to the etching process. Once the mask is in place, etching of the material that is not protected by the mask can occur, by either wet chemical or by “dry” physical methods.
One type of etching is Catalyst Influenced Chemical Etching (CICE), which is a catalyst-based etching method that can be used to fabricate features in semiconductors, such as silicon, germanium, etc., where such features have high aspect ratios, low sidewall taper, low sidewall roughness, and/or controllable porosity. This method is used to create higher density and higher performance Static Random-Access Memory (SRAM) as well as low-loss waveguides.
Unfortunately, there are currently limitations in fabricating features in semiconductors using CICE.
The principles of the present invention provide a means for utilizing the CICE process to effectively fabricate features in semiconductors using the equipment and process technologies for catalyst influenced chemical etching of the present invention.
Referring now to the Figures in detail,
As shown in
Tool 100 further includes a precision pick-and-place module frame 106 supporting short-stroke xy stages 107. Furthermore, as shown in
Furthermore, as shown in
Additionally, as shown in
Furthermore,
In one embodiment, tool 100 for pick-and-place assembly incorporates one or more of the following components: a source substrate chuck 102, a product substrate chuck 104, an intermediate substrate chuck (holds an intermediate substrate) (not shown in
Referring now to
As shown in
In one embodiment, source/product/intermediate substrate chuck 202 includes an optional light source 204 for field release (e.g., fiber-based) via a light path 205. Furthermore, in one embodiment, source/product/intermediate substrate chuck 202 includes an optional imager 206 for in-situ metrology. Additionally, in one embodiment, source/product/intermediate substrate chuck 202 includes an optional light source 207 for thermal actuation, a DMD assembly 208 and another optional light source 209 for field release (e.g., fiber-based).
Furthermore, in one embodiment, source/product/intermediate substrate chuck 202 includes an optional projector 210 to project optical signals as well as another optional imager 211 for in-situ metrology.
Additionally, in one embodiment, source/product/intermediate substrate chuck 202 includes an optional group of thermoelectric coolers 212, an optional transparent, thermally conductive printed circuit board (PCB) 213, and an optional cooling assembly 214 with a transparent covering.
As shown in
Furthermore, as shown in
A further discussion of
In one embodiment, the primary function of the substrate chucks 202 is to hold the source/product/intermediate substrates, respectively, in a thermo-mechanically stable state during field assembly as well as to change the thermo-mechanical state of the substrates in a controlled manner (if needed).
In one embodiment, substrate chucks 202 are constructed using one or more of the following: silicon carbide (SiC), sapphire, fused silica, glass, silicon, flexible substrates (such as polycarbonate, etc.). In one embodiment, the substrate-touching-surfaces of the chuck are coated with a hard material, such as, for instance, one or more of the following: silicon nitride (SiN), silicon carbide (SiC), etc.
In one embodiment, one or more of substrate chucks 202 have transparent portions. The transparent portions (in the relevant spectrum) could allow through-chuck light transmission to facilitate field-release/temporary-bonding from/to the substrates and/or through-chuck metrology. Light-based field-release solutions are commercially available. Light is incident from the underside of substrate chuck 202, or alternatively from the sides, or a combination of the two. In one embodiment, waveguide-based solutions are used to direct light from the side of substrate chuck 202, where the light is incident, to the substrate underside. If the minimum feature size needed in the waveguide substrate is larger than 100 nm, direct write methods could be used for patterning of the substrate (for instance, laser direct writing). If the minimum feature size is smaller than 100 nm, nanoimprint lithography (NIL), along with a limited number of standardized NIL templates, could be used for the patterning. The standard templates could consist of quantized pattern pieces, such as a 1 mm vertical waveguide channel, a 1 mm horizontal waveguide channel, a +90° waveguide channel, a −90° waveguide channel, etc. These could be used to pattern custom waveguide paths from any out-coupling grating 216 to an in-coupling grating 217. In one embodiment, in-coupling gratings 217 are placed at a location on the periphery that satisfies the quantized X and Y separation constraints imposed by the quantized waveguide pieces. In another embodiment, an addressable UV LED array is used for field release from source substrate 103.
In one embodiment, one or more of the substrate chucks 202 incorporate metrology modules (e.g., metrology module 108) to allow in-situ metrology.
In one embodiment, one or more of the substrate chucks 202 have thermal actuators, embedded or otherwise. Thermal actuators could be used to control one or more of the following: temperature on the source/product/intermediate substrates, field distortion, and field topography. In one embodiment, thermal actuation could be performed using an array of thermoelectric coolers (TEC). A heat exchanger could be utilized to exchange heat with the thermal actuators. In one embodiment, the heat exchanger uses a liquid, such as water, as the working fluid. In one embodiment, the thermal actuators are mounted on a thermally conductive printed circuit board 213. In one embodiment, printed circuit board 213 is transparent.
In another embodiment, thermal actuation is performed using incident spatially modulated radiation that is absorbed by the source/product/intermediate substrates, for instance, using one or more digital micromirror devices (DMDs). The radiation could incorporate one or more of the following: Short Wavelength Infrared Radiation (SWIR), Middle Wavelength Infrared Radiation (MWIR), and Long Wavelength Infrared Radiation (LWIR).
In one embodiment, one or more of the substrate chucks 202 are inert to source substrate sacrificial layer etchants. In another embodiment, one or more of the chucks 202 could be coated with a material that is inert to sacrificial layer etchants, for instance, PTFE, high-density polyethylene (HDPE), etc.
In one embodiment, one or more of the source substrate chucks 102 are mounted on a motion stage. In one embodiment, one or more of the source substrate chucks 102 are mounted on a motion stage that moves independently of other stages in an n-MASC tool (tool for nanometer-scale modular assembly of semiconductor chiplets).
In one embodiment, the n-MASC tool incorporates multiple substrate chucks 202 for simultaneous handling and/or processing of multiple source/product/intermediate substrates, each of which might be independently movable.
Referring now to
As shown in
A cross-section view of transfer chuck (TC) 111 is shown in
Referring to
In one embodiment, TC 111 includes heat exchanger fluid 403 and a thermally conductive printed circuit board 404. Furthermore, in one embodiment, TC 111 includes a heat exchanger layer 405 and a thermal actuator layer 406 which may contain thermoelectric coolers 407. Additionally, in one embodiment, TC 111 includes an xy actuator layer 408. In one embodiment, xy actuator layer 408 is comprised of stainless steel. In one embodiment, xy actuator layer 408 has a thickness of 5 mm. A top view of such an xy actuator layer 408 is shown in
Referring to
Returning to
An illustration of the top view of the pneumatic valve layer 412 is shown in
A further illustration of an alternative top view of the pneumatic value layer 412 is shown in
Returning to
Additionally, in one embodiment, TC 111 includes a pressure manifold layer 425 for field bowing. In one embodiment, layer 425 has a thickness of 0.3 mm. In one embodiment, pressure manifold layer 425 includes an optional pressure line 426.
Furthermore, in one embodiment, TC 111 includes a vacuum suction layer 427. In one embodiment, vacuum suction layer 427 has a thickness of 0.3 mm.
Additionally,
Furthermore, as shown in
Additionally, as shown in
Referring now to
As shown in
As shown in
In one embodiment, TC 111 has no vacuum supply in regions where fields will not be assembled, such as shown at element 506.
In one embodiment, primary and secondary vacuum manifolds 503, 504 are optionally designed in a manner such that the pins do not interfere with the waveguide multilayer memory (WMM) beam paths, such as shown at element 507.
Furthermore, in one embodiment, TC 111 includes a vacuum section 508 in secondary vacuum manifold 504 that holds the fields to the manifold pins.
Additionally,
In one embodiment, secondary vacuum manifold 504 is fabricated from a standard silicon substrate. In one embodiment, primary vacuum manifold 503 is fabricated using thick silicon substrates to provide added structural strength against sagging to gravity.
Referring now to
As shown in
An expanded view of a portion of top metal layer 601 is shown in
A discussion regarding
The primary function of TC 111 is to pick-up/place one or more fields from/onto the source/product/intermediate substrates in a thermo-mechanically stable manner as well as to change the thermo-mechanical state of the fields in a controlled manner (if needed).
In one embodiment, one or more of the TCs 111 are constructed using one or more of the following: silicon carbide (SiC), sapphire, fused silica, glass, silicon, flexible substrates (such as polycarbonate, etc.). In one embodiment, the substrate-touching-surfaces of one or more of the TCs 111 are coated with a hard material (e.g., silicon nitride (SiN), silicon carbide (SiC), etc.).
In one embodiment, one or more of the TCs 111 have transparent portions. The transparent portions (in the relevant spectrum) could allow through-TC light transmission to facilitate field-release/temporary-bonding from/to the substrates and/or through-TC metrology. Light could be incident from the underside of the substrate chuck, or alternatively from the sides, or a combination of the two. In one embodiment, waveguide-based solutions are used to direct light from the side of the substrate chuck, where the light is incident, to the substrate underside.
In one embodiment, the chuck, such as TC 111, incorporates one or more metal layers, such as metal layer 601. The metal layer, such as metal layer 601, could be used to provide structural stability to TC 111. The metal layer, such as metal layer 601, could be machined using macro-machining techniques (e.g., computerized numerical control (CNC) machining). In one embodiment, the metal layer, such as metal layer 601, is made of a high thermal expansion material. In one embodiment, the metal layer, such as metal layer 601, is made of a low thermal conductivity material. In one embodiment, the metal layer, such as metal layer 601, is made using stainless steel.
In one embodiment, TC 111 incorporates a thick substrate (e.g., thick silicon, thick sapphire), of 0.775 mm thickness or more. The thick substrate could be used to provide structural stability to TC 111.
In one embodiment, TC 111 incorporates layers to facilitate bonding of various TC layers (e.g., chrome thin film, polymer films, adhesive polymer films, etc.).
In one embodiment, TC 111 incorporates layers to prevent contamination of n-MASC tool components (including TC sub-components) by the sacrificial layer etchant (e.g., chrome thin film, polymer films, adhesive polymer films, etc.).
In one embodiment, the multiple layers which constitute TC 111 are joined together using one or more of the following: anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, an adhesive, etc.
In one embodiment, TC 111 utilizes vacuum suction to hold fields 401. In one embodiment, TC 111 incorporates integrated valve assemblies to turn on and off the vacuum suction for individual picked fields. TC 111 could also incorporate integrated valve assemblies to turn on and off a pressure source corresponding to individual picked fields. The pressure source could be utilized to create a thin fluidic lubricating layer just prior to field pickup or field bonding. Holes and recesses needed for enabling vacuum and pressure supply to the picked fields could be created using deep etching processes, such as Metal-assisted Chemical Etching (MACE), Deep Reactive Ion Etching (DRIE), etc. Furthermore, TC 111 utilizes flexure mechanisms machined into one or more of the TC layers to source the pressure and vacuum from the movable parts of TC 111 to the fixed parts of TC 111.
In one embodiment, the valve assembly (to turn pressure/vacuum on and off) consists of a hole in TC 111, a flexible membrane (made of a polymer, for instance), a membrane actuation mechanism (for instance, a voice coil along with a magnetically sensitive material deposited or attached to the flexible membrane), a relay (using a transistor, for instance) to turn the actuation mechanism on and off. In one embodiment, the actuation mechanism utilizes thermal expansion.
In one embodiment, TC 111 incorporates porous layers to create vacuum suction on fields 401. In one embodiment, TC 111 incorporates a layer with hybrid porous and non-porous structures to create vacuum suction on fields 401.
In one embodiment, TC 111 uses electrostatic force to hold fields 401. In one embodiment, TC 111 uses Johnsen-Rahbek-type electrostatic chucking to hold fields 401 only where they contact TC 111. In one embodiment, the chucking mechanism incorporates an array of switches to modulate the electrostatic holding force. In one embodiment, the array of switches is addressed using a multiplexer electronic circuit.
In one embodiment, TC 111 utilizes an adhesive to hold fields 401. In one embodiment, TC 111 utilizes UV-release glue to hold fields 401.
In one embodiment, TC 111 contacts fields 401 using an array of pins, such as pins 428. The pin could be in the shape of a truncated frustum. The pins could have one or more holes through which vacuum or pressure is sourced. In another embodiment, TC 111 contacts fields 401 using an array of rings. The ring regions could include one or more holes to source vacuum or pressure.
In one embodiment, the pins, such as pins 428, are compliant in the z-axis.
In one embodiment, the TC contact surfaces are polished post-assembly of TC 111. Any recesses in the TC layers could be filled with fluid-etchable layers, such as silicon oxide (which is etchable using vapor HF). The fluid-etchable layers could be etched away post-polishing.
In one embodiment, TC 111 incorporates integrated mechanical actuators (e.g., one or more piezoelectric actuators, thermal actuators, electrostatic actuators, etc.) to perform actuation in the X, Y, and/or theta axes, for one or more of the picked fields 401. In one embodiment, TC 111 incorporates flexure layers to facilitate in-plane motion of fields 401 as well as specific portions of TC 111. In one embodiment, thermal actuators are used to perform said in-place motion by suitable heating and cooling of the flexure arms. Thermal actuation of the flexure arms may be produced using an array of thermoelectric elements. In one embodiment, the thermoelectric elements are used to transfer heat to the flexures using an array of flexible pillars. Alternatively, thermoelectric elements are used to transfer heat to the flexures using a thin, low coefficient-of-friction material (e.g., a thin film of polytetrafluoroethylene (PTFE), a thin film of a thermally conductive paste, etc.). In another embodiment, thermal actuation of the flexure arms is performed using spatially modulated radiation that is absorbed by the flexure arms, such as by using one or more digital micromirror devices (DMDs). In one embodiment, piezoelectric transducers are placed areally around fields 401 (that are arranged in a checkerboard arrangement) to perform in-plane actuation of fields 401. In one embodiment, thermal actuation is performed in a timed manner, where, at a certain time ta after the start of thermal actuation, and for a duration Δta, desired control is maintained.
In one embodiment, the integrated mechanical actuators, described above, are used to correct one or more components of the first-order overlay errors. In one embodiment, the integrated mechanical actuators, described above, are used to correct one or more components of the higher-order overlay errors.
In one embodiment, TC 111 incorporates pressurize-able regions to create a bow in fields 401 just prior to bonding. In one embodiment, TC 111 incorporates pressurize-able regions to actuate fields 401 in the z-axis.
In one embodiment, TC 111 incorporates one or more heat exchanger layers, such as heat exchanger layer 405, to transport excess heat or cold away from TC 111.
In one embodiment, TC 111 incorporates one or more layers which incorporate flexures which are constrained to move in the z-axis. The flexures could have a motion range of 10 μm or more. In one embodiment, the flexures are actuated using thermal actuators, piezoelectric actuators, and/or pneumatic actuators.
In one embodiment, the thickness variation of fields 401 is actively sensed. In one embodiment, the thickness variation of fields 401 is sensed using air gages.
In one embodiment, TC 111 has optically clear pathways to allow in-situ metrology through TC 111. In one embodiment, TC 111 has optically clear pathways for infrared radiation.
In one embodiment, one or more custom TCs 111 are used for every new field design, with the TC actuator grid (defined by the array of repeating actuator groups, where each actuator group is used to actuate a single field of default dimensions) matched to the field dimensions. In one embodiment, custom TCs 111 could be swapped using a robot arm and lift pins.
In one embodiment, TCs 111 with a fixed grid (corresponding to a default field dimension) are adapted to assemble fields of varying dimensions. An algorithm to achieve this is described below—
One such labelling is shown in
In one embodiment, TC 111 is held using a structural member in the form of a thin ring that contacts TC 111 in an annular region that is etched into the sides of TC 111.
In one embodiment, sacrificial layer etchants are sourced through TC 111 through holes in the etchant-inert part of TC 111. In one embodiment, sacrificial layer etchants are sourced through the parts of TC 111 that are made from silicon.
The following discussion is based on
In one embodiment, a cascade of TCs 111 is used to transfer fields from source substrate 103 to product substrate 105. One or more TCs 111 pick up a subset of fields 401 from source substrate 103 and transfer them (in a field-by-field manner, for instance) to an intermediate substrate 801, while ensuring that the pitch of the fields along the X axis, as well as the pitch of the fields along the Y axis, matches the corresponding X and Y pitch of fields 401 in product substrate 105. In one embodiment, one or more TCs 111 are used to flip the orientation of a subset of fields 401 from source substrate 103 or one of the intermediate substrates 801 such that the correct side required for bonding faces product substrate 105. In one embodiment, one or more TCs 111 perform overlay control and hybrid bonding for the subset of fields 401 being assembled onto product substrate 105.
In another embodiment, a cascade of TCs 111 is used to transfer fields 401 from source substrate 103 to product substrate 105. One or more TCs 111 pick up a subset of fields 401 from source substrate 103 and transfer them in a column-by-column manner to an intermediate substrate 801 while ensuring that the pitch of the fields along the X axis matches the pitch of fields 401 in product substrate 105. In one embodiment, one or more TCs 111 that pick up a subset of fields 401 from intermediate substrate 801 and transfer them in a row-by-row manner to a different intermediate substrate 801 while ensuring that the pitch of the fields along the Y axis matches the pitch of fields 401 on product substrate 105. In one embodiment, one or more TCs 111 are used to flip the orientation of a subset of fields 401 from source substrate 103 or one of the intermediate substrates 801 such that the correct side required for bonding faces product substrate 105. In one embodiment, one or more TCs 111 perform overlay control and hybrid bonding for the subset of fields 401 being assembled onto product substrate 105.
In one embodiment, intermediate substrates 801 are made from silicon, silicon oxide, glass, polymers (such as polycarbonate), and/or sapphire. In one embodiment, intermediate substrates 801 have metrology marks embedded inside. In one embodiment, the metrology marks in intermediate substrates 801 are utilized to align fields to a known precise grid.
In one embodiment, source substrate 103 consists of singulated fields on a dicing tape frame. In one embodiment, intermediate substrate 801 consists of a glass substrate with embedded alignment marks. In one embodiment, temporary bonding onto intermediate substrate 801 is performed using inkjetted UV-curable adhesive. Furthermore, in one embodiment, final bonding is between fields 401 attached to intermediate substrate 801 and product substrate 105.
In one embodiment, TC 111 is geometrically bounded by a cylinder with a diameter of 300 mm. In another embodiment, TC 111 is geometrically bounded by a cuboid. In one embodiment, TC 111 is bounded by a cuboid two sides of which are larger than 300 mm.
Furthermore, as shown in
Additionally,
Furthermore,
Such fields 401 of product substrates 105 are bonded forming the assembled product substrate 105 as shown via element 806.
Referring now to
As shown in
In one embodiment, multiple TCs 111 are used in parallel to assemble fields 401 (e.g., dies 901), where each TC 111 can pick-up, overlay and bond one or more fields 401. In one embodiment, multiple TCs 111 are used in parallel to assemble fields 401, where each TC 111 can pick-up, overlay and bond one field.
Referring now to
As shown in
Furthermore,
Additionally,
In one embodiment, a TC 111 with a reconfiguring actuation grid is used. In one embodiment, the reconfiguring mechanism is fabricated monolithically. In one embodiment, the reconfiguring arrangement is constructed by stacking one or more layers, each of which is monolithically fabricated. In one embodiment, the reconfiguring mechanism is made using bulk metal, bulk polymer, thin coatings, etc. or any combination thereof. In one embodiment, the reconfiguring mechanism is made using steel, stainless steel, chrome, etc. or any combination thereof. In one embodiment, the reconfiguring mechanism consists of flexure elements. In one embodiment, the flexure elements are arranged so as to form scissor mechanisms between each pair of actuation units 1007. In one embodiment, separate reconfiguring mechanisms are utilized for expansion along the X and Y directions. These mechanisms could be stacked on top of each other. Each mechanism could be actuatable in one direction while being free to move in the orthogonal direction. In one embodiment, the actuation of the reconfiguring mechanism is produced using actuators (e.g., voice coil motors, piezoelectric actuators, thermal actuators, etc.) placed at one or more locations on or within the periphery of the reconfiguring mechanism. In one embodiment, the actuators are placed on the axes of symmetry of the reconfiguring mechanism. In one embodiment, each actuation unit 1007 is moved in X and/or Y using or more dedicated actuators. In one embodiment, groups of one or more actuation units are moved in X and/or Y using groups of one or more actuators. In one embodiment, the reconfiguring mechanism rests on fluidic bearings. In one embodiment, the reconfiguring mechanism could be stepped and/or scanned across the relevant substrate. In one embodiment, the reconfiguring grid is in the shape of a rectangle, the shorter arm of which is smaller than the size of the source/product/intermediate substrates. In one embodiment, the reconfiguring grid is in the shape of a single horizontal or vertical line of actuation units.
In one embodiment, the TC actuation units 1007 are attached to a plate such that the pitch of actuation units 1007 is an integer multiple of the field pitch on the source/product/intermediate substrates 103/105/801. The plate could be custom fabricated for each new field layout. The plate could have recesses, or slots, to position actuation units 1007. In one embodiment, the plate has alignment features (pins, for instance) to align actuation units 1007 in the X, Y, Z, θX, θY, and/or θZ axes. In one embodiment, actuation units 1007 are attached to the plate using an adhesive, flexure-based snap-in mechanisms, magnets, electromagnets, vacuum, etc. or any combination thereof.
Referring now to
As shown in
Additionally, as shown in
As shown in
Furthermore, as shown in
Additionally, as shown in
Furthermore, as shown in
As shown in
In one embodiment, bottom part 1302 of TC 111 (that contacts with the picked dies) remains fixed. Furthermore,
Furthermore,
In one embodiment, top part 1301 of TC 111 could be brought back to its default un-clogged state using a piranha clean, UV-based cleaning, etc. If the cleaning process is slow, multiple TCs 111 could be used.
Referring to
In one embodiment, the suction-creating layer on TC 111 (that touches the picked field) could be custom fabricated to match the grid of the picked fields 401. The custom suction-creating layer could be attached to the rest of TC 111 using vacuum suction, adhesive(s), electrostatic forces, magnetic forces, electromagnetic forces, etc. or any combination thereof.
In one embodiment, plasma producing units, such as plasma units 110, are utilized to clean the bonding surfaces immediately prior to bonding.
In one embodiment, plasma producing units, such as plasma units 110, operate at atmospheric pressure. In one embodiment, such plasma producing units are produced by Surfx® Technologies.
In one embodiment, plasma units, such as plasma units 110, cover the area of the entire source/product/intermediate substrates 103/105, 801.
In one embodiment, plasma units, such as plasma units 110, are scanned over the area of the source/product/intermediate substrates 103/105/801. Plasma units, such as plasma units 110, could be mounted on motion stages that can travel along the X axis, Y axis, and/or Z axis.
In one embodiment, plasma units, such as plasma units 110, are mounted on a retractable plate that retracts out of the way of fields 401 once plasma treatment is completed.
In one embodiment, plasma units, such as plasma units 110, face upwards to treat downward facing fields 401.
In one embodiment, plasma units, such as plasma units 110, face downwards to treat upward facing fields 401.
In one embodiment, the upward and downward facing plasma heads are synchronized such that as the upward facing units treat the downward facing fields 401, the downward facing units treat the upward facing fields 401.
In one embodiment, multiple source/product/intermediate substrates 103/105/801 are plasma treated in a separate chamber of the n-MASC tool.
Referring now to
As shown in
Furthermore, as shown in
In one embodiment, metrology module 108 corresponds to a full reconfigurable array of imagers 1401 that is 300 mm×300 mm.
In one embodiment, the exemplary field 401 has a horizontal length of 25 mm and a vertical length of 30 mm. In one embodiment, field 401 has up to 8 total alignment marks (4 for X and 4 for Y alignment). Furthermore, field 401 may have alignment marks in layer 0 or half-kerf.
In one embodiment, imager 1401 consists of a short-wave infrared (SWIR) sensor (e.g., Sony® IMX990-AABJ-C). In one embodiment, there are about 130 such sensors in metrology module 108.
In one embodiment, an exemplary Y-scan for metrology module 108 travels about 300 mm. In one embodiment, an exemplary X-scan for metrology module 108 travels about 190 mm.
Referring now to
As shown in
Furthermore, as shown in
In one embodiment, an exemplary Y-scan for metrology module 108 travels about 500 mm. In one embodiment, an exemplary X-scan for metrology module 108 travels about 3×190 mm (i.e., performs an X-scan of metrology module 108 that travels 190 mm 3 separate times).
As shown in
Furthermore, as shown in
Furthermore,
Additionally,
In one embodiment, the exemplar field 401 has a horizontal length of 20 mm and a vertical length of 20 mm. In one embodiment, field 401 has up to 8 total alignment marks (4 for X and 4 for Y alignment).
In one embodiment, imager 1401 consists of a short-wave infrared (SWIR) sensor (e.g., Sony® IMX990-AABJ-C). In one embodiment, there are about 20 such sensors in metrology module 108.
In one embodiment, metrology module 108 corresponds to a full reconfigurable array of imagers 1401 that is 300 mm×300 mm.
Referring now to
Furthermore,
Referring now to
As shown in
Furthermore, telecentric focusing optics 1803 are utilized. In one embodiment, such optics 1803 include a numerical aperture of about 0.2, a resolution at 1.4 μm of about 4.2 μm, a depth-of-field at 1.4 μm of about 20 μm and a magnification of 1×.
Additionally,
Furthermore,
If the alignment marks are patterned on layer 0, or in the inter-die kerf (in the case when an entire field composed of multiple dies is picked up), full kerf width could potentially be available for creating alignment marks.
Alternatively, a MAC-based dicing technique could be used to create micrometer-scale-thick kerf cuts with sharp corners. This could allow most of the kerf region that was previously unavailable to be used for alignment mark placement.
The detection precision using imaging-based marks (assuming 5 μm SWIR pixel pitch and 1/10 sub-pixel detection) is approximately 0.5 μm. However, the detection precision using moiré marks (assuming ρ1, ρ2=3, 3.05 μm, 1/10 sub-pixel detection) is approximately 8 nm. Furthermore, the moiré phase-unambiguous capture range is approximately 1.5 μm,
Furthermore,
Additionally,
Furthermore,
If the alignment marks are patterned on layer 0, or in the inter-die kerf (in the case when an entire field composed of multiple dies is picked up), full kerf width could potentially be available for creating alignment marks.
Alternatively, a MAC-based dicing technique could be used to create micrometer-scale-thick kerf cuts with sharp corners. This could allow most of the kerf region that was previously unavailable to be used for alignment mark placement.
Furthermore, in such an embodiment, the detection precision using imaging-based marks (assuming 1 μm SWIR pixel pitch and 1/20 sub-pixel detection) is approximately 90 nm.
Furthermore,
Referring to
Furthermore,
It is noted that
As shown in
Furthermore, as shown in
As shown in
In one embodiment, diffractive elements at the locations identified by element 2404 couple light into and out of light guides at specified angles. Photonic light guides 2405 patterned into ATC 1101 could be fabricated in a custom layer which is attached to the rest of ATC 1101 using adhesive, vacuum, electromagnetic force, magnetic force, electrostatic force, etc. or any combinations thereof.
In one embodiment, photonic light guides 2405 guides the light onto picked fields 2406 on ATC 1101 at the moiré plane 2008.
Referring to
Referring to
In one embodiment, metrology module 108 conducts measurements on all fields 401 on TC 111 simultaneously.
In one embodiment, metrology module 108 incorporates one or more imager units 1401. In one embodiment, imager units 1401 are sensitive to visible radiation, infrared radiation, short-wavelength infrared radiation (SWIR), etc.
In one embodiment, one or more light sources 2402 are used to illuminate the metrology targets. In one embodiment, light source 2402 incorporates light emitting diodes (LED), laser diodes, fiber guided light sources, vertical-cavity surface-emitting lasers (VCSELs), etc. or any combination thereof. Alternatively, edge-lighting could be used as light source 2402 for the metrology, where the light is injected from the sides of an edge-lighting substrate and transported to the relevant regions using photonic crystal-based light guiding, for instance. In one embodiment, light sources 2402 are mounted on a printed circuit board. In one embodiment, light sources 2402 are mounted adjacent to imager units 1401. In one embodiment, light source 2402 sends light towards the metrology targets at an angle using an off-axis lens. Alternatively, light source 2402 sends light towards the metrology target at an angle using one or more mirrors. The mirror assembly could be constructed using reflective blaze gratings. The blaze gratings could be coated with a metal. The blaze gratings could be manufactured on silicon, sapphire, silicon oxide, glass, and/or polymer substrates. In one embodiment, the light from light source 2402 is incident at the Littrow angle 2306. In another embodiment, the light from light source 2402 is incident at an angle such that one of the first diffracted orders from the metrology marks returns towards imagers 1401 along the field normal direction.
In one embodiment, imager units 1401 are mounted on a printed circuit board. In one embodiment, light sources 2402 are mounted on a printed circuit board. In one embodiment, imager units 1401 and light sources 2402 are mounted together on a printed circuit board. In one embodiment, light sources 2402 and imager units 1401 mounted on the printed circuit board are optically isolated using a dark machined frame. In one embodiment, the printed circuit board is thermally conductive.
In one embodiment, an array of lenses patterned on silicon, sapphire, glass, silicon oxide, and/or polymer substrates are utilized to direct light from light source 2402 onto the metrology marks and focus light from the metrology marks onto the imager array. In one embodiment, the lens array incorporates annular lens-like regions etched into the lens array substrate. In one embodiment, the lens array incorporates a group of concentric metal annuli. Alternatively, the lens array incorporates meta-lenses that are made out of etched substrate, metal, and high refractive index materials, such as titanium oxide. In one embodiment, the lens arrays form telecentric couples for focusing light onto the imager array.
In one embodiment, the metrology scheme is based on the principle of moiré-based spatial phase sensing. In one embodiment, the metrology scheme is based on on-axis moiré metrology. In one embodiment, the metrology scheme is based on circular moiré metrology. In one embodiment, purely imaging-based metrology is utilized (e.g., box-in-box alignment mark metrology). In one embodiment, a focus variation system is utilized to maintain focus at two or more different planes during metrology. Focus variation could, for instance, be achieved using a zoom lens. In one embodiment, one or more of the methods mentioned in this paragraph are utilized concurrently.
In one embodiment, metrology is performed in a reflective mode, where light source 2402 is on the same side of the metrology marks as imager units 1401. In another embodiment, metrology is performed in a transmissive mode, where light source 2402 is on the opposite side of imager units 1401.
In one embodiment, the metrology scheme uses visible light. In one embodiment, the metrology scheme uses infrared light.
In one embodiment, de-magnifying optics is used to observe a substrate area larger than the size of imager units 1401. In another embodiment, magnifying optics are used to observe a substrate area smaller than the size of imager units 1401. In one embodiment, sub-pixel edge-detection techniques are used to detect edges in the metrology signal.
In one embodiment, metrology module 108 is placed on a motion stage that moves in the X, Y, and/or Z axes. In one embodiment, metrology module 108 captures information from all fields currently being assembled by stepping and/or scanning by appropriate amounts along the X, Y, and/or Z axes.
In one embodiment, metrology marks are placed near one or more corners of fields 401 being assembled. Fields 401 could be free of circuit elements in the layers above and below the metrology marks. In one embodiment, metrology marks are placed in the kerf region of fields 401. In one embodiment, field 401 consists of two or more dies, each of which is separated from one another by a kerf region, and this inter-die kerf region contains one or more alignment marks.
In one embodiment, metrology is conducted in real-time as fields 401 are being bonded onto product substrate 105. In another embodiment, metrology is conducted prior to the bonding occurring. In one embodiment, a feedforward model is utilized to correct the repeatable components of field distortions.
In one embodiment, metrology module 108 measures alignment between fields 401 picked up by TC 111, where TC 111 has embedded alignment marks that match the field grid. Metrology module 108 could subsequently align TC 111 to product substrate 105 using metrology marks placed near the edge region and/or the kerf regions of TC 111 and product substrate 105. In one embodiment, real-time topography mapping of the picked fields 401 and product substrate 105 is performed, and the predicted error compensated for by overlay control actuators (thermal actuators, for instance). In one embodiment, a single topography measurement is performed on each field 401. The topography mapping could be performed using air gages (for instance). The array of air gages could be installed next to PCB 213, for instance. Air curtains could also be used to cool product substrate 105 and the picked fields 401 in case PCB 213 heats them up to a significant extent.
In one embodiment, on-axis alignment methods are used in metrology module 108.
In one embodiment, TC 111 has gratings attached and/or patterned on it to track XY displacement with high accuracy.
In one embodiment, alignment marks are placed on fields 401 within the half-kerf region (as shown in
In one embodiment, very large sensors are used for alignment detection in metrology module 108.
In one embodiment, photonic crystal-based light guiding techniques are used to illuminate the alignment marks at the correct angle and location.
In one embodiment, local data processors are associated and placed in close proximity to one or more of the image sensors 1401. These data processors could be used to perform sensor-local image processing. In one embodiment, the data processing is fabricated as part of image sensor 1401 (an in-sensor computer).
In one embodiment, a fixed grid of image sensors 1401 is used. In one embodiment, image sensors 1401 are arranged in a linear array, a staircase-type array, or a combination of the two. In one embodiment, image sensors 1401 are arranged such that the region of the substrate captured by one of the sensors overlaps with the region of the substrate captured by the next nearest image sensor 1401, such that the entire array of sensors captures a continuous and uninterrupted swath of the substrate. In one embodiment, image sensors 1401 contain a light sensitive area surrounding a light insensitive area. In one embodiment, light sources 2402 are mounted in this light insensitive area, at an angle if required, and encased on the sides in an opaque covering (to prevent contamination of the sensor with stray light). Light from light source 2402 is passed through focusing optics 2303 and is incident towards the metrology plane. Light source 2402 is designed such that the depth of the beam (along the Z axis) is the same as the depth of image sensor 1401. If the incident light lands upon overlaid metrology marks, light is reflected in the direction normal to the substrate towards image sensors 1401. The light incident towards image sensors 1401 from the metrology mark plane is focused onto the sensors using 1× magnification low-numerical-aperture optics. The sensor array is scanned in the X direction (see
In one embodiment, a reconfiguring arrangement of image sensors 1401 is used. In one embodiment, the reconfiguring arrangement is fabricated monolithically. In one embodiment, the reconfiguring arrangement is constructed by stacking one or more layers, each of which is monolithically fabricated. In one embodiment, the reconfiguring arrangement is made using bulk metal, bulk polymer, thin coatings, etc. In one embodiment, the reconfiguring arrangement is made using steel, stainless steel, chrome, etc. In one embodiment, the reconfiguring arrangement consists of flexure elements. In one embodiment, the flexure elements are arranged so as to form scissor mechanisms between each pair of image sensors. In one embodiment, separate reconfiguring arrangements are utilized for reconfiguring along the X and Y directions. These arrangements could be stacked on top of each other. Each arrangement could be actuatable in one direction while being free to move in the orthogonal direction. In one embodiment, the actuation of the reconfiguring arrangement is produced using actuators (e.g., voice coil motors, piezoelectric actuators, thermal actuators, etc.) placed at one or more locations on or within the periphery of the reconfiguring arrangements. In one embodiment, the actuators are placed on the axes of symmetry of the reconfiguring arrangement. In one embodiment, each sensor is moved in the X and/or Y direction using one or more dedicated actuators. In one embodiment, groups of sensors are moved in the X and/or Y direction using groups of actuators. In one embodiment, the reconfiguring arrangement rests on fluidic bearings. In one embodiment, the reconfiguring arrangement could be stepped and/or scanned across TC 111. In one embodiment, the reconfiguring arrangement is in the shape of a rectangle, the shorter arm of which is smaller than the size of the source/product/intermediate substrates 103/105/801. In one embodiment, the reconfiguring arrangement is in the shape of a single horizontal or vertical line of sensors.
In one embodiment, image sensors 1401 are attached to a plate such that the pitch of image sensors 1401 is an integer multiple of the field pitch on the TC(s)/source/product/intermediate substrates (111/103/105/801). The plate could be custom fabricated for each new field layout. The plate could have recesses, or slots, to position image sensors 1401. The plate could have alignment features (pins 1104, for instance) to align image sensors 1401 in the X, Y, Z, θX, θY, and/or θZ axes. Image sensors 1401 are attached to the plate using an adhesive, flexure-based snap-in mechanisms, magnets, electromagnets, vacuum, etc.
In one embodiment, metrology module 108 is separated from the rest of the pick-and-place tool using a transparent window. In one embodiment, metrology module 108 is placed behind a transparent window such that there is no mass transfer between metrology module 108 and the rest of the pick-and-place tool. In one embodiment, metrology module 108 is placed in a hermetically sealed chamber with a transparent window facing TC 111. In one embodiment, the hermetically sealed chamber has a door to take out and/or put in metrology module 108.
In one embodiment, the topography (as well as the registration of fields 401 to a known grid) on product substrate 105 is measured prior to the attachment of picked fields 401 onto one or more intermediate substrates. In one embodiment, the topography of picked fields 401 on TC 111 (as well as the registration of picked fields 401 to a known grid) is measured prior to the attachment of fields 401 onto one or more intermediate substrates. In one embodiment, the measured topography and registration information on product substrate 105 and picked fields 401 on TC 111 is utilized to actuate picked fields 401, and partially or wholly compensate for the overlay error which would result if the final bonding step onto product substrate 105 (intermediate substrate to product substrate bonding) was uncompensated. The prediction of the overlay error based on topography and registration data could be conducted using mechanical modeling techniques. In one embodiment, the temperature of fields 401 on TC 111, as well as the temperature of product substrate 105, are maintained within a small window (e.g., 10 mK, for instance). In one embodiment, a single topography measurement is performed on each field 401 on TC 111 and product substrate 105. The topography mapping could be performed using air gages (for instance).
In one embodiment, groups of image sensors 1401 (consisting of one or more image sensors 1401) use a dedicated and/or local data processor to process the entire or a portion of the image processing pipeline used to determine the metrology output (e.g., overlay, alignment, topography, etc.) from the captured images. In one embodiment, the data processor is a single-board computer.
In one embodiment, custom light paths (that transport light incident from light sources 2402 to locations ideal for projection onto the alignment marks) are patterned into TC 111. In one embodiment, the light paths are made in a custom layer which is attached to the rest of TC 111. In one embodiment, the attachment is performed using adhesive, vacuum, electromagnetic force, magnetic force, electrostatic force, etc. In one embodiment, the light paths consist of only transmissive and reflective diffracting structures. In one embodiment, the light paths are created using nanoimprint lithography (NIL). In one embodiment, the light paths consist of repeating standardized sections, which could be patterned using a limited number of fixed masks or reticles.
The bulk HF etcher is used to create tethers in the sacrificial layer of one or more source substrates.
In one embodiment, substrates are arranged horizontally on a multi-substrate chuck. In another embodiment, substrates are arranged vertically on a multi-substrate rack.
In one embodiment, in-situ metrology for endpoint and uniformity measurement is conducted for one or more of the substrates being etched.
A stocker unit could be used to store multiple, fully and partially populated, source/product/intermediate substrates 103/105/801. The stocker unit could be used to store TC unit 111 and metrology unit 108 as well. In one embodiment, TCs 111 could have fields 401 attached to them. In one embodiment, the stocker unit has dedicated vacuum sources with emergency power backup to supply vacuum to the stored TCs 111.
In one embodiment, the stocker unit has temperature and humidity control.
In one embodiment, single or multiple robotic handler units could be used to move individual substrates, substrate groups, TCs 111, metrology units 108 between various parts of the n-MASC tool, etc.
Referring now to
As shown in
Furthermore, as shown in
Furthermore,
A further discussion regarding
A Known-bad-die Replacement Chuck (KRC) 2601 is used to replace known bad dies (KBDs) 2605 with known good dies (KGDs) 2603. One or more buffer substrates 2604 are used as the source of KGDs 2603. KRC 2601 could replace KBDs 2605 (with KGDs 2603) on one or more of the source/intermediate/product substrates 103/108/105. The design of KRC 2601 could be similar to TC 111 in its ability to chuck fields 401, sense and correct overlay, maintain thermal stability, etc.
In one embodiment, KRC 2601 replaces KBDs 2605 on source substrate 103. KBDs 2605 are selectively released from source substrate 103, for instance, using localized UV exposure of the UV release adhesive, and replaced by a KGD 2603 using KRC 2601. In one embodiment, TC 111 picks up groups of two or more dies from source substrate 103 that has had one or more or all of its KBDs 2605 replaced with KGDs 2603, and proceeds with assembly onto product substrate 105.
In one embodiment, KRC 2601 assembles KGDs 2603 on product substrate 105. KBDs 2605 are either removed directly from TCs 111 after pickup from source substrate 103, or alternatively TC 111 avoids picking up KBDs 2605 from source substrate 103. The space on product substrate 105 that would have been occupied by KBDs 2605 is filled by KGDs 2603 picked from buffer substrates 2602 and assembled onto product substrate 105 using KRC 2601.
In one embodiment, KRC 2601 assembles KGDs 2603 on an intermediate substrate (not shown in
In one embodiment, the dies (e.g., dies 2603) on buffer substrate 2602 are height mapped, such that KRC 2601 could pick up KGDs 2603 of the correct height to place onto the source/intermediate/product substrates 103/801/105. Height mapping could be performed using a variety of methods, such as air gages, confocal laser sensors, etc.
In one embodiment, KRC 2601 is attached to the n-MASC tool using a z-actuation assembly that is independent of the z-actuation assembly for TCs 111. In another embodiment, KRC 2601 is mounted onto the same z-actuation assembly as TC 111 (with the TCs 111 unloaded from the z-actuation assembly temporarily).
The pick-and-place assembly tool could be designed to operate in various regimes of throughput, overlay and yield.
Exemplary throughput options are as follows—
Referring now to
Referring to
As shown in
Furthermore, as shown in
Additionally, as shown in
As shown in
As shown in
As shown in
Afterwards, TSV formation and package connections are performed forming device 3006 that includes connections 3007 to the package and TSVs 3008.
Referring now to
As shown in
Referring now to
As shown in
The following discussion is based on
In one embodiment, source substrate 103 contains a buried sacrificial layer 2702, 2707. In one embodiment, sacrificial layer 2702, 2707 is silicon oxide. In one embodiment, the starting substrate for the sacrificial-layer-containing source substrate consists of a low-doped n-type layer (shortened to N−) 2708, 2712 and a high-doped p-type layer (shortened to P++) 2709, 2713. The high-doped p-type layer 2709, 2713 can be first converted to porous silicon (using silicon anodization, for instance), and subsequently oxidized to create a buried sacrificial layer of silicon oxide. The low-doped n-type layer 2708, 2712 remains unaffected during anodization and limits the anodization to only the high-doped layer. In one embodiment, the layers with low-n-type and high-p-type doping could be created using epitaxial growth. In one embodiment, the bulk silicon itself is highly p doped (e.g., layer 2711).
In one embodiment, source substrate 103 consists of background devices on a carrier substrate. The carrier substrate could be bulk silicon, glass substrate, tape frame, etc., depending on the process used for creation of the background devices and the desired device orientation. In one embodiment, the carrier substrate is transparent. In one embodiment, the carrier substrates are attached to the background fields using a UV-release adhesive. In one embodiment, the carrier substrates are attached to the background fields using a sublimating polymer. In one embodiment, back-grinding is performed using the MACE process.
In one embodiment, the background fields are attached to the carrier substrate using a light-to-heat conversion (LTHC) adhesive layer. In one embodiment, after pickup (by one or more TCs 111), fields 401 could be cleaned on TC 111 itself (for instance) using oxygen plasma, etchant vapor (for instance, vapor HF), and/or etchant liquid.
In one embodiment, distortion of thin fields 401 due to residual stresses is controlled using a structural encapsulation layer of a thickness and material such that the rigidity of the encapsulation layer is close to or equal to the rigidity of the underlying field 401. In one embodiment, the encapsulation layer consists of a chemical encapsulation layer 2803 (to protect against chemical damage) along with a structural encapsulation layer 2804 (to prevent distortion due to residual stresses). In one embodiment, structural encapsulation layer 2804 is patterned to counter varying distortion tendencies across the area of field 401. In one embodiment, residual distortion in the encapsulated fields is sensed using wavefront-based methods, laser-based raster scan methods, capacitive methods, etc.
In one embodiment, for face-to-back assembly, the encapsulation layer on picked fields 401 is not removed prior to bonding. In one embodiment, a residual-stress-compensating structural encapsulation layer is included in the device itself. In one embodiment, metal interconnects run through structural encapsulation layer 2804.
In one embodiment, the encapsulation layer includes compliant elements to prevent field distortion due to embedded particles. In one embodiment, the compliant elements are in the form of the compliant pins of a compliant pin chuck. In one embodiment, the encapsulation layer includes a compliant polymer layer to prevent field distortion due to embedded particles.
In one embodiment, the encapsulation layer contains a scratch resistant layer, made for instance using, a diamond-like layer or hard coatings, such as aluminum oxide.
In one embodiment, the encapsulation layer consists of the following three layers—carbon, silicon oxide, carbon (with the silicon oxide sandwiched between the two carbon layers).
In one embodiment, the pattering of the encapsulation layer is conducted using nanoimprint lithography, photolithography, e-beam lithography, etc. In one embodiment, the patterning of the encapsulation layer is conducted using the same lithography process that is used for creation of field access holes.
In one embodiment, fields 401 contain nanowire-forests at the bonding interface to facilitate electrical connection. In one embodiment, the nanowire-forests incorporate copper nanowires.
In one embodiment, through silicon vias (TSVs) 2902, 2904, formed post-bonding to electrically connect bonded fields 401, have a multi-shell structure that could include a metal connection (for instance, in the center of the TSV), along with a low-k dielectric in the form of an anulus around the metal connection.
In one embodiment, assembled fields 401 on product substrate 105 consist of memory layers (e.g., 3002) and logic layers (e.g., 3001). In one embodiment, fields 401 on product substrate 105 contain interposers (e.g., interposer field 3201) that could be used to create electrical connectivity, heat dissipation, etc.
In one embodiment, for face-to-back assembly, field-contacting pins on the transfer chucks have a cross-sectional area that is larger than the size of the optional access holes in fields 401.
In one embodiment, starting substrates with sacrificial layers are attached to a carrier substrate with an adhesive, and the sacrificial layer stripped off, such that source substrate 103 consists of fields 401 on a carrier substrate.
Fields 401 on an incoming background source substrate could be first transferred to an intermediate substrate 801, and subsequently transferred using TC 111 to a second intermediate substrate 801, which is then finally flipped onto and hybrid bonded to product substrate 105. The incoming background singulated fields could be on a transparent carrier (for instance, glass, quartz, sapphire, and/or polymer). The first intermediate substrate 801 could be a transparent substrate (for instance, glass, quartz, sapphire, and/or polymer). The second intermediate substrate 801 could be a transparent substrate (for instance, glass, quartz, sapphire, and/or polymer) or a non-transparent substrate (in visible spectrum), for instance, silicon. The adhesive that attaches fields 401 to the carrier substrate in source substrate 103 could be UV-releasable, thermally releasable, etc. The adhesive used to attach fields 401 to the first intermediate substrate 801 in source substrate 103 could be UV-releasable, thermally releasable, etc. In one embodiment, fields 401 from source substrate 103 are released after flipping and attachment onto the first intermediate substrate 801 by UV exposure of the UV-release adhesive on the source substrate side.
Referring to
Furthermore, as shown in
In one embodiment, wafers 3301 are flipped with temporary bonding and the pre-flip carriers 3302 are detached, such as by using a transfer chuck 111, thereby forming source wafers 3305A-3305N (3305A identified as “source wafer 1,” 3305B identified as “source wafer 2,” and 3305N identified as “source wafer N”) as shown in
Next, there may be a collective die transfer to an intermediate wafer 3306A-3306N (3306A identified as “intermediate wafer 1,” 3306B identified as “intermediate wafer 2,” and 3306N identified as “intermediate wafer N”) while potentially adjusting the pitch in the X and/or Y directions using TC 111 as shown in
Furthermore, as shown in
Additionally, as shown in
Referring now to
As shown in
Referring now to
As shown in
After the transfer, transfer wafer 3309 is flipped with temporary bonding and carrier substrates 3302 are detached, such as by using a transfer chuck 111, thereby forming structure 3501.
Furthermore, as shown in
Referring now to
As shown in
Furthermore,
Furthermore,
In one embodiment, TC 111 includes a full reconfigurable array of mini-TCs 3601 that is 300 mm×300 mm. An expanded version of the cross-section of mini-TC 3601 is shown in
As shown in
Referring to
Additionally,
As shown in
Referring now to
As shown in
Referring now to
Referring now to
Referring now to
Referring now to
As shown in
Referring now to
Referring now to
Referring now to
In one embodiment, δy, δz, θz, θx are controllable. In one embodiment, TC 111 includes an optional flexure bearing with an optional frictionless rotary bearing.
As shown in
A further discussion regarding
Please find below a listing of the definitions of terms discussed herein.
In one embodiment, singulated fields on source substrate 103 (obtained after backgrinding) are first transferred to an intermediate substrate 801 using a transfer chuck 111, and subsequently transferred to a transfer substrate 3309. In one embodiment, during transfer from source substrate 103 to intermediate substrate(s) 801, fields 401 are displaced in the X and/or Y axes, such that field pitch matches the grid pitch on product substrate 105 along the X and/or Y axes. In one embodiment, during transfer from the intermediate substrate(s) 801 to transfer substrate(s) 3309, fields 401 are displaced in the X and/or Y axes, such that field pitch matches the grid pitch on product substrate 105 along the X and/or Y axes. In one embodiment, during the transfer from intermediate substrate(s) 801 to transfer substrate(s) 3309, predicted overlay error of fields on product substrate 105 is compensated fully or partially by actuators (thermal, mechanical) on TC 111 and/or a transfer substrate chuck. In one embodiment, fields 401 are transferred from transfer substrate 3309 to product substrate 105 in a whole-substrate manner. In one embodiment, transfer substrate 3309 is detached from the temporarily bonded fields using heating (with a thermal release adhesive) or UV exposure (with a transparent or perforated substrate and UV curable adhesive). In one embodiment, transfer substrate 3309 is detached from fields 401 after temporary bonding onto product substrate 105 (with the bonding performed using room temperature hybrid bonding, for instance). After detachment of transfer substrate 3309, residual adhesive and/or UV-curable planarizing material are cleaned off using an oxidizing wet clean, O2 plasma ashing, etc. The clean could be performed after temporary bonding between oxide surfaces and prior to permanent bonding, where permanent bonding is performed using thermal curing of hybrid bonded surfaces.
One or more of the source/intermediate/transfer substrates 103/801/3309 could be composed of a glass substrate, a glass substate in roll form, aluminum, aluminum in roll form, aluminum in foil form, polymers, polymers in roll form, stainless steel, and/or stainless steel in roll form. In one embodiment, one or more of the source/intermediate/transfer substrates 103/801/3309 have through-substrate perforations that act as light guides.
In one embodiment, intermediate and transfer substrates 801, 3309 are composed of a transparent substrate (e.g., silicon oxide, fused silica, glass, etc.), a non-transparent substrate (e.g., silicon), and/or a partially transparent substrate (e.g., silicon with perforations). Silicon substrates with perforations could be fabricated using deep etch processes, such as deep reactive-ion etching (DRIE), metal assisted chemical etching (MACE), etc.
In
In one embodiment, TC 111 is reconfigurable, and contains optical elements (to focus light from and onto light source 2402 and light sensors on MM 108) attached to every single or a group of actuation units. In one embodiment, the TC contains one or more light sources attached to every single or a group of actuation units 1007. In one embodiment, optical elements and light sources 2402 associated with a single actuation unit 1007 can themselves be displaced in the X, Y, and/or Z axes relative to actuation unit 1007. The actuation could be performed using magnetic, electromagnetic (for instance, voice coils), thermal, piezoelectric, and/or pneumatic actuation modalities.
In one embodiment, an assembly of turn mirrors and a single or multiple light source(s) 2402 are used to project light for metrology onto TC 111. In one embodiment, the turn mirrors are composed of mirrors with reflectivity that starts at a predetermined amount and gradually increases and/or decreases as one proceeds along the light path from light source(s) 2402. In one embodiment, the turn mirrors are composed of a transparent substrate coated with patterned films of a reflective material, with varying pattern pitch to match the reflectivity requirement at a particular location.
In one embodiment, a laser-based method could be used to ablate and/or evaporate plugging material 1201. The laser could be used to heat the portion of TC 111 immediately surrounding plugging material 1201. In one embodiment, the laser operates in the ultraviolet frequency. In one embodiment, the laser has a wavelength of 257 nm. In one embodiment, the laser is a continuous wave laser, pulsed laser or an ultrashort pulse laser. In one embodiment, a wet clean is used to etch plugging material 1201. The cleaning material could be dispensed only near the locations where plugging material 1201 is located.
In one embodiment, plugging material 1201 is a transient material. In one embodiment, plugging material 1201 is end-capped polyoxymethylene.
In one embodiment, two or more TCs 111 are used, where one of the TCs 111 is used for pick-and-place assembly, and rest of the TCs 111 are cleaned and returned to their default state for vacuum switching. In one embodiment, TCs 111 are attached to an indexing mechanism. In one embodiment, TCs 111 are attached to a mechanism that flips their orientation as well as indexes them for cleaning.
In one embodiment, a thermally stable optical plate is used as the reference to measure registration errors of fields on the source substrate(s) 103, intermediate substrate(s) 801, transfer substrate(s) 3309 and/or product substrates 105. In one embodiment, the optical plate is custom made for measuring registration for different dies. In another embodiment, the optical plate is composed of a dense array of alignment marks that remains the same for new kinds of dies.
In one embodiment, the adhesive(s) 3304 used to attach fields 401 to the source substrate(s) 103, intermediate substrate(s) 801, transfer substrate(s) 3309, and/or product substrate(s) 105, could be composed of two or more layers. The layers could be UV-curable adhesive, nano-particle inks, thermally-curable adhesive, pressure-sensitive adhesive, and/or transient materials. In one embodiment, the nano-particle inks absorb radiation in a narrow wavelength range. In one embodiment, the nano-particle inks absorb radiation in a narrow wavelength range, at which one or more of the substrates and chucks in the n-MASC system show minimal or zero absorption. In one embodiment, one of the components of adhesive 3304 is a transient material that turns into a gas upon heating. The heating could be produced using radiative (for instance, using a laser), convective or conductive heat transfer. In one embodiment, the transient material contains polyoxymethylene. In one embodiment, adhesive 3304 is dispensed onto the source substrate(s) 103, intermediate substrate(s) 801, transfer substrate(s) 3309, and/or product substrate(s) 105 in adhesive islands (e.g., adhesive islands 3308, 3401, 3502). The adhesive islands (e.g., adhesive islands 3308, 3401, 3502) could vary in size from less than 10 μm across to 300 mm across.
In one embodiment, the source substrate(s) 103, intermediate substrate(s) 801, transfer substrate(s) 3309, and/or product substrate(s) 105 contain a fixed and dense grid of alignment marks. The grid of alignment marks could be used as a fixed and stable reference to measure the misalignment of fields 401 picked on TC 111, for instance.
In one embodiment, adhesive 3304 dispensed onto source substrate(s) 103, intermediate substrate(s) 801, transfer substrate(s) 3309, and/or product substrate(s) 105 is performed outside of the n-MASC tool.
In one embodiment, a stock of one or more buffer source substrates of each type (needed by product substrate 105) are maintained in a stocker unit in the n-MASC tool. If the current stock of buffer substrates are all partially populated, and do not contain all the dies needed at the correct locations to produce the required field layout on product substrate 105, a new buffer substrate can be added for the specific field type, until a preset limiting number of buffer substrates is reached, at which point, die-by-die or low-number-of-die pick-and-place is implemented using one or the already existing buffer substrates in the inventory.
In one embodiment, one or more of the encapsulation layers used during n-MASC contain conductive elements. In one embodiment, the conductive elements are connected to a potential source to create electrostatic attraction between a transfer chuck 111 and field 401 on which the encapsulation layer lies. In one embodiment, one or more of the encapsulation layers are on the opposite face of field 401 as the device structures.
In one embodiment, one or more mini-TCs 3601 are used to pick-and-place one or more dies 901. Mini-TCs 3601 rest on rails 3806 and could be actuated using electromagnetic attraction and/or repulsion between rails 3806 and sliders 3802. An exemplary system is shown in
In one embodiment, the TC reconfiguration could be feedback controlled. Global precision could be achieved using an encoder plate. In one embodiment, the encoder plate is used only at the start of the assembly of a particular source wafer set. The encoder plate could be loaded onto the source wafer chuck 102, TC 111 reconfigured, and then could be removed. Each mini-TC 3601 could reference the globally precise encoder plate. Real-time feedback could be implemented by incorporating the encoder plate in source wafer chuck 102 or potentially MM 108.
In one embodiment, mini-TCs 3601 rest on pucks that slide on an electromagnetic plate that is able to control the motion of said pucks in the X, Y, Z, θx, θy, and/or θz axes. Mini-TCs 3601 could face upwards and dies 901 and/or fields 401 to be picked-and-placed face downwards (such that the process of pickup separates the dies and/or fields from the substrate in a downward direction).
In one embodiment, mini-TCs 3601 rest on a 300 mm or larger chucking surface. In one embodiment, mini-TCs 3601 are attached to the chucking surface using vacuum, electromagnetic forces, and/or chemical adhesion. During pick-and-place assembly, mini-TCs 3601 could be picked up from the chucking surface using a mini-TC picker mechanism and expanded or contracted in the X and/or Y axes to match the SPPx or SPPy of product substrate 105 prior to placement on the intermediate wafer(s) 801, transfer wafer(s) 3309 or product wafer(s) 105. The expansion could be performed in either one step or two steps. In the one step expansion case, the picker mechanism could contain flexure mechanisms, for instance, based on scissor mechanisms that can be expanded independently in both the X and Y directions. In the two-step expansion case, the picker mechanism first expands the pitch of all mini-TCs 3601 in one direction. Subsequently, the mechanism is rotated by 90 degrees, or a separate mechanism is utilized which is arranged in an orthogonal direction to the first mechanism, to expand the pitch of mini-TCs 3601 in the orthogonal direction. The picker mechanism could expand the pitch of mini-TCs 3601 using rail-type systems described above, or scissor-type mechanisms, or combinations of the above.
Referring now to
As shown in
Furthermore, a top view of TC 111 is provided in
Referring to
An expanded view of a cross-section of Y rail 4002 is depicted in
As shown in
Referring to
A top view of ACM 3903 showing the routing of vacuum inlet 4209 is depicted in
A further discussion regarding
In one embodiment, transfer chuck 111 could be composed of an array of adaptive chucking modules (ACMs) 3903, each of which can be used to pick and place one or more fields 401 from one or more of the source/intermediate/product substrates 103/801/105. In one embodiment, ACMs 3903 are composed of an array of valve units. In one embodiment, an electrostatic actuation mechanism is utilized to actuate the valves. In one embodiment, a seal 4207 consisting of one or more chambers is utilized to isolate vacuum inlet 4209 from the outlet. In one embodiment, the air volume contained inside seal 4207 consisting of one or more chambers is used to cushion the impact of membrane 4208 as it closes the valve.
ACMs 3903 could be moved with respect to each other using a variable pitch mechanism. The variable pitch mechanism could be composed of flexure bearings, air bearings, and electromagnetic bearings as well as pneumatic, electromagnetic actuators. In one embodiment, ACMs 3903 are mounted on planar motors that provide actuation along 6 axes. Some exemplary designs are shown in
In one embodiment, ACMs 3903 include a mechanism for theta actuation of ACMs 3903 with respect to the variable pitch mechanism (VPM). In one embodiment, the theta actuation mechanism is flexure-based. In one embodiment, the theta-actuating flexures are actuated using thermal actuators that induce a thermal expansion in the flexure arms. In one embodiment, the spacing between picked fields in TC 111 (or equivalently the pitch of ACMs 3903) is increased to accommodate a greater length of flexures, for the thermal actuation to produce a larger theta displacement.
In one embodiment, one or more imagers 1401 are used to detect errors in field pick-and-place by ACMs 3903. In one embodiment, imagers 1401 are visible light imagers or IR imagers. In one embodiment, imagers 1401 observe a single ACM 3903 per imager or multiple ACMs 3903 per imager. The image stream from imagers 1401 could be used by automated fault detection algorithms to flag errors in the pick-and-place process. The fault detection algorithms could be based on artificial neural networks (ANNs), convolutional neural networks (CNNs), etc.
Referring to
Referring to
Referring now to
As shown in
Furthermore, as shown in
Furthermore,
Additionally,
Furthermore,
Furthermore,
Additionally,
Furthermore,
Additionally,
Referring now to
Furthermore,
Referring to
Referring to
In one embodiment, transfer substrate 3309 contains embedded structures, that are selectively compliant in the Z-direction while being stiff in the X and Y directions. Exemplary structures are shown in
In one embodiment, the in-plane distortion of transfer substrates 3309 is controlled using thermal actuation (e.g., peltier coolers, infrared radiation-based localized heating sources), and mechanical actuation techniques. In one embodiment, thermal actuation is utilized to draw out any excess heat generated during adhesive curing using UV radiation, for instance. Optionally, high-heat-conductivity adhesives could be used to facilitate the heat transfer process.
In one embodiment, transfer substrate 3309 is custom made for each new SiP. In one embodiment, encapsulation layer 4409, mesa layer 4401 and in-coupling grating layer 4406 are custom patterned for each SiP.
In one embodiment, to prevent interference of the transfer-substrate-facing surface of TC 111 with pre-existing fields 401 on transfer substrate 3309 (when placing fields 401 that have been picked up by TC 111 onto transfer substrate 3309), a short plasma strip step could be used to reduce the thickness of encapsulation layer 4409 on the pre-existing fields 401. The plasma could be an atmospheric pressure plasma.
In one embodiment, to prevent interference of the transfer/source/intermediate-substrate-facing surface of TC 111 with pre-existing fields 401 on the transfer/source/intermediate substrate 3309/103/801 (when placing fields 401 that have been picked up by TC 111 onto the transfer/source/intermediate substrates 3309/103/801), a repulsive force could be created between pre-existing fields 41 on the transfer/source/intermediate substrate 3309/103/801 and the transfer/source/intermediate-substrate-facing surface of TC 111. The force could be created by forcing air out of ACMs 3903 (that are in TC 111) at the pre-existing field locations, to create a thin cushion of air that separates the pre-existing fields 401 from the substrate-facing surface of TC 111. Alternatively, the force could be created by charging the substrate-facing surface of TC 111 and TC-facing surface of the pre-existing fields 401 with similar polarity charges, to create an electrostatic repulsion between the surfaces. In one embodiment, the compliance of the z flexure structures 4412 (also referred to as “flexure stems”) inside the transfer/source/intermediate substrates 3309/103/801 could be changed to assist in creation of the TC-to-field gap during the placement step.
In one embodiment, one or more of the mesa layers 4401, waveguide layers 4405, encapsulation layers 4409 and z-compliant structures 4410 in transfer substrate 3309 are made using materials that have a high thermal conductivity (for instance metals, silicon, high thermal conductivity composite polymers that contain high thermal conductivity fillers), to allow vertical and lateral transport of heat away from fields 401 and towards the bulk of the transfer/source/intermediate substrate 3309/103/801 and transfer chuck 111.
In one embodiment, the thickness of mesa structures 4401 is increased to increase the local X, Y compliance of the transfer/source/intermediate substrate 3309/103/801. In one embodiment, the volume of the adhesive drops 4416 is increased to increase the pinned height of adhesive 4404, to increase the effective local X, Y compliance of the transfer/source/intermediate substrate 3309/103/801.
Referring to
Furthermore,
Furthermore, as shown in
Referring now to
As shown in
Furthermore, as shown in
Furthermore,
Additionally,
Furthermore,
Furthermore,
Additionally,
Referring now to
In one embodiment, source substrate 103 could be composed of fields 401 attached to a transparent carrier substrate (for instance, glass, fused silica, sapphire), or a tape frame carrier membrane, using an adhesive (e.g., adhesive 4707). The adhesive could be a continuous film, a continuous film the thickness of which varies to compensate for the thickness variation in fields 401, or separated into islands the X/Y extents and thicknesses of which vary to account for the different X/Y extents and thicknesses of fields 401. In one embodiment, such a source substrate 103 is fabricated by starting with fields 401 on a substrate with a sacrificial layer, for instance, silicon-on-oxide (SOI), silicon-on-sapphire (SOS), flipping and adhering to a suitable carrier substrate in a whole-substrate manner, and detaching the bulk of the starting substrate using a suitable etchant. In one embodiment, the starting substrate consists of fields 401 fabricated on a silicon layer that lies on top of a sacrificial silicon-germanium (SiGe) layer. Such SiGe layers could be grown using epitaxial deposition techniques. The etching of the sacrificial silicon-germanium layer could be performed using wet etching, plasma etching, atomic layer etching and hybrid etching methods. In one embodiment, an etchant composed of vapor HF, vapor H2O2, and vapor acetic acid is used.
Referring to
As discussed above, in step 4801, a partial etch of sacrificial layer 4903 is performed to create tethers 4906 as shown in
In step 4802, bulk substrate 4904 is flipped and temporarily attached to an intermediate substrate 4907 via an adhesive 4908 as shown in
In step 4803, bulk substrate 4904 is separated using a sacrificial layer etch as shown in
In step 4804, intermediate substrate 4907 is flipped and temporarily attached to a source substrate 4909 (e.g., source substrate 103) for assembly using islands of adhesive 4910 as shown in
In step 4805, intermediate substrate 4907 (along with adhesive 4908) is removed, such as via an etching technique, as shown in
A further discussion regarding method 4800 is provided below.
In one embodiment, fields 401, 4901 contain access holes distributed throughout the area of field 401, 4901. The etchant for the sacrificial layer (e.g., sacrificial layer 4903) could be sourced through access holes 4902 in addition to sourcing from the edges of fields 401, 4901 (during tether formation etch and bulk substrate separation). In one embodiment, the XY pitch for access hole 4902 is 20 μm. In one embodiment, a silicon layer above sacrificial layer 4903 is ˜300 nm thick. In one embodiment, sacrificial layer 4903 (for instance, SiGe or SOI) is ˜0.5 μm thick if a vapor etchant is used or ˜5 μm thick if a wet etchant is used with the values chosen to allow for sufficient lateral transport of the sacrificial layer etchant.
In one embodiment, the thickness of mesa structures 4401 (shown in
In one embodiment, the thickness of fields 401, 4901, as they are lying active-side-down, during back-grinding or during the source wafer creation process shown in
The adhesives described herein could be used to attach fields 401, 4901 to the source, intermediate, transfer, and carrier substrates 103, 801, 3309, 4904, as well as transfer chucks (TCs) 111. The adhesives could be composed of UV-release adhesive, thermal-release adhesive, light-to-heat-conversion (LTHC) coatings, liquid-crystal-based (LC) adhesives, UV-phase-switching LC-based adhesives, etc.
In one embodiment, the adhesive layer is composed of one or more layers of a first light-absorbing layer and a layer of transient material(s). The light absorbing layer could be a purely polymeric layer (for instance, LTHC coatings manufactured by 3M®), or a composite of polymer and nanoparticles that are optimized for light absorption. In one embodiment, fields 401, 4901 could be coated on their underside and/or their entirety using an adhesive coating (for instance, VALMat) that sticks to the transient material.
In one embodiment, adhesive drops 4416 are dispensed at a suitable distance away from the edges of a field 401, 4901, so that the cantilevered field (near the edges of field 401, 4901) bends to accommodate any residual height disparity between adjacent fields 401, 4901 during hybrid bonding. Such a bending would not necessarily lead to any significant overlay errors if the thickness of fields 401, 4901 is small.
In one embodiment, a light-to-heat-conversion (LTHC) layer is used to locally heat, and/or vaporize, the adhesive. The LTHC layer could be composed of one or more of the resonant absorber layers. In one embodiment, the LTHC contains embedded nanoparticles that are designed to absorb radiation in a narrow wavelength range, ideally at a wavelength at which one or more of the TCs 111, source substrates 103, transfer substrates 3309 show minimal or zero light absorption. In one embodiment, the adhesive is composed of polyimide. In one embodiment, the adhesive is composed of polyimide-LTHC-based release layers.
In one embodiment, the nanoparticles used for light absorption in the LTHC layer are made using gold, silicon, ruthenium, noble metals, titanium, and/or tungsten. In one embodiment, the size of the nanoparticles is increased to increase their melting point (for instance, the melting point of gold nanoparticles drops as the size of the nanoparticles decreases).
Referring now to
Referring to
At any point in time, there are N (N is a positive integer number) active buffer substrates 5002 that are maintained. In one embodiment, these are, at all points of time, maintained to be at a low level of depletion so that the KBD replacement step for any given transfer wafer 3309 can be completed in at most one or two pick and place steps.
As shown in
Furthermore, as shown in
Furthermore,
As shown in
Furthermore, plasma etching for field dicing is shown in
In one embodiment, alignment marks 5108, 5109 are created in the fields during singulation.
In one embodiment, alignment marks 5108, 5109 are created on the backside of the fields. For example, photolithography (PL) or nanoimprint lithography (NIL) may be used for patterning of marks 5108, 5109. In another example, deep reactive ion etching (DRIE) may be used for dry etching of marks 5108, 5109. In a further example, CICE may be used for etching of marks 5108, 5109. Marks 5108, 5109 could be placed below the circuit patterns or near kerf region 5107 away from the circuit regions. In one embodiment, marks 5108, 5109 could be etched all the way through the thickness of the fields or partially.
The singulation of the fields could be performed using a separate set of pattering and etching techniques (compared to the alignment mark creation step). Photolithography (PL) or nanoimprint lithography (NIL) could be used for the patterning. Dry etching (e.g., DRIE) may be used for etching. Furthermore, wet etching (e.g., CICE) may be used for etching. Alternatively, singulation could be performed using a laser-based method, such as laser cutting, or stealth dicing.
Referring now to
Referring now to
As shown in
Referring to
In one embodiment, fields 401 from a source substrate 103 that have been picked up by TC 111 are sampled at a limited set of locations, using upward-looking microscopes 5201, to measure the position of those fields 401 with respect to a stable reference grid 5203, and/or with respect to TC 111. The position of the rest of the picked fields 401 on TC 111 could be extrapolated using a suitable position extrapolation technique.
The alignment marks on fields 401 could be observed from the bottom-side of TC 111, from above TC 111 directly, or from above TC 111 with the alignment signal sourced through in-coupling gratings 4406 (that are used to send in UV light for adhesive curing). Interference of the alignment signal with circuit elements on fields 401 (for instance) could be filtered out using computational methods or by designing the position of the alignment marks such that they avoid interfering structures.
In one embodiment, the position of ACMs 3903 on the VPM, such as VPM 4302, could be observed directly with respect to a stable 2D grid. Compact grid encoders could be integrated onto ACMs 3903 and be used to look at the 2D grid plate to measure the displacement of the ACMs 3903 in real-time during assembly.
In one embodiment, transfer substrate 3309 contains a grid of alignment marks. The grid of alignment marks could be patterned on the mesas (e.g., mesa 4401) in transfer substrate 3309, using optionally the same technique that is used for fabricating the mesas (e.g., mesa 4401) (for instance, i-line lithography). In one embodiment, the incoming fields 401 are aligned to the grid of alignment marks on transfer substrate 3309. The field position errors coming in from the optional upward facing microscopes 5201, and from the alignment microscopes for measuring the alignment between transfer substrate 3309 and fields 401, could be corrected for by the set of thermal actuators on the transfer substrate chuck.
In one embodiment, the zero-layers for all fields 401 are fabricated on the same lithography tool (this includes different kinds of fields, and not simply different fields of the same kind).
In one embodiment, the field-facing surface of TC 111 is polished to be highly flat so as to act as a reference flat for fields 401 that are picked and placed. In one embodiment, the surface of TC 111 is actively modulated in the z-direction to achieve a flat or a desired non-flat profile.
In one embodiment, product wafer chuck 104 contains actuators to flatten the surface of product wafer 105 prior to hybrid bonding. Sensing of the topography on product wafer 105 could be performed using laser-based methods, air gages, etc. Actuation of the wafer chuck could be performed using piezoelectric actuators, thermal actuators, and/or electromagnetic actuators.
Referring now to
As shown in
Referring now to
As shown in
As shown in
The following discussion is based on
MACE could be used to dice substrates into fields 401.
In one embodiment, the diced edges are straight. In another embodiment, the diced edges could have one or more curved or angled elements (such as 90° corners, etc.).
In one embodiment, the MACE catalyst is dispensed onto the un-diced substrates (e.g., un-diced fields 5101) using one or more inkjets. In one embodiment, the catalyst is gold. After dicing, the catalyst could be removed using an etchant (for instance, aqua regia for a gold catalyst).
In another embodiment, a knife-edge dicer frame 5401 is used to etch into the substrate (e.g., substrate 3302). In one embodiment, the knife-edge 5402 is coated with a MACE catalyst. In one embodiment, knife-edge 5402 is coated with a protective layer (a carbon layer, for instance). In one embodiment, knife-edge 5402 has intermittent stabilizing structures.
In one embodiment, MACE etchant covers the entire substrate (e.g., substrate 3302). In one embodiment, MACE etchants are dispensed using an inkjet near the kerf region 5107 of fields 401. In one embodiment, the MACE etchant is contained near kerf region 5107 using a recess that has been etched prior to dicing. In one embodiment, the MACE etchant is contained near kerf region 5107 using surface tension.
In one embodiment, the MACE etchant is circulated to prevent etch stagnation. In one embodiment, etchant circulation is implemented within the neighborhood of kerf region 5107.
In one embodiment, fields 401 are coated with a protective layer to protect against chemical damage during dicing and catalyst removal.
In one embodiment, knife-edge dicer frame 5401 has flexure mechanisms to provide compliance along the Z axis. In one embodiment, knife-edge dicer frame 5401 has flexure mechanisms to provide compliance along the Z axis for each field 401.
In one embodiment, the dicing edge has a cross-section that is optimized to reduce dishing and etch stagnation tendencies. In one embodiment, the dicing edge has a trapezoidal cross-section at the etch region. The trapezoidal cross-section could be created using crystallographic etching (KOH-based etching, for instance).
In one embodiment, the dicing edges have orthogonal structures to provide mechanical support.
In one embodiment, etch-based dicing techniques (e.g., MACE-based dicing) are used to create non-straight field edges. In one embodiment, etch-based dicing techniques (e.g., MACE-based dicing) are used to singulated fields 401 such that alignment marks 5301 on kerf region 5107 are retained after dicing.
Referring now to
As shown in
Referring now to
In particular,
Referring now to
Referring to
Furthermore, in step S701, an optional plasma etch may be performed to improve the profile of catalyst break layer 5802 resulting in the removal of template 5803 as shown in
In step S702, a catalyst 5806 is deposited on UV-cured layer for catalyst break 5805 and substrate 5801 as shown in
The following discusses
In one embodiment, the dicing process is performed from the front side of source substrate 103 or the back side. In one embodiment, the process is performed from the front side of source substrate 103 that has been bonded to a carrier substrate 3302 or the back side of source substrate 103 with the front side bonded to carrier substrate 3302. In one embodiment, the process is performed on back-grounded substrates attached to carrier substrate 3302.
In one embodiment, the etch process for the silicon-containing regions of the device stack is CICE. In one embodiment, the etch process for the silicon components of the device stack is a silicon electrochemical etch. In one embodiment, the etch process for the non-silicon-containing regions of the device stack (e.g., silicon oxide, metals, non-silicon substrates such as germanium, gallium arsenide, silicon carbide) is a physical etch process, such as a deep reactive ion etching (DRIE) or a wet etch process (e.g., an etch that uses an etchant containing hydrofluoric acid in liquid or vapor form).
In one embodiment, the unetched parts of the device stack, such as metal lines that might remain unetched after exposure to an HF etch (for instance), are etched at the end using a more aggressive cleaning etch, such as using aqua regia, nitric acid, etc. In one embodiment, the unetched parts of the device stack that contain copper are etched using ferric chloride, cupric chloride, alkaline etchants, a mixture of hydrogen peroxide and sulphuric acid, chromic-sulphuric acid, sodium chlorate, citric acid, ammonium persulphate, etc. In one embodiment, the etchant for the unetched parts of the device stack is suitably diluted so that it has reduced or no activity for the device encapsulation layer, oxide layers, and other functional device layers. In one embodiment, the etchant is removed post-etch using a spray of dilutant (for instance, water).
In one embodiment, the device layers inside a field 401 are protected during the etching process using an encapsulation layer, such as encapsulation layer 5601. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is composed of a noble metal, a non-noble metal, a non-metal, and/or a polymer. In one embodiment the encapsulation layer, such as encapsulation layer 5601, is composed of CVD carbon. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is composed of parylene, a fluoropolymer (for instance, PTFE), and/or carbon (CVD deposited or spin-coated, for instance). In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is electrically insulating. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, contains silicon oxide.
In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is patterned using photolithography or nanoimprint lithography. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is deposited using inkjetting. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is patterned using the discontinuous film created by fluidic pinning by a patterned template.
In one embodiment, the etchant for the chemical dicing process (using MACE, for instance) is dispensed only near the regions to be etched (using an inkjet, for instance) or be held in a chamber so as to cover the entire substrate including the regions to be etched. In one embodiment, an inkjet is used for etchant dispensing, and all the wetted regions of the inkjet are coated with an etchant-inert layer (e.g., a fluoropolymer, such as PTFE, parylene, etc.).
For MACE-based dicing, in one embodiment, the etch catalyst, such as catalyst 5106, is composed of a noble metal, a non-noble metal, a non-metal, a polymer, and/or a ceramic. In one embodiment, the catalyst, such as catalyst 5106, is composed of Au, Ag, Ru, Pt, Pd, C, Ta, W, Cu, Al, and/or Ni. In one embodiment, the catalyst, such as catalyst 5106, is a bilayer of gold and silver, with silver lying beneath and encapsulated by the gold. In one embodiment, the etch catalyst, such as catalyst 5106, is dispensed as nanoparticle ink using inkjets. In one embodiment, the etch catalyst, such as catalyst 5106, is electroplated. In one embodiment, the etch catalyst, such as catalyst 5106, is deposited using a physical vapor deposition technique, such as sputtering, electron beam deposition, etc. In one embodiment, the etchant is deposited using a technique that produces sidewalls with a line edge roughness (LER) below 10 nm (1σ, or 3σ), for instance, using a physical vapor deposition technique (e.g., e-beam, focused ion beam, sputtering), electroplating, and/or electroless plating. In one embodiment, the catalyst, such as catalyst 5106, contains a thin film of silicon oxide underneath to improve etch uniformity. In one embodiment, the thickness of the silicon oxide film is between 10 nm and 100 nm. In one embodiment, the etch rate of the catalyst, such as catalyst 5106, is controlled by temperature, pH of the etchant solution (using a buffer solution, for instance HF and NH4OH, or NH4F), plasma treatment of the etchant, alloying the catalyst with a material (e.g., carbon) that has lower activity for MACE using combinatorial sputtering.
In one embodiment, the catalyst, such as catalyst 5106, is dispensed on top of a discontinuous polymer film that is created by fluidic pinning (of a UV-curable polymer) by a patterned template, and subsequent UV exposure (of the UV-curable polymer). In one embodiment, the catalyst, such as catalyst 5106, contains a break at the edge between the polymer and the substrate, such as substrate 3302. In one embodiment, plasma-based cleaning is used to clean the edges of the polymer to create an improved metal break.
In one embodiment, MACE-based dicing is stopped in a timed manner, or in case an adhesive film, such as adhesive film 5102, is available (in case the substrate is attached to a carrier substrate), the adhesive film is used as an etch stop. In one embodiment, the adhesive film, such as adhesive film 5102, is coated with an etchant resistant material, such as carbon.
Once dicing is complete, the catalyst, such as catalyst 5106, is removed using a suitable etchant, such as aqua region (or an etchant containing potassium iodide, cyanides, etc.) for gold, or an atomic layer etching process, or in the specific case when partial dicing is performed prior to back-griding, the back-grinding process could also dispose of the catalyst by grinding it off.
In one embodiment, the geometry of the diced edge along a straight edge of a field 401 is composed of curved and/or angled components. In one embodiment, alignment marks, such as marks 5301, are contained in curved portions of diced edge 5303. In one embodiment, diced edge 5303 contains support structures, such as structures 5302, to prevent wandering. Such a support structure may be present on the external or internal portions of diced edge 5303. The alignment marks, such as marks 5301, contain recesses to accommodate the support structures, such as structures 5302. In one embodiment, image processing techniques are utilized to filter out any loss of alignment signal due to the recesses in the alignment marks, such as marks 5301. The recesses created in the alignment marks, such as marks 5301, could be filled-in post-dicing using a suitable material deposition technique, such as CVD (of silicon, silicon oxide, etc.), ALD, etc.
In one embodiment, the catalyst film, such as catalyst 5106, deposited on the metal break layer 5105, is used to create electrostatic attraction between the dies and transfer chuck 111.
High aspect ratio, porosity-free, taper-free semiconductor nanostructures can be made using CICE. CICE is also described as Metal Assisted Chemical Etch (MACE). For CICE of silicon, catalysts that comprise one or more of the following: (in alloy form, if necessary) Au, Pt, Pd, Ag, Ru, Ir, W, Cu, TiN, Ti, Graphene, carbon, etc. catalyze the reduction of H2O2 and inject the resulting electronic holes into silicon thereby changing the oxidation state of silicon. In one embodiment, HF selectively etches this silicon, and the catalyst sinks into the etched region to continue the local redox reaction, thereby producing silicon nanostructures in areas without the catalyst. The characteristics of the resulting silicon nanostructures are highly dependent on the balance of reaction rates, charge transfer, etchant mass transfer and movement of the catalyst. In one embodiment, the substrate for CICE consists of one or more of the following: a single crystal bulk silicon wafer, a layer of polysilicon deposited on a substrate, a layer of amorphous silicon deposited on a substrate, an SOI (silicon on insulator) wafer, silicon-on-glass, silicon-on-sapphire, epitaxial silicon on a substrate, alternating layers of semiconductor materials of varying doping levels and dopants, highly doped silicon and lightly doped silicon, undoped silicon and doped silicon or germanium, silicon and SixGe1-x, differently doped silicon and/or SixGe1-x, differently doped silicon and/or Ge, or Si and Ge.
In one embodiment, the collapse of CICE-etched nanostructures is delayed or eliminated by using “collapse-avoiding caps” or “collapse-avoiding features” on the tips of the nanostructures. In one embodiment, the collapse-avoiding caps prevent collapse by electrostatic repulsion between the nanostructures.
As stated above,
In one embodiment, the catalyst is patterned using one or more of the following: nanoimprint lithography, photolithography, focused ion beam milling, electron beam lithography, laser interference lithography, nanosphere lithography, block copolymer lithography, and directed self-assembly. In another embodiment, the CICE patterning includes using thermally stable carbon, etching into this carbon using NIL (nanoimprint lithography) resist, photoresist, etc., and stripping any polymer resists prior to catalyst deposition using metal break.
Referring to
In step S902, ALD-enhancing material 6003 is patterned on ALD-blocking material 6002 as shown in
In step S903, ALD-blocking material 6002 not covered by ALD-enhancing material 6003 as well as a portion of substrate 6001 not covered by ALD-enhancing material 6003 are etched as shown in
In step S904, a catalyst 6004 is selectively deposited via ALD on the exposed substrate 6001 and ALD-enhancing material 6003 as shown in
In step S905, CICE is performed to create nanostructures 6005 with collapse-avoiding caps 6006, where collapse-avoiding caps 6006 are made by catalyst 6004 and ALD-enhancing material 6003.
Referring now to
Referring to
In step 6102, catalyst material 6203 is directionally deposited on mask 6202 and the exposed areas of substrate 6201 (i.e., those areas of substrate 6201 not covered by mask 6202) as shown in
In step 6103, catalyst material 6203 is removed from the sidewalls of mask 6202, such as via dry etching, as shown in
In step 6104, CICE is performed to create nanostructures 6204 with collapse-avoiding caps 6205, where collapse-avoiding caps 6205 are made by catalyst material 6203 and mask 6202.
During the CICE process, isolated metal catalysts may wander and create non-vertical undesired etch paths. Discontinuous catalyst features tend to wander during the CICE process and cause defects. CICE of holes with isolated catalysts may wander due to van der Waals forces on the catalyst as well as stochastic variations in forces applied due to local etchant concentration or etch rate variations, as shown in
Referring to
To prevent wandering of catalysts, such as catalyst 6301, stabilizing patterns can be inserted in the isolated catalysts—thereby providing a supporting structure to the catalyst during CICE. These stabilizing patterns can be predetermined holes of different cross-sections, that are patterned in the isolated catalyst structures. The supporting structures can be removed after CICE to achieve vertical wander-free CICE.
Referring to
In one embodiment, patterning and fabrication of the catalyst buttress designs shown in
Referring to
In step 6502, a dot pattern 6602 is inserted in catalyst 6301, such as via photolithography, imprint lithography, e-beam lithography, EUV lithography, self-aligned patterning, spacer patterning, etc. as shown in
In step 6503, a spacer pattern 6603 is deposited surrounding dot pattern 6602 as shown in
In step 6504, dot pattern 6602 is removed, such as via various types of etching techniques as shown in
In step 6505, spacer pattern 6603 as well as portions of catalyst 6301 exposed (i.e., portions of catalyst 6301 that are not covered by spacer pattern 6603) are removed via etching, such as via various etching techniques (e.g., dry etching), thereby creating isolated dots as shown in
In one embodiment, the silicon nanostructures after CICE are porous. Porosity in silicon (Si) enhances etchant diffusion and may further prevent wandering of isolated catalysts 6301. In another embodiment, the silicon nanostructures are made using silicon superlattice etch to create alternating layers of porous and non-porous silicon nanostructures for exemplary applications in 3D NAND Flash, as shown in
Referring to
In one embodiment, shown in
Referring to
Similar to etching of holes with CICE, etching of lines and spaces requires long isolated lines of catalysts, which tends to wander during the CICE process. In one embodiment, lithographic links between the lines and spaces are used to connect the isolated catalyst lines. The dimensions and locations of the lithographic links are designed to ensure minimum disruption to the final device requirements. Deposition of filler material using methods, such as CVD, ALD, physical vapor deposition (PVD), etc. are used to fill the gaps etched by CICE in the areas with lithographic links. In one embodiment, the lithographic links are orthogonal to the direction of the desired lines and spaces etch, and ALD of low-k dielectric materials, such as silicon oxide are used to fill the gaps, as discussed below in connection with
Referring to
Referring now to
In step 7102, filler material is deposited, such as via CVD, PVD, etc., in the previously removed lines of catalyst 6301 and lithographic links 7301 as shown in
Fabrication of high aspect ratio structures in polysilicon using CICE enables applications, such as stack capacitors in DRAM.
As isolated catalysts, such as isolated catalysts 6301, suffer from wandering, CICE to create high aspect ratio holes is challenging. In one embodiment, the etched nanostructures can be used to change the tone of the features—from pillars to holes, using atomic layer deposition (ALD) to partially fill gaps between the pillars.
The tone-reversal process with CICE can be further expanded to include arbitrary materials, where polysilicon or silicon structures are made with CICE, and the gaps between the structures are filled with structural material. In one embodiment, the material is an insulator. In one embodiment, the structural material is carbon, amorphous carbon, silicon dioxide, silicon nitride, metal oxide, tin oxide, and/or indium tin oxide. In one embodiment, the deposited material is one or more of the following: SiO2, TiO2, Al2O3, Pd, Pt, W, TiN, TaN, Cu, SiNx, SnOx, ZnOx, etc. The silicon is selectively removed to create the inverse tone of the structures in the structural material. In one embodiment, the etched polysilicon and/or silicon structures are removed using: selective wet etchants (e.g., KOH, TMAH, EDP), dry etchants (e.g., XeF2 vapor), plasma etching (e.g., Cl2, SF6, BCl3, etc. species in plasma. Optionally, desired material can be deposited in the areas where silicon was removed, thereby creating high aspect ratio arbitrary geometry structures in any material. Alternatively, the structural material could be a conductor, and the desired material could be an insulator, depending on the application requirements.
In one embodiment, the etch stop layer is selected such that it does not get etched in the CICE process as discussed in
Referring now to
Referring to
In step 7602, a deposition of oxide 7703 on silicon pillars 7701 and substrate 7702 is performed as shown in
In step 7603, silicon pillars 7701 are removed (i.e., etched) using various etching techniques, such as CICE, as shown in
In step 7604, a desired material 7704 is deposited, such as via CVD, PVD, ALD, etc., in areas where silicon pillars 7701 were removed thereby creating high aspect ratio arbitrary geometry structures as shown in
Referring now to
Referring to
In step 7902, CICE is performed to etch portions of polysilicon 8102 leaving pillars 8105 of polysilicon as shown in
In step 7903, a deposition of oxide 8106 on pillars 8105 and the exposed regions of etch stop layer 8101 (i.e., those regions not covered by pillars 8105 of polysilicon) is performed as shown in
In step 7904, an etchback of oxide 8106 to the top level of pillars 8105 as well as the removal of pillars 8105, such as via various etching techniques (e.g., ALE), is performed as shown in
In step 7905, desired material 8107 is then deposited, such as via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8105 as shown in
Referring now to
Referring to
In step 8202, CICE is performed to etch portions of polysilicon 8402 leaving pillars 8405 of polysilicon as shown in
In step 8203, exposed portions of etch stop layer 8401 (i.e., those portions of etch stop layer 8401 that are not covered by pillars 8405) are removed (i.e., etched), using various etching techniques, such as via ALE, as shown in
In step 8204, a deposition of oxide 8406 on pillars 8405 and the exposed regions of the desired device, such as material 8403 (i.e., those regions not covered by etch stop layer 8401), is performed as shown in
In step 8205, an etchback of oxide 8406 to the top level of pillars 8405 as well as the removal of pillars 8405 and etch stop layer 8401, such as via various etching techniques (e.g., ALE), is performed as shown in
In step 8206, desired material 8407 is then deposited, such as via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8405 and the removed etch stop layer 8401 as shown in
Referring now to
Referring to
In step 8502, portions of polysilicon 8702 are etched, such as via CICE, leaving pillars 8705 of polysilicon as shown in
In step 8503, a catalyst (e.g., Ru) 8706 is deposited on the exposed portions of etch stop layer 8701 (i.e., those portions of etch stop layer 8701 that are not covered by pillars 8705), such as via ALD, CVD, PVD, electroplating or thermal evaporation, as shown in
In step 8504, catalyst 8706 is removed, such as via various etching techniques (e.g., dry etch, wet etch), as shown in
In step 8505, the exposed portions of etch stop layer 8701 (i.e., those portions of etch stop layer 8701 that are not covered by pillars 8705) are removed, such as via an etching technique (e.g., ALE), as shown in
In step 8506, a deposition of oxide 8707 on pillars 8705 and the exposed regions of the desired device, such as material 8703 (i.e., those regions not covered by etch stop layer 8701), is performed as shown in
In step 8507, an etchback of oxide 8707 to the top level of pillars 8705 as well as the removal of pillars 8705 and etch stop layer 8701, such as via various techniques (e.g., dry etch, wet etch), is performed as shown in
In step 8508, desired material 8708 is then deposited, such as via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8705 and the removed etch stop layer 8701 as shown in
In one embodiment, in step 8509, for the tone-reversal CICE, step 8501 is repeated, in which an etch stop layer 8709 and a layer of polysilicon 8710 are deposited on the device structure shown in
In step 8510, step 8502 is repeated, in which portions of polysilicon 8710 are etched, such as via CICE, leaving pillar 8711 of polysilicon as shown in
In step 8511, steps 8503-8507 are repeated, resulting in the structure with oxide 8712 as shown in
In step 8512, step 8508 is repeated, in which desired material 8713 is then deposited, such as via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8711 and the removed etch stop layer 8709 forming the structure shown in
Steps 8509-8512 may continually be repeated for the desired number of metal and/or insulator layers.
In one embodiment, method 8500 is used for metal layers in interconnects, where the structural material is a low-k dielectric, such as silicon oxide or silicon oxynitride, and the desired material is a conductor, such as Cu, Mo, W, Ru, TiN, TaN, Pd, etc. In one embodiment, CICE is used for the fabrication of metal interconnects, and the catalyst, such as catalyst 8706, for CICE is Ru. In one embodiment, the catalyst, such as catalyst 8706, is not removed after CICE, and the Ru is used as a seed layer for electroplating of Cu to create Cu interconnects using the dual-damascene process. Other metals that can be deposited for interconnects include Ru, Co, Mo, TiN, Cu, W, TaN, etc. The metals can be deposited using ALD, CVD, PVD, electroplating or thermal evaporation. In one embodiment, Cu is deposited using electroplating, and polished using CMP.
Tone-reversal CICE can be used to selectively grow superlattice structures in high aspect ratio holes, thereby enabling vertical, taper-free superlattice nanostructures with no sidewall damage, fabricated without the use of plasma etch for the superlattice materials. The superlattice materials may be deposited using selective atomic layer deposition, epitaxial growth, selective electrodeposition etc., such that each layer only grows on the previous layer deposited, and not on the structural material.
Referring to
In step 8802, a deposition of oxide 8904 on pillars 8903 and the exposed regions of substrate 8902 is performed as shown in
In step 8803, an etchback of oxide 8904 to the top level of pillars 8903 as well as the removal of pillars 8903, such as via various technique techniques (e.g., ALE), is performed as shown in
In step 8804, desired material 8905 is then deposited, such as via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8903 as shown in
Roll-to-Roll (R2R) processes can be used for fabrication of silicon nanostructures using R2R deposition of silicon, R2R patterning, and R2R CICE. In one embodiment, polysilicon is deposited on a stainless steel roll and patterned using R2R nanoimprint lithography followed by removal of imprint resist residual layer thickness (RLT). Other substrates include foils of metals and metal alloys, polymer films and other flexible substrates. In another embodiment, a barrier layer is deposited between the roll substrate and the polysilicon. Barrier layers are chemically resistant to the CICE etchant solution and can act as an etch stop. Cr, Carbon, Al2O3 are examples of materials used for barrier layers.
Thin films of adhesion layer material and catalyst material are deposited using e-beam evaporation, thermal evaporation, physical vapor deposition, chemical vapor deposition, etc. Examples of thin films deposited include Ti, Au, Pt, Pd, Ag, Ru, RuO2, Ir, IrO2, TiN, W, Cu, etc. or any combination thereof. The catalyst patterned on polysilicon on the R2R substrate is then exposed to wet chemical etching for CICE. In one embodiment, the rolls are arranged in a vertical orientation, and the etchant is sprayed on the patterned side of the roll. In another embodiment, the CICE process is performed using vapor-phase etchants. In one embodiment, polysilicon nanowires are made using R2R processes for high density anodes in battery and ultracapacitor applications.
Deterministic Lateral Displacement (DLD) is a microfluidic technique which separates particles in a fluid medium based on their size, using specific arrangements of pillars arrays placed within a microfluidic channel. The gaps between the pillars and the placement of the pillars determine the separation mechanics. The pillar arrays required for DLD can be fabricated using nanolithography, such as nanoimprint lithography combined with the Catalyst Influenced Chemical Etching (CICE) process. In one embodiment, shown in
In one embodiment, exfoliation is used to remove a thin layer of silicon from the silicon pillars, such that the remaining silicon substrate can be polished and re-used. This process enables a reduction in cost for DLD device fabrication, which is discussed in Ward et al., “Design of Tool for Exfoliation of Monocrystalline Micro-Scale Silicon Films,” Journal of Micro and Nano-Manufacturing, Apr. 5, 2019, which is incorporated by reference herein in its entirety.
Referring to
Referring to
In step 9102, supporting material 9203 is deposited in the recesses between silicon nanowires 9202 as shown in
In step 9103, nickel 9204 is deposited on top of supporting material 9203 for exfoliation as shown in
In step 9104, at least a substantial portion of silicon wafer substrate 9201 is exfoliated leaving a thin layer of silicon wafer substrate 9201 as shown in
In step 9105, a supporting substrate 9205 is then bonded to the remaining portion of silicon wafer substrate 9201 as shown in
In step 9106, nickel 9204 and supporting material 9203 are removed, such as via an etching technique (e.g., ALE), thereby forming the DLD device as shown in
In step 9107, an encapsulation layer 9206 is deposited on silicon nanowires 9202 of the DLD device as shown in
In one embodiment, the pillars, such as silicon nanowires 9202, in the encapsulated DLD device may be further etched, such as via CICE, to increase the pillar height. For example, CICE etchant may be flown through the device inlets to further etch the pillars, such as silicon nanowires 9202, in the encapsulated DLD device.
Collapse of silicon nanopillars, such as silicon nanopillars 9202, in the DLD arrays limits the maximum height of the pillars. In one embodiment, the pillar height is increased by creating a ceiling structure on the silicon nanopillars using deposition of materials chemically resistant to the etchant, such as carbon, Cr, etc., which is discussed in Rouhani et al., “In-Situ Thermal Stability Analysis of Amorphous Carbon Films with Different Sp3 Content,” Carbon, Vol. 130, Apr. 1, 2018, pp. 401-409, which is incorporated by reference herein in its entirety.
In another embodiment, the ceiling structure, or stabilizing material, is made by co-sputtering an HF-resistant material with a HF-consumed material, thereby creating a porous mesh. In one embodiment, carbon and SiO2 are co-sputtered to create a ceiling structure. When exposed to the CICE etchant, the SiO2 is etched away, resulting in a porous carbon mesh. The porous carbon mesh structurally stabilizes the silicon nanopillars while the CICE etchant further increases their height.
Referring to
In step 9302, stabilizing material 9403 is deposited via various deposition techniques, such as via CVD, PVD, ALD, etc., on the top of DLD pillars 9402 as shown in
In step 9303, stabilizing material 9403 is etched back to below the top portion of DLD pillars 9402 (referred to herein as the “DLD pillar caps 9404”) as shown in
In step 9304, DLD pillar caps 9404 are removed, such as via various etching techniques (e.g., ALE), leaving a small portion of DLD pillars 9402 (identified as element 9405) above the etched back stabilizing material 9403 as shown in
In step 9305, a cover plate 9406 is bonded to the remaining portion of DLD pillars 9405 that remains after DLD pillar caps 9404 were removed as shown in
Referring to
In step 9502, DLD pillars 9602 are etched, such as via various etching techniques (e.g., ALE), to shorten the height of DLD pillars 9602 as shown in
In step 9503, a layer with etchant-resistant and etchant-soluble components 9603 is deposited on DLD pillars 9602 as well as the exposed regions of silicon wafer substrate 9601 as shown in
In step 9504, a further CICE is performed on silicon wafer substrate 9601 below layer 9603 to expand the height of DLD pillars resulting in the structure shown in
In step 9505, a porous resistant layer 9604, such as porous HF-resistant layer, is optionally deposited on layer 9603 approximately at the middle height level of pillars 9602 to stabilize pillars 9602 as shown in
Referring to
In step 9702, a sacrificial material 9804 (e.g., polyvinyl alcohol (PVA)) is deposited along the walls of DLD pillars 9802 as shown in
In step 9703, DLD pillar caps 9803 are removed, such as via various etching techniques (e.g., ALE), as shown in
In step 9704, a cover plate 9805 with an etchant-resist film 9806 is bonded to the remaining top portion of DLD pillars 9802 as shown in
In step 9705, a sacrificial material etchant (e.g., deionized water) flow is performed to remove sacrificial material 9804 as shown in
Referring to
In step 9902, a sacrificial material 9804 (e.g., polyvinyl alcohol (PVA)) is deposited along the walls of DLD pillars 9802 as shown in
In step 9903, DLD pillar caps 9803 are removed, such as via various etching techniques (e.g., ALE), as shown in
In step 9904, a cover plate 9805 with an etchant-resist film 9806 is bonded to the remaining top portion of DLD pillars 9802 as shown in
In step 9905, an oxide etchant (e.g., dilute hydrofluoric acid) flow is performed to remove sacrificial material 9804 as well as portions of DLD pillars 9802 to make them thinner as shown in
In another embodiment, multiple layers of DLD devices are made using polysilicon deposition and CICE, as discussed below in connection with
Referring to
In step 10102, structural material 10203 is deposited in the recesses between DLD pillars 10202 as shown in
In step 10103, an encapsulation layer 10204 is deposited on structural material 10203 and DLD pillars 10202 as shown in
In step 10104, a layer of polysilicon 10205 is deposited on encapsulation layer 10204 as shown in
In step 10105, CICE is performed which etches portions of polysilicon layer 10205 forming pillars 10206 as shown in
In step 10106, structural material 10207 is deposited in the recesses between pillars 10206 as shown in
In step 10107, an encapsulation layer 10208 is deposited on structural material 10207 and pillars 10206 as shown in
It is noted that steps 10104-10107 may be repeated to increase the number of DLD stacks.
In step 10108, structural material 10207, 10203 is removed, such as via various etching techniques (e.g., CICE), as shown in
As shown in
In one embodiment, particles separated by the DLD device can be detected on-chip using spectroscopy methods, such as surface enhanced Raman spectroscopy (SERS). The SERS substrates are integrated into the DLD chip with porous silicon for filtration of the carrier fluids, such that the particles to be detected are on the porous silicon. The particle detection can be enhanced by patterning SERS enhancement structures, such as gold nanostructures. In one embodiment, the porous silicon for the SERS detectors is made using CICE, where the areas with porous silicon are doped using ion implantation. Alternatively, areas with porous silicon are patterned with a higher CICE catalytic activity catalyst, such as Pt, Pd or Ru, while areas with non-porous DLD pillar arrays are patterned with a lower CICE catalytic activity catalyst, such as Au.
The ability of creating nanostructures with vertical sidewalls and varying critical dimensions and shapes can be used for applications, such as metalenses and metasurfaces. In one embodiment, a metasurface includes arrays of pillars with varying silicon nanopillar shapes and geometries, such that the metasurface can focus light with specific wavelengths, such as near IR and mid IR. Additionally, arrays can also be made of oxidized porous silicon, which enables focusing of visible wavelengths.
In one embodiment, 3D integration methods, such as nMASC, are used for integration of III-V detectors in the metasurfaces.
The following discussion is based on
In one embodiment, the tool for pick and place assembly is used to assemble two or more fields, where at least one of the fields is a light sensitive pixel array, and at least a pair of fields are assembled one on top of another. In one embodiment, the tool for pick and place assembly is used to assemble two or more fields, where at least one of the fields is a light sensitive pixel array, and at least one of the fields is composed of logic circuits. In one embodiment, the tool for pick and place assembly is used to assemble two or more fields, where at least one of the fields is a light sensitive pixel array, and at least one of the fields is composed of logic circuits, and at least one of the fields is composed of memory circuits.
In one embodiment, the total thickness of the imager assembly is less than 25 μm. In one embodiment, groups of one or more pixels are addressed using logic circuit that physically lies underneath the pixels.
In one embodiment, one or more image sensors are curved into a spherical shape. The curvature of the imagers could be produced by pressurizing the front side of the imagers using a transfer chuck, while the backside of the imager conforms to a spherical mold. The mold could optionally be transparent. In one embodiment, the mold has adhesive on it to secure the curved imagers. The adhesive could be UV-curable. The UV curing could be performed from the backside of the transparent mold. In one embodiment, the adhesive is inkjetted prior to the imager curving. In one embodiment, multiple imagers are picked up from a source substrate, such as source substrate 103, and placed and curved onto a group of molds simultaneously. In one embodiment, the group of molds are made as a single contiguous part using a transparent polymer. In one embodiment, the edges of the imager dies are fixed during the assembly process. In one embodiment, the edges of the imager dies are unconstrained during the assembly process. In one embodiment, the imager has a petal-type structure. In one embodiment, the one or more edges of one or more petals reside behind an adjacent petal after the curving process.
In one embodiment, the throughput of DLD devices can be improved by stacking multiple DLD devices and running the samples in parallel. In one embodiment, the DLD devices are stacked using 3D integration techniques. In one embodiment, the 3D integration technique is n-MASC.
As a result of the foregoing, the principles of the present invention provide a means for utilizing the CICE process to effectively fabricate features in semiconductors using the equipment and process technologies for catalyst influenced chemical etching of the present invention.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2022/022151 | 3/28/2022 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63167462 | Mar 2021 | US | |
| 63174128 | Apr 2021 | US | |
| 63215807 | Jun 2021 | US |
