Patent Application
20120268899
The present invention relates to stacked microelectronic assemblies and methods of making such assemblies, and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip chip” designs, the front face of the chip confronts the face of a package substrate, i.e., chip carrier and the contacts on the chip are bonded directly to contacts of the chip carrier by solder balls or other connecting elements. In turn, the chip carrier can be bonded to a circuit panel through terminals overlying the front face of the chip. The “flip chip” design provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front face, such as disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977, the disclosures of which are incorporated herein by reference.
Certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding. Packages which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself are commonly referred to as “chip-sized packages.”
In addition to minimizing the planar area of the circuit panel occupied by microelectronic assembly, it is also desirable to produce a chip package that presents a low, overall height or dimension perpendicular to the plane of the circuit panel. Such thin microelectronic packages allow for placement of a circuit panel having the packages mounted therein in close proximity to neighboring structures, thus reducing the overall size of the product incorporating the circuit panel. There are, however, applications in which a relatively larger package is desired. These include instances in which a larger microelectronic element is to be packaged and in which a large fan-out area is needed to achieve connection to a larger array on a printed circuit board or the like. Many wafer-level packages present reliability issued in such relatively larger sizes due to an inherent increase in the effects of varying coefficients of thermal expansion among the components of the package. Such effects can also be visible in relatively smaller applications, particularly when contacts are placed in certain locations and when the package undergoes frequent heat-cycling.
Accordingly, further improvements would be desirable in the area of wafer-level packages or similar structures.
An embodiment of the present disclosure relates to a microelectronic package. The microelectronic package includes a microelectronic element including a first surface having contacts thereon, a second surface remote therefrom, and edge surfaces extending between the first and second surfaces. A reinforcing layer adheres to the at least one edge surface and extends in a direction away therefrom, the reinforcing layer not extending along the first surface of the microelectronic element. A conductive redistribution layer including a plurality of conductive elements extends from the contacts along the first surface and along a surface of the reinforcing layer beyond the at least one edge surface. An encapsulant overlies at least the reinforcing layer. The microelectronic element has a first coefficient of thermal expansion, the encapsulant has a second coefficient of thermal expansion, and the reinforcing layer has a third coefficient of thermal expansion that is between the first and second coefficients of thermal expansion.
In this embodiment the reinforcing layer can have a first surface substantially coplanar with the first surface of the microelectronic element, and the reinforcing layer can include a dielectric layer formed along portions of the first surface of the microelectronic element and the first surface of the reinforcing layer. The encapsulant can extend outward from at least one of the edge surfaces of the microelectronic element, and at least a portion of the second surface of the microelectronic element can be uncovered by the encapsulant.
The second coefficient of thermal expansion can be greater than the first coefficient of thermal expansion. The third coefficient of thermal expansion can be between 3 and 10 parts per million per degree Celsius (ppm/° C.). Further, the third coefficient of thermal expansion can be between 5 and 10 ppm/° C. In a variation of the embodiment, the microelectronic element can have a first modulus of elasticity, the encapsulant can have a second modulus of elasticity less than the first modules of elasticity, and the reinforcing layer can have a third modulus of elasticity that is between the first and second moduli of elasticity. The third modulus of elasticity can be between 5 and 8 GPa.
The microelectronic element can be substantially rectangular along the major surfaces thereof so as to include four edge surfaces, and the redistribution layer can include a fan-out area that extends outwardly from the microelectronic package in a plane parallel to the first surface of the microelectronic element. In such a package, the reinforcing layer can extend along a portion of each of the four sides of the microelectronic element and at least a portion of the fan-out area of the redistribution layer. Further, at least some of the conductive elements can be positioned in the fan-out portion in an array that surrounds the microelectronic element, and the reinforcing layer can extend outward such that the conductive elements within the fan-out layer at least partially overly the reinforcing layer.
The reinforcing layer can be of a substantially uniform thickness in a direction normal to the inside surface of the redistribution layer, and the redistribution layer can extend along the reinforcing layer. The reinforcing layer can further overlie the second surface and each of the edge surfaces of the microelectronic element. Alternatively, the reinforcing layer can taper from a first thickness above the redistribution layer adjacent the edge surface of the microelectronic element to a second thickness at an edge thereof remote from the microelectronic element, the first thickness being greater than the second thickness. The second thickness can be substantially zero. Further, the reinforcing layer can be wedge-shaped, forming an upper surface that is angled with respect to the first surface of the microelectronic element. Alternatively, the reinforcing layer can be generally parabolic in shape, forming a curved upper surface. The reinforcing structure can extend away from the edge surface to a first distance and the redistribution layer can extend away from the edge surface at a second distance grater than the first distance. At least some of the conductive elements can extend within the area of the redistribution layer beyond the reinforcing layer.
The contacts of the microelectronic element can be first contacts, and the conductive elements of the redistribution layer can form second contacts exposed on the redistribution layer. Further, the package can include a plurality of solder balls connected to at least some of the second contacts within an area of the redistribution layer that overlies the reinforcing layer. A plurality of conductive vias can be formed in the encapsulant from an outside surface thereof to a conductive feature of the redistribution layer, the conductive via being electrically connected to the conductive feature.
A microelectronic assembly according to an embodiment of the present disclosure can include a first microelectronic package according to the above embodiment. The assembly can further include a second microelectronic package having a first surface with a plurality of conductive features exposed thereon and a microelectronic element electrically connected to at least some of the conductive features. The second microelectronic package can be mounted to the first microelectronic package with the first surface facing the first microelectronic package, the conductive features of the second microelectronic package being electrically connected to the conductive vias of the first microelectronic package.
Another embodiment of the present disclosure can relate to a microelectronic package. The package includes a microelectronic element including first and second major surfaces and a plurality of side surfaces extending between the major surfaces, the first major surface having contacts formed thereon. The package also includes a redistribution layer having a dielectric layer with an inside surface, a portion of which extends along the first major surface of the microelectronic element, an outside surface with contact pads exposed thereon, and a plurality of conductive traces electrically connecting the pads to the microelectronic element. A reinforcing layer adheres to at least a portion of at least one of the side surfaces of the microelectronic element and extends along a portion of the inside surface of the dielectric layer from adjacent the microelectronic element, terminating at a location remote therefrom, along the side wall such that at least the first major surface of the microelectronic element is uncovered by the reinforcing layer. An encapsulation layer is formed over at least the microelectronic element and the reinforcing layer.
A further embodiment of the present disclosure relates to a microelectronic package. The microelectronic package includes a microelectronic element having first and second rectangular major surfaces and four side surfaces extending between the major surfaces. The package further includes a redistribution layer including an inside surface a portion of which extends along the first major surface of the microelectronic element and defining a fan-out area extending away from the microelectronic element. The redistribution layer further includes an outside surface with contact pads exposed thereon and a plurality of conductive traces electrically connecting the pads to the microelectronic element. A reinforcing layer adheres to a portion of each of the side surfaces of the microelectronic element and extends along a portion of the inside surface of the redistribution layer, within the fan-out portion, from adjacent the microelectronic element to a location remote therefrom. The reinforcing layer does not contact the first major surface of the microelectronic element. An encapsulation layer is formed over at least the microelectronic element and the reinforcing layer.
A microelectronic package according to any of the previously-described embodiments can be included in a system with one or more other electronic components electrically connected to the microelectronic package. Such a system can include a housing, the microelectronic package and the other electronic components mounted to the housing.
A further embodiment of the present disclosure relates to a method for making a microelectronic package. The method includes forming a reinforcing layer adhering to at least one edge surface of a microelectronic element. The microelectronic element has a first surface with contacts thereon, a second surface remote therefrom, and edge surfaces extending between the first and second surfaces. The reinforcing layer is formed so as to not extend along the first surface of the microelectronic element. Then an encapsulant is formed overlying the second surface of the microelectronic element and contacting the reinforcing layer. Conductive elements are then patterned extending from the contacts along the first surface and along a surface of the reinforcing layer beyond the at least one edge surface.
In such a method, the microelectronic element and the reinforcing layer can include a dielectric layer formed along at least a portion thereof such that the dielectric layer defines the first surface of the microelectronic element and the surface of the reinforcing layer. Portions of at least some of the conductive elements can be formed to define contact pads exposed on the dielectric layer, and the method can further include forming a plurality of solder balls on respective ones of the contact pads.
The method can be carried out such that the step of forming a reinforcing layer includes forming a plurality of reinforcing layers adhering to first edge surfaces of respective ones of a plurality or microelectronic elements, the method further including the step of dividing the package into a plurality of packages, each corresponding to one of the plurality of microelectronic elements and having a reinforcing structure and a portion of the redistribution layer.
The microelectronic element can have a first coefficient of thermal expansion, the redistribution layer can have a second coefficient of thermal expansion, and wherein the reinforcing layer can be formed by depositing a material having a third coefficient of thermal expansion that is between the first and second coefficients of thermal expansion. The third coefficient of thermal expansion can be between 3 and 15 ppm/° C.
The reinforcing layer can be formed extending away from the microelectronic element at a substantially uniform thickness. Alternatively, the reinforcing layer can be formed such that it tapers from a first thickness adjacent the microelectronic element to a second thickness at an edge thereof remote from the microelectronic element, the first thickness being greater than the second thickness. The redistribution layer can include a fan-out area that extends outwardly from the microelectronic element in a plane parallel to the major surfaces thereof to a first distance. The reinforcing layer can then be formed such that, upon formation of the redistribution layer, the reinforcing structure will extend along the fan out area at a distance of at least 500 μm.
The method of the present embodiment can be carried out such that the reinforcing layer is further formed along all of at least one edge surface and over the second major surface of the microelectronic element.
Further, the above method can include forming a plurality of conductive vias in the encapsulant from an outside surface thereof to a conductive feature of the redistribution layer. The conductive via can be electrically connected to the conductive feature. A microelectronic assembly can be formed from such a package by a method including mounting a second microelectronic package thereon. The first microelectronic package can have a microelectronic element contained therein and a plurality of external contact pads exposed on a first surface thereof. The first surface of the first microelectronic package can be positioned to face the outside surface of the encapsulant layer of the second package, and mounting the first microelectronic package can include electrically connecting the contact pads to the conductive vias of the second microelectronic package.
A further embodiment of the present disclosure relates to a method for making a microelectronic package. The method includes forming a reinforcing structure on an in-process unit having a foil defining a first surface and laminated on a carrier layer and at least one microelectronic element mounted on the foil. The microelectronic element has a first major surface on the foil, a second major surface remote therefrom at a first height and a plurality of edge surfaces extending between the major surfaces. The reinforcing structure is formed to adhere to a portion of at least one of the edge surfaces from a location adjacent the foil to a location remote therefrom at a second height that is less than the first height and to extend along a portion of the foil surrounding the microelectronic element. The method further includes forming an encapsulation layer over at least the reinforcing structure and a portion of the microelectronic element. The foil and carrier are then removed from the in-process unit to temporarily expose the first surface of the microelectronic element and a first surface of the reinforcing structure. A redistribution layer is then formed along at least the first surface of the reinforcing structure and the microelectronic element. The redistribution layer includes a dielectric material defining an inside surface contacting portions of the reinforcing structure and the microelectronic element and an outside surface having a plurality of contact pads exposed thereon. The redistribution layer further includes a plurality of conductive traces electronically connecting the contact pads to the microelectronic element.
With reference to
The microelectronic element 12 has a front surface 14, a rear surface 16 remote therefrom, and first and second edges 24, 26, extending between the front and rear surfaces. Electrical contacts 28 are exposed at the front surface 14 of the microelectronic element 12. As used in this disclosure, a statement that an electrically conductive element is “exposed at” a surface of a structure indicates that the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface toward the surface from outside the structure. Thus, a terminal or other conductive element which is exposed at a surface of a structure may project from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or depression in the structure.
An encapsulant layer 18 overlies rear surface 16 of microelectronic element 12 and can further overlie a portion of edge surfaces 24,26 and extend outward therefrom away from edge surfaces 24,26 to form a first surface 20 that is substantially coplanar with front surface 14 of microelectronic element 12. Encapsulant layer 50 can be formed from a dielectric material with insulating properties such as that described in U.S. Patent App. Pub. No. 2010/0232129, which is incorporated by reference herein in its entirety.
A reinforcing layer 50 adheres to at least a portion of edge surfaces 24,26 of microelectronic element 12 and extends outwardly therefrom and between a portion of microelectronic element 12 and encapsulant layer 18. Reinforcing layer 50 includes an inside edge surface 52 that adheres to an edge surface 24,26 of microelectronic element 12, a front surface 54 that can be substantially coplanar with both front surface 14 of microelectronic element 12 and first surface 20 of encapsulant layer 18. Reinforcing layer 50 further includes a rear surface 56 that can be in contact with encapsulant layer 18 and defines a thickness where it is spaced apart from front surface 54. The description of reinforcing layer including reference to the “front” and “rear” surfaces, as well as any other description of the relative position of elements used herein that refers to a vertical or horizontal position of such elements is done for illustrative purposes only to correspond with the position of the elements within the Figures, and is not limiting.
As shown in
In an embodiment, microelectronic element 12 includes additional edge surfaces in addition to edge surfaces 24,26 shown in
A redistribution layer 30 is formed along a common surface 31 defined by front surface 14 of microelectronic element 12, front surface 54 of reinforcing layer 50 and first surface 20 of encapsulant layer 18. Redistribution layer 30 includes a plurality of pads 32 with faces 33 exposed on package 10 for connection to a printed circuit board (“PCB”) or other microelectronic device. Pads 32 are electrically connected to contacts 28 of microelectronic element 12 by a plurality of traces 34. In the embodiment shown in
Redistribution layer 30 can be used to achieve a connection between the contacts 28 of microelectronic element 12 and another microelectronic structure, such as a PCB or the like, that has contacts in a different configuration than that of contacts 28. As such, pads 32 of redistribution layer 30 can be formed in an array that is different than that of contacts 28 and that can correspond to an array of a structure to which package is to be mounted. As shown in
Reinforcing layer 50 can extend to edge 58 at a distance such that at least a portion of the pads 32 in a row within fan-out layer closest to microelectronic element 12 overlie the at least a portion of the front surface 54 of the reinforcing layer 50. In an embodiment, reinforcing layer extends such that edge 58 is positioned between contact pads 32 within first and second rows at increasing distances from microelectronic element. Alternatively, edge 58 can be positioned such that a portion of reinforcing layer 50 overlies a portion of a contact pad 32 positioned within a second row of such a structure. In another embodiment, encapsulant 18 extends outward from microelectronic element 12 at a distance of at least 500 pm.
All of the structures present in microelectronic package 10 have their own coefficient of thermal expansion (“CTE”), meaning that they expand and contract in response to changes in temperature by varying amounts. In many applications of packaged microelectronic elements, for which microelectronic package 10 can be suited, the temperature of the package undergoes frequent, if not constant, heat cycling due to changes in the current flowing therethrough. Accordingly, frequent changes in size of the structures of packaged microelectronic elements are common. In forms of wafer-level packaging that lack the reinforcing layer as shown in the Figures of the present disclosure, a microelectronic element and encapsulant layer can intersect along coplanar edges that further intersect with a redistribution layer at the same location. The differences in CTE between these three structures can lead to various forms of failure for the package from changes in heat or heat cycling. Such failure can include, delamination of: the encapsulant from the microelectronic element, the redistribution layer from the microelectronic element, or the redistribution layer from the encapsulant. Failure can also include damage or fracture of traces within redistribution layer, or breaking of the joints between contact pads of the redistribution layer and solder balls used to join the contact pads to a PCB or the like. Failure of solder joints is particularly problematic when a pad is formed near or overlying the interface between an encapsulant and a microelectronic element. Failures of the type described have limited the size of microelectronic elements and of redistribution layer arrays because the effect of different CTE is dependent on the size of the elements. Accordingly, the effects have been reduced by keeping size small.
The incorporation of reinforcing layer 50 between microelectronic element 12, encapsulant 18, and redistribution layer 40 can reduce the effects of differing coefficients of thermal expansion among the elements of package 10 by forming reinforcing layer of a material with a CTE between at least two of the other elements of package 10. For example, the CTE of reinforcing layer 50 can be between that of microelectronic element 12 and encapsulant layer 18. Additionally or alternatively, the CTE of reinforcing layer 50 can be between that of microelectronic element 12 and redistribution layer 30 or between encapsulant layer 18 and redistribution layer 30. In an embodiment, the CTE of reinforcing layer 50 is between about 3 and 10 parts per million per degree Celsius (“ppm/° C.”). In another embodiment, the CTE of reinforcing layer 50 can be between about 5 and 10 ppm/° C. In yet another embodiment the CTE of reinforcing layer 50 can be between about 7 and 15 ppm/° C.
The structure and location of reinforcing layer 50 along with the material properties, such as CTE, can provide an additional step, or gradient, in material property change within package 10. Such a gradient can mitigate at least some of the effects of abrupt changes in material characteristics that have been problematic in other forms of wafer-level packaging. In the embodiment of
In another example, the effective CTE can be observed from the microelectronic element 12 when moving in the Y direction from a location adjacent reinforcing layer 30 to a location overlying reinforcing layer 50 and continuing to a location overlying encapsulant layer 18. In this example, the effective CTE can change from a first level adjacent the reinforcing layer 30 to a second, higher level when overlying reinforcing layer 50. The effective CTE can change to a third, still higher level when overlying encapsulant layer 18.
In the embodiment of
Reinforcing layer 50 can be structured to provide a gradient in other material characteristics in addition to or instead of CTE. For example, the modulus of elasticity of reinforcing layer 50 can be between that of encapsulant layer 18 and microelectronic element 12 or between that of encapsulant layer 18 and redistribution layer 30. In such an embodiment, reinforcing layer 50 can have a modulus of elasticity of between 5 and 8 GPa.
The embodiment shown in
Second package 60 can be mounted on package 10 by bonding solder balls to upper contact pads 70 of package 12 and to pads 63, which are electrically connected to second microelectronic element 62. Second package 60 can be any type of package structured to mount to another package such as package 10. In the embodiment shown, second package 60 is similar in structure to package 12 in that it is a wafer-level package with a reinforcing layer 66 positioned within a portion of an interface between microelectronic element 62, encapsulant 64 and redistribution layer 68, although other embodiments are possible. The stacked packages 10,60 are then mounted on a PCB 80 having contact pads 82 exposed at a surface thereon by solder balls bonded to contact pads 82 and pads 32.
A method for making a microelectronic package 10, such as that of
In
Package 10′ is removed from foil 84 and carrier 82 in
The metalized vias, if included, the traces 34, and pads 32 can be formed at the same time. The metalized vias (not shown), traces 34, and pads 32 can be formed by depositing a metal into the openings, if present, leading to the contacts 28 of microelectronic element 12 and onto common surface 31. In particular, the traces 34 can be formed by selectively depositing metal onto trace areas of common surface 31. The process of depositing metal onto trace areas can include placing a patterned seed layer on common surface 31 and then placing a photo resist mask on the seed layer. The metal may be deposited using any suitable process. Suitable depositing processes include, but not limited, spin-coating, laminating, printing, dispensing or molding. Alternatively, traces 34 can be formed by patterning the plated metal on common surface 31. Pads 32 can be formed at the same time as traces 34 in the same manner. In
As shown in
In
A reinforcing layer according to the embodiments described herein can further be incorporated into alternative forms of wafer-level packages, including ones with stacked microelectronic elements. An example of such a package is described in co-pending, commonly-assigned, U.S. patent application Ser. No. 12/953,994, the entire disclosure of which is hereby incorporated by reference herein.
The microelectronic assemblies described above can be utilized in construction of diverse electronic systems, as shown in
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
