Patent Application
20130320521
The invention relates to semiconductor structures and, more particularly, to a releasable buried layer for 3-D fabrication and methods of manufacturing.
Standard interposer fabrication for 3-D stacking makes use of a complex process that includes both front and backside wafer level processing, through-Si vias to connect the front side to the backside, and a “handle-wafer” methodology that protects the front side during the backside wiring fabrication. In known processes, the backside silicon is removed by a physical chemical mechanical planarization process, reducing the full wafer thickness from about 750 um down to 50-100 um before the handle-wafer is applied and the backside wiring is formed while the wafer is still intact. Upon completion of backside wiring and bumping processes, the handle wafer is removed just prior to segmenting of the wafer into individual interposer units by a dicing process.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
In an aspect of the invention, a method of forming an interposer structure comprises forming a carbon rich dielectric releasable layer over a wafer. The method further comprises forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further comprises bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.
In an aspect of the invention, a method comprises providing a releasable layer over a Si substrate. The method further comprises forming wiring layers upon the releasable layer. The method further comprises bonding the wiring layers to a substrate using reflow processes. The releaseable layer is formed to withstand semiconductor back end of the line processing of greater than 300° C. without detaching from the Si substrate. The releaseable layer is formed to detach from the Si substrate after BEOL processing.
In an aspect of the invention, a structure comprises a carbon rich low-k dielectric releasable layer disposed between an Si substrate and wiring layers. The structure further comprises at least one bond pad connecting wiring in the wiring layers to a solder bump connection.
In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the releasable buried layer for 3-D fabrication, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the releasable buried layer for 3-D fabrication. The method comprises generating a functional representation of the structural elements of the releasable buried layer for 3-D fabrication.
The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
The invention relates to semiconductor structures and, more particularly, to a releasable buried layer for 3-D fabrication and methods of manufacturing. In embodiments, the present invention makes use of a thin-film SiCOH low-k dielectric material as a back end of the line (BEOL) releasable layer that is both process and thermally compatible with standard Si BEOL processes, e.g., can withstand temperatures of above 150° C. and even above 300° C. These BEOL processes can be, for example, used to fabricate aluminum and Cu BEOL multilevel wiring structures that are used to build interposers and other structures in 3-D packaging designs. SiCOH dielectrics can be used as high-performance insulating materials in BEOL technologies, which can withstand temperatures exceeding 500° C., for example.
In embodiments, a releasable dielectric layer can be formed during a PECVD process in which carbon-containing film precursors are mixed in real time during the deposition process to intentionally create a carbon-rich layer at the interface of such material, e.g., an oxide or other insulator layer. It has been found that this carbon rich interface performs very poorly in adhesion testing, and accordingly is a suitable releasable layer for a BEOL stack built as part of an interposer or 3-D process design. For example, advantageously, the carbon rich layer enables fabrication of a 3-D interposer multilevel wiring component using standard BEOL processing, without the need for through-Si vias, wafer backside processing or the use of handle wafers. This enables a significant cost and process complexity reduction with respect to existing processes for interposer fabrication.
A releasable layer 16 is formed on the insulator layer 14 (or optionally directly on the wafer 12). In embodiments, the releasable layer 16 is a carbon rich ultra low-k dielectric material. In embodiments, the carbon rich ultra low-k dielectric releasable layer 16 can be deposited to about 10 nm to about 20 nm; although other dimensions are also contemplated by the present invention. In embodiments, the specific film thicknesses and carbon content can be optimized. For example, a carbon content of the releasable layer 16 can be about anywhere from 20% to upwards of 75% relative to other constituent components in the releasable layer, e.g., oxygen, Si and hydrogen components.
In specific processes, the releasable layer 16 can be formed using CVD processes. Specifically, in embodiments, the releasable layer 16 is p-SiCOH film comprised of BCHD (bicycloheptadiene) and DEMS (diethoxymethylsilane). During the deposition process, the chamber is flooded starting at the initial phase of deposition, i.e., time T0, with carbon-containing gas. In embodiments, the flow rate of the carbon can be optimized, depending on the required adhesive properties of the releasable layer 16. These adhesive properties can be dependent on many factors including, but not limited to, BEOL processes (including reflow of the solder bump during packaging), and underlying layers to the releasable layer (i.e., whether the releasable layer is provided on an oxide film, nitride film, directly on the wafer, itself, etc.). For example, the carbon containing precursor can preferably be initially spiked to provide a higher concentration of carbon deposition at the interface.
It should be understood by those of ordinary skill in the art that under normal deposition conditions, the turn-on of BCHD is delayed to allow the formation of a “graded layer” for the purpose of improved adhesion; however, in contrast, in the present invention the BCHD is turned on initially at time T0 to form a carbon rich dielectric releasable layer 16. It has been found that by forming a carbon rich interface with, e.g., the insulator layer 14 or with the wafer 12, the interface is of sufficient strength to hold together through BEOL processing, but will delaminate under an elevated stress condition during solder flow processes.
Alternate embodiments of the releasable layer 16 may include NBlok on both top and bottom of the carbon rich ultra low-k dielectric material 16 film or even a thin layer of conventionally formed p-SiCOH material sandwiched between two carbon rich ultra low-k dielectric material films. Accordingly, the present invention contemplates any structure that makes use of the carbon rich ultra low-k dielectric material 16 as a releasable layer.
A dielectric material 20 can then be deposited on the first level metallization 18. The dielectric material 20 can be a low-k dielectric material, formed in a conventional manner. It should be understood by those of skill in the art, that the dielectric material 20 would include a very low or zero concentration of carbon, to ensure quality adhesive properties, particularly during BEOL processes. Thereafter, in subsequent processes, contacts 22 and additional wiring level metallization 24 can be formed using conventional deposition, lithography, etching processes, within subsequent layers of the dielectric material 20. As these subsequent processes are conventional processing steps, no further explanation is required in order for one of skill in the art to understand and practice the present invention. The additional wiring level metallization 24 can be any passive device such as, for example, capacitors, inductors or wiring.
After a top level metallization 26 is formed (either through an additive or subtractive process), a passivation layer 28 can be deposited using conventional deposition processes, e.g., CVD. In embodiments, the top level metallization 26 can be aluminum, in contact with a lower wiring layer. The passivation layer 28 can be, for example, photosensitive polyimide (PSPI).
Still referring to
A solder bump 32 can then be formed in contact with the UBM 32. In embodiments, the solder bump 32 can be a lead free solder bump, formed using controlled collapse chip connection (C4) processes. As should be understood by those of ordinary skill in the art, the releasable layer 16 will provide adequate adhesion with the wafer 12 during these BEOL processes.
In
In embodiments, the reflow temperature can range from about 375° C. to about 220° C. In specific embodiments, the cool down ramp rate can be, for example, greater than 3° C./sec., with a reflow temperature of 220° C. to 100° C. As another example, cool down ramp rate could be less than 2° C./sec., starting with a temperature of about 100° C. to ambient. As representatively shown in
As should now be understood by those of skill in the art, the releasable layer makes it possible to fabricate a stackable interposer structure using conventional high-temperature BEOL processing, while simplifying standard processing to a significantly more favorable cost point. For example, the releasable layer placed at the bottom of the wiring stack can serve as the I/O level for connection to additional components each with their own solder bumps. In further aspects of the present invention, it is possible to include the releasable layer beneath a polycrystalline Si layer in the case of an SOI-like substrate, which would enable the formation of Si-based devices beneath the BEOL metallization, in the manner of a standard semiconductor chip. Accordingly and advantageously, the present invention that provides a releasable layer composition and thickness to ensure proper adhesive strength during wafer level BEOL and die level chip-join processing. On the other hand, the releasable layer composition is optimized to release from the chip during chip-join and post-clean processing. Thus, it is now possible to use of advanced Si technology BEOL processing for the formation of the interposer layer. This includes advanced ultra-low K dielectric insulating materials and Cu BEOL at very tight pitch, which in turn allows for a high wiring density. And, advantageously, no through silicon via structure or substrate backside processing is needed.
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990.
Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
