Patent Application
20130256883
Various aspects of the disclosure relate generally rotated semiconductor device Fan-Out Wafer Level packages and to methods of manufacturing rotated semiconductor device Fan-Out Wafer Level packages.
Today, fabrication of integrated circuit devices typically includes packaging of the integrated circuits or semiconductor devices. Reliability of the packaged device is always a concern, especially with respect to the integrity of the chip/package interconnects.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the disclosure of the invention are described with reference to the following drawings, in which:
In various aspects of the disclosure, semiconductor device arrangements may be provided that may include at least one semiconductor device within a Fan-Out Wafer Level package, in which the semiconductor device is rotated with respect to the edges of the package. The degree of rotation with respect to the edge of the package may include a number of angles, including 22.5°±5°, 22.5°±10°, 45°±5° or 45°±10°, for instance. The rotation of the semiconductor device may decrease the semiconductor device material included in areas with a high difference in coefficient of thermal expansion (silicon to board) in the region of the distance to neutral point from the center of the semiconductor device to the corner of the package, allowing for better thermal cycling performance. The rotated semiconductor device may also allow for improved interconnect routing between the semiconductor device and the underlying ball grid array. Rotation of the semiconductor device may further allow for reduced distance from bond pads located on the semiconductor device corner to the package edge, allowing for shorter interconnects and better electrical performance. Rotation of the semiconductor device may allow for improved routing in package-on-package structures. Rotation of the semiconductor device may also allow for improved usage of the space available in the chip package, allowing for the incorporation of two or more semiconductor devices into a package that previously only accommodated one semiconductor device.
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects of the disclosure in which the invention may be practiced. Other aspects of the disclosure may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects of the disclosure are not necessarily mutually exclusive, as some aspects of the disclosure can be combined with one or more other aspects of the disclosure to form new aspects of the disclosure. The following detailed description therefore is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Various aspects of the disclosure are provided for devices, and various aspects of the disclosure are provided for methods. It will be understood that basic properties of the devices also hold for the methods and vice versa. Therefore, for sake of brevity, duplicate description of such properties may be omitted.
The terms “coupling” or “connection” as used herein may be understood to include a direct “coupling” or direct “connection” as well as an indirect “coupling” or indirect “connection”, respectively.
The terms “disposed over”, “located over” or “arranged over” as used herein are intended to include arrangements where a first element or layer may be disposed, located or arranged directly on a second element or layer with no further elements or layers in-between, as well as arrangements where a first element or layer may be disposed, located or arranged above a second element or layer with one or more additional elements or layers between the first element or layer and the second element or layer.
The term “rotated semiconductor device” as used herein may be understood to indicate that one or more semiconductor devices are rotated about an axis with respect to an enclosing package. For example, in accordance with some aspects of the disclosure, an edge of a semiconductor device may be rotated 45 degrees, ±5 degrees with respect to the edges of the underlying package, resulting in a flat edge of the semiconductor device being directly opposite a corner of the package. However, the term “rotated semiconductor device,” as used herein, includes rotation about any axis or corner of the semiconductor device, and is not intended to imply only rotation about a central axis of the semiconductor device or the package.
The term “bond pad” as used herein may be understood to include, for example, pads that will be contacted in a bonding process (for example, in a wire bonding process, in a flip chip process or in a ball attach process) of a semiconductor device or chip. In case that a ball attach process is applied, the term “ball pad” may also be used.
The term “redistribution trace” as used herein may be understood to include, for example, conductive lines or traces disposed over a semiconductor device's or wafer's active surface and used to relocate a bond pad of the semiconductor device or wafer. In other words, a bond pad's original location over the semiconductor device or wafer may be shifted to a new location by means of a redistribution trace which may serve as an electrical connection between the (relocated) bond pad at the new location and an electrical contact (or pad) at the original location over the semiconductor device or wafer.
The term “redistribution layer (RDL)” as used herein may be understood to refer to a layer including a plurality or set of redistribution traces used to relocate (“redistribute”) a plurality of bond pads of a semiconductor device or wafer.
The term “reconstitution structure” as used herein may be understood to include, for example, a structure that may be formed (e.g. cast) around a semiconductor device to serve as an artificial wafer portion where, for example, additional bond pads may be placed (for example, in addition to bond pads located over the semiconductor device). Bond pads located over the reconstitution structure may be electrically connected to the semiconductor device (e.g. to electrical contacts or pads of the semiconductor device), for example by means of redistribution traces of a redistribution layer. Thus, additional interconnects for a semiconductor device may be realized over the reconstitution structure (so-called “fan-out design”).
The term “embedded wafer level ball grid array (eWLB)” may be understood to refer to a packaging technology for integrated circuits. In an eWLB package, interconnects may be applied on an artificial wafer made of semiconductor device or chips (e.g. silicon semiconductor device or chips) and a casting compound. eWLB may be seen as a further development of the classical wafer level ball grid array technology (WLB or WLP: wafer level package). For example, all process steps for the generation of the package may be performed on the wafer. This may, for example, allow, in comparison to classical packaging technologies (e.g. ball grid array), the generation of very small and flat packages with improved electrical and thermal performance at decreased cost.
The term “thermal cycles to failure” may be understood to refer to a series of tests where a package or device is exposed to repeated heating and cooling cycles (“thermal cycling”) until the device or package experiences electrical or mechanical failure, often through fractures in the packaging or the electrical conductors of the package.
The term “distance to neutral point” (DNP) may be understood to refer to the distance from an input/output location in the package, such as a bond pad or ball pad, to the center of the package. For a symmetricly-oriented package, the neutral point is also the geometric center of the semiconductor device.
In WLB technologies, which are built on a wafer (e.g. silicon wafer), the interconnects (typically solder balls) usually fit on the chip (so-called fan-in design). Therefore, usually only chips with a restricted number of interconnects for a given distance between the interconnects may be packaged.
In contrast thereto, the eWLB technology may allow the realization of semiconductor device or chips with a high number of interconnects. Here, the package may be realized not on a semiconductor wafer (e.g. silicon wafer) as for classical Wafer Level Package, but on an artificial wafer. To this end, a front-end-processed wafer (e.g. silicon wafer) may, for example, be diced and the singulated chips may be placed on a carrier. The distance between the chips may be chosen freely, but may be typically larger than on the (silicon) wafer. The gaps and the edges around the chips may be filled with a casting compound to form a wafer of substrate of other format. After curing, an artificial wafer containing a mold frame around the semiconductor device for carrying additional interconnect elements may be realized. After the build-up of the artificial wafer (the so-called Reconstitution), electrical connections from the chip contacts or pads to the interconnects may, for example, be realized in thin-film technology, like for other classical Wafer Level Package. The electrical connections formed therein are referred to as the “redistribution traces.”
With eWLB technology an arbitrary number of additional interconnects may, in principle, be realized on the package in an arbitrary distance (so-called fan-out design). Therefore the eWLB technology may, for example, also be used for space sensitive applications, where the chip area would not be sufficient to place the needed number of interconnects in a realizable distance. Because there are a finite number of connections which need to be made from a given semiconductor device, this means that there will be a relative depopulation of bond pads from the center of the package area toward the edges of the package.
An eWLB may be seen as one example of a so-called fan-out wafer level package. In addition to eWLB, other types of fan-out wafer level packages are known, for example fan-out wafer level packages that are not cast-based or include so-called embedding technologies.
There are a plurality of redistribution wiring structures 127 embedded throughout 110, as shown in expanded
Also shown in
As discussed above, and as illustrated in
The arrangement shown in
In the fabrication of packages, such as for example an embedded wafer level ball grid array (eWLB), a number of different materials must be used. Semiconductor device 101 is typically silicon, reconstitution structure 110 is often predominantly a polymeric mold compound, redistribution layer 127 is a metal or other conductor, and the underlying printed circuit board (PCB) is a metal encased in a laminate polymer. Each of the aforementioned structures has associated with it a unique coefficient of thermal expansion (CTE), which is an inherent property of the material(s) used to form the structure(s). Due to the CTE associated with the various materials, the individual structures will expand or contract in size differently with variations in temperature. Because the CTEs for the various structures are different, the structures will move slightly relative to each other as the temperature of the local environment changes. Expecially with respect to movement between the package and the board, this causes stress in the board elements, especially in the various interconnect elements such as the solder ball connections, leading to solder fatigue in the solder ball. Such movement can then lead to a failure of the packaged device. This is particularly problematic when the packaged device is subjected to thermal cycling.
By way of example, the CTE for a typical silicon-based semiconductor device is in the range of 3 ppm, the CTE for a highly-filled polymeric mold compound is 7 ppm, and the CTE for the underlying PCB is approximately 16 ppm, for example. These differences in CTE will cause stress in the various interconnects upon temperature cycling, where the magnitude of the stress between any two components will increase with increasing differences in CTE between the components.
Another factor relating to the stresses upon the various interconnects in a package is the distance to neutral point (DNP), which is measured from the center of the semiconductor device to the location of a solder ball. The DNP is mainly important to any position where there is a solder ball in the package—the higher the DNP, the higher the stress in the solder ball. For instance, for the purposes of this aspect of the disclosure and with reference to
As illustrated in
In another aspect of the disclosure, this may lead to a decrease in failures with thermal cycling because there is less of a CTE mismatch in the corner region, where there is a higher interconnect density.
Moreover, in another aspect of the disclosure, following rotation of semiconductor device 201 the corners 265 of semiconductor device 201 have been translated to an area nearer to the outer edge of package 240. This, of course, increases the portion of total DNP associated with semiconductor device material 250, and hence the amount of semiconductor material, that falls within edge 240 of package 200. This leads to some increase in stress in this area due to a net increase in the CTE mismatch in the edge 240 region of package 200. However, the increase is small compared to the decrease in stress associated with the corner position. This leads to an overall increase in reliability for the package.
Note that, although a rotation of approximately 45 degrees is used in tOis example, in another aspect of the disclosure, the rotated package design is not limited to this angle. Indeed, the angle may vary widely depending on application, and thus the current illustration should not be seen as limiting. In an aspect of the disclosure, the angle of rotation may vary, for example, between 45±5°. This orientation may be beneficial, for instance, in the case when the semiconductor device area to package size ratio is relatively high, in other words when there is a relatively small semiconductor device in a relatively large package. In a further aspect of the disclosure, an angle of 45±10° may be appropriate.
In contrast, an angle of 22.5°±5° may be more beneficial when the semiconductor device to package area ratio is relatively low, in other words when the semiconductor device is relatively large compared to the package. In a further aspect of the disclosure, an angle of 22.5°±10° may be appropriate
Moreover, in another aspect of the disclosure, although an approximately square semiconductor device is shown in the Figures, the semiconductor device may take any shape used in the art, and thus the shape of the semiconductor device is in no way limiting with respect to this disclosure.
Further, the axis of rotation of the semiconductor device is not limited to the center of the semiconductor device. Rotation about one corner of semiconductor device 301 is another aspect of this disclosure, as shown in
In another aspect of the disclosure, rotation of semiconductor device 401 within package 400 leads to a decrease in the distance from the chip corner to the package edge, as is illustrated in
Moreover, as further illustrated in
The advantage of a rotated semiconductor device placement is illustrated in
Yet another advantage of the current rotated semiconductor device eWLB package is illustrated in
Semiconductor device arrangements in accordance with some aspects of the disclosure described herein (for example, the semiconductor device arrangement in accordance with the embodiment shown in
A person skilled in the art will recognize that combinations of the above exemplary embodiments may be formed. For example, a package-on-package configuration as disclosed in
Semiconductor device arrangements in accordance with some aspects of the disclosure described herein may, for example, also be used in connection with a flip chip process.
While the invention has been particularly shown and described with reference to specific aspects of the disclosure, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
