Patent Application
20080116584
This invention relates generally to interconnected electronic components and, in specific, embodiments to self-aligned through-vias for chip stacking.
One of the goals in the fabrication of electronic components is to minimize the size of various components. For example, it is desirable that hand held devices such as cellular telephones and personal digital assistants (PDAs) be as small as possible. To achieve this goal, the semiconductor circuits that are included within the devices should be as small as possible. One way of making these circuits smaller is to stack the chips that carry the circuits.
A number of ways of interconnecting the chips within the stack are known. For example, bond pads formed at the surface of each chip can be wire-bonded, either to a common substrate or to other chips in the stack. Another example is a so-called micro-bump 3D package, where each chip includes a number of micro-bumps that are routed to a circuit board, e.g., along an outer edge of the chip.
Yet another way of interconnecting chips within the stack is to use through-vias. Through-vias extend through the substrate thereby electrically interconnecting circuits on various chips. Through-via interconnections can provide advantages in terms of interconnect density compared to other technologies. While there is, in theory, no limit as to the number of chips that can be stacked, the ability to remove heat from inside the stack can limit the number of chips as a practical matter.
During the stacking of chips on each other, it is important that the through-vias and bond pads on the chips are aligned. Misaligned vias and bond pads can result in degraded electrical conductivity, poor reliability and even the absence of electrical connections and functionality between layers.
Conventionally, correctly aligned features are ensured by specifying fine alignment tolerances. This can result in increased cost due to more expensive equipment and/or lower throughput. This problem gets exacerbated when very fine pitch vias are used, since the alignment tolerance requirement becomes even more critical. However, being able to bond dies with fine pitched vias accurately and reliably can be a huge competitive advantage, both in terms of cost and performance.
As a result, what is needed is a way of improving the alignment tolerance of through-vias in 3D chip stacking.
An electronic component includes a first component and a second component, each having a surface that includes a plurality of exposed contacts separated by an insulating material. A sandwich layer is disposed between the surface of the first component and the surface of the second component. The surface of the first component is then attached to the surface of the second component with the sandwich layer therebetween. The sandwich layer forms conductive areas between contacts of the first component and contacts of the second component and forms an insulator between the conductive areas.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
a and 1b are cross-sectional views illustrating the goal of stacking components;
a and 2b illustrate cross-sectional views of a first embodiment of the invention;
a and 3b illustrate cross-sectional views of a second embodiment of the invention;
a and 6b illustrate cross-sectional views of an alternate embodiment of the invention;
a and 8b illustrate an embodiment that implements a redistribution layer.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The present invention will be described with respect to preferred embodiments in a specific context, namely a stack of semiconductor chips interconnected by through-vias. The invention may also be applied, however, to other interconnected components. For example, a chip or chips can be coupled to a board. In another example, components other than semiconductors can be used.
A first embodiment will now be described with respect to
Referring first to
In the preferred embodiment, the components 10 and 20 semiconductor components, e.g., wafers or chips (dies). For example, both components 10 and 20 can be semiconductor wafers, e.g., wafer-on-wafer stacking, or both components can be chips, e.g., chip-on-chip stacking. In another example, one component is a wafer while the other component is a chip, e.g., chip-on-wafer stacking. The following discussion applies equally to each of these combinations.
Further, it is noted that the drawings are provided for simplistic illustration of concepts of the present invention. It is understood that many more than two vias 12/22 and/or pads 14/24 will be included in a typical integrated circuit. Further, these contacts will not typically cover the entire surface area of the chip, although they certainly could. In many device configurations, the vias and pads are formed in the periphery of the chip (e.g., for logic components) or in the center of the chip (e.g., for memory components such as dynamic random access memories).
a and 2b illustrate a first embodiment that can solve the problem of misalignment of the electrical connections. As shown in
In the embodiment of
Referring now to
To form the self-aligned local interconnects (and intervening insulating material), the components are typically heated while in contact. It is desirable that the material 30 not require very high temperatures for the formation of the conducting 32 and insulating 34 compounds. For example, the sandwich layer can be heated at a temperature not greater than about 400° C., preferably between about 250° C. and about 350° C.
Titanium is one example of a material that can be used for the sandwich layer 30. Titanium is very reactive and is commonly used to form silicides and glue layers. In the case of semiconductor components, titanium will react with polysilicon, aluminum, copper or tungsten contacts to create the conductive interconnects 32. It will also react with typical passivation layers such as silicon dioxide or silicon nitride to create titanium oxides, oxynitrides and silicates. As additional examples, the sandwich layer material can be other metals such as tantalum or other materials such as conductive polymers, manganese, platinum, magnesium or copper.
Of the types of stacked chips which can be formed, one example would be to stack several memory chips on each other. The chips could be DRAM, SRAM, NAND or NOR Flash chips or any combination of these dictated by the product application. In the case of memory chips, the metallization and contact material could be aluminum, the passivation layers could be silicon dioxide and silicon nitride, the sandwich layer could be titanium and the isolation material could be silicon dioxide or a polymer such as benzocyclobutene (BCB).
In another example, a logic chip such as a microprocessor or a digital signal processor (DSP) could be stacked with other chips such as memory or analog chips. In such a case, the metallization material could include copper and tantalum layers, whereas the other layers could be the same as before. In a third example, a CMOS chip (logic or memory) could be combined with a non-CMOS component such as a MEMS or a biosensor device. In such a case, the metallization material could also include a conductive paste such as solder. The other materials would remain similar to the two examples above.
In the embodiments described thus far, the sandwich layer 30 interacts with both the conductors 12/14/22/24 and the insulators 16/26. This feature is not necessary. If the material 30 is a conductor 32 as deposited, then it only needs to react with the insulator 16/26 to become an insulator 34. Likewise, if the material 30 is an insulator 34 as deposited, then it only needs to react with the conductors 12/14/22/24 to become a conductor 32.
In the case where the components 10 and 20 are aligned in a face-to-face manner, as illustrated in
a and 3b illustrate the example where the active-side surface of the second component 20 is attached to the back-side surface of the first component 10. The active-side surface is denoted in these figures by the inclusion of the region 18 (28), which is labeled “active circuits.” This configuration is desirable when identical components are being used since the through-vias will naturally line-up, thus avoiding the need for redistribution layers, customization of chips for the top and bottom, or careful design of via placement.
In the example illustrated in
A typical semiconductor chip includes a silicon (or other semiconductor) back-side surface. Unless the layer 30 can react with silicon to create an insulator, an additional material will be added. Accordingly,
The concepts of the present invention are not limited to the stacking of only two components.
Thus far, the invention has been described only in terms of stacking of semiconductor components. In other embodiments, other components can be stacked. For example, the first component 10 can be a semiconductor chip 10 while the second component 20 is a board. Examples of this type of configuration are illustrated in
Referring first to
b illustrates an example where two chips 10 are mounted upon each other (either face-to-face or in any other configuration). The stacked assembly is then mounted on a board 20. The board 20 includes pads 24 and through-vias 22, which in this case include horizontal interconnects. As a point of illustration, solder balls 50 are included on the surface of component 20 that is opposite of where the stack is mounted. Combinations of the embodiments of
In the preferred embodiment, at least one, if not both, of the stacked components are semiconductor chips. The fabrication of these chips will now be described with respect to the flow chart 60 of
As illustrated by box 62, active circuitry is formed at a surface of a semiconductor wafer. The circuitry can include transistors, resistors, capacitors, inductors or other components used to form integrated circuits. For example, active areas that include transistors (e.g., CMOS transistors) can be separated from one another by isolation regions, e.g., shallow trench isolation. This processing can be referred to as front-end or front end of line (FEOL).
As illustrated by box 64, the components formed during the front-end processing can then be interconnected by metallization, sometimes referred to as back end of line (BEOL). Metallization is formed over the active circuitry and in electrical contact with the active circuitry. The metallization and active circuitry together form a completed functional integrated circuit. In other words, the electrical functions of the chip can be performed by the interconnected active circuitry. In a logic chip, the metallization may include many layers, e.g., nine or more, of copper. In other devices, such as DRAMs, the metallization may be aluminum. In other examples, other materials can be used. In fact, the metallization need not actually be metal if other conductors are used.
Referring now to box 66, a final passivation layer is formed over the metallization layer. The final passivation layer can include more than one layer of material, the topmost layer being interactive with the sandwich layer, if desired. Examples of materials that can be used for the final passivation layer are silicon dioxide and silicon nitride. The final passivation layer includes openings to expose the contact areas.
The formation of the through-vias is illustrated by box 68. A plurality of through-vias can be formed through the semiconductor wafer, e.g., extending from the front-side surface to the back-side surface or extending deep enough to be exposed after the backside grinding (box 72). For example, via holes are etched to a depth of about 10 μm to about 100 μm. These holes are then lined with an insulator, such as an oxide or a polymer. After forming a barrier (e.g., Ta, TaN, Ta/TaN, Ti, TiN, Ti/TiN, as examples), a copper seed layer is formed followed by plated copper. Other processes and/or materials could alternatively be used. The through-vias are electrically coupled to the contact areas.
The sandwich layer 30 can then be formed over the final passivation layer and the exposed contacts, as shown by box 70. In one example, a blanket layer of conductive material is deposited over the final passivation layer and over the exposed contact area. This material may be any of the materials discussed above.
Optionally, the wafer may be thinned from the back-side, e.g., through grinding, as indicated by box 72. The advantage of thinning the wafer (or chip, if the wafer has already been singulated) is to create a lower profile component and to shorten the length of the through-vias, which enhances the electric properties. In addition, when the wafer is thinned, the through-vias can be formed by etching via holes down to a depth less than the thickness of the wafer, which saves processing time.
Box 74 is provided to indicate that the completed component can then be stacked with other components. This process can be performed as described above.
In each of the embodiments discussed above, the interconnects 32 are formed in a self-aligned manner. In this process, the two contacts to be electrically connected should overlap at least a small amount. Small misalignments are tolerable. In other situations, it is desirable to electrically connect contact areas that are not close to one another. For example, this technique is very useful when using different types of chips. For example, a memory chip or chips can be stacked with a controller chip.
In an extension of concepts of the present invention, it is possible to form a redistribution layer. In this case, a material that reacts with the previous layer to form a conducting compound is deposited prior to the deposition of the sandwich layer 30. The second layer is then patterned to form the redistribution wiring scheme.
b shows an exemplary cross-section (which does not match up with the plan view of
Any of the embodiments discussed above can be implemented using the redistribution scheme discussed here.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
