Patent Application
20110233786
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-068407, filed on Mar. 24, 2010; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.
Since portable electronic equipment such as cellular phones are being manufactured smaller and thinner in size, the area of a semiconductor device mounting region is becoming smaller and the height is becoming smaller too. Therefore, a so-called double-sided mount type semiconductor device, in which semiconductor chips are mounted on both sides of a single substrate, is used. For example, the double-sided mount type semiconductor device is manufactured as follows. First, a wiring layer is formed on a support substrate, and a semiconductor chip is mounted on the front surface of the wiring layer. Then, the support substrate is removed, and another semiconductor chip is mounted on the rear surface of the wiring layer.
In the above-described semiconductor device manufacturing process, it is demanded that the support substrate is removed easily in a short time without causing a defect in the semiconductor chip or the wiring layer while it is made possible to repeatedly use the support substrate. As a method of removing the support substrate, there is a known method that uses a separation layer formed of a thermoplastic resin. The separation layer formed of the thermoplastic resin is formed on the support substrate, and a wiring layer having an organic insulating film and a metal wiring is formed on it. After the semiconductor chip is mounted on the wiring layer and sealed with a resin, shearing is conducted while heating the separation layer to separate a structure comprised of the wiring layer, the semiconductor chip and the sealing resin layer from the support substrate.
A method of shearing the separation layer while heating has an advantage that the support substrate can be removed easily in comparison with, for example, a method that melts or burns the separation layer at a high temperature. In addition, a thermal adverse effect on the semiconductor chip or the wiring layer is small. But, when the separation layer formed of the thermoplastic resin is sheared to separate the support substrate, a stress concentrates on the edge portions of the wiring layer, and the wiring layer might peel off. In addition, when the wiring layer and the sealing resin are cut off together to singulate a semiconductor device after plural semiconductor chips are mounted on the wiring layer and resin-sealed, the wiring layer might be damaged. It also causes peeling of the wiring layer.
According to one embodiment, there is provided a method for manufacturing a semiconductor device, comprising forming on a support substrate a separation layer formed of a resin material; forming on the separation layer a wiring layer which is comprised of an organic insulating film having plural device forming regions and regions corresponding to dicing regions for dividing the plural device forming regions, and a metal wiring which is formed on the plural device forming regions of the organic insulating film; removing the regions corresponding to the dicing regions of the organic insulating film; mounting plural semiconductor chips on the wiring layer to arrange them on the plural device forming regions; forming a sealing resin layer for sealing at least part of each of the plural semiconductor chips on the separation layer to cover an edge surface of each of the plural device forming regions of the wiring layer; separating the support substrate from a resin sealing body having the wiring layer, the plural semiconductor chips and the sealing resin layer; and cutting the resin sealing body according to the dicing regions to singilate a structure having the wiring layer, the semiconductor chip and the sealing resin layer.
A semiconductor device and a manufacturing method of the semiconductor device according to embodiments are described below with reference to the drawings.
The separation layer 2 is formed of a resin material. The resin material forming the separation layer 2 is preferably a thermoplastic resin such as polyethylene, polypropylene, polystyrene, aclylonitrile styrene resin, aclylonitrile butadiene styrene resin, methacrylate resin, polyamide, polyacetal, polyethylene terephthalate, ultra high molecular weight polyethylene, polybutylene terephthalate, methylpentene, polycarbonate, polyphenylene sulfide, polyether ether ketone, liquid crystalline polymer, polytetrafluoroethylene, polyether imide, polyalylate, polysulfone, polyether sulfone, polyamide imide, cellulose resin, polyimide, etc. The separation layer 2 has preferably a thickness in a range from 1 to 20 μm. When the separation layer 2 has a thickness of less than 1 μm, there is a possibility that the support substrate 1 cannot be separated well. Even when the separation layer 2 is formed thick, its thickness of about 20 μm is sufficient. When the separation layer 2 is formed to have a larger thickness, its manufacturing cost increases. The thickness of the separation layer 2 is preferably determined depending on the method of separating the support substrate 1.
Then, wiring layers 3 are formed on the separation layer 2 as shown in
As shown in
A metal wiring which configures the wiring layers 3 is then formed. As a seed layer 6 for plating, for example, a Ti film having a thickness of 0.05 μm and a Cu film having a thickness of 0.1 μm are formed as shown in
As shown in
The second organic insulating film 4B is formed to have the same shape as the first organic insulating film 4A. Therefore, the wiring layers 3 which are comprised of the metal wiring 8 and the first and second organic insulating films 4A and 4B are present in the device forming region X only as shown in
The connection portions 8a of the metal wiring 8 are formed to penetrate through the organic insulating film 4 and exposed to the first and second surfaces 3a and 3b of the wiring layers 3. Exposed portions of the connection portions 8a on the side of the second surface 3b function as the connection pads to the semiconductor chips mounted on the wiring layers 3. The exposed portions of the connection portions 8a on the side of the first surface 3a function as the connection pads to another semiconductor chip, wiring board or the like.
As shown in
The semiconductor chip 9 is undergone FC mounting such that the metal bumps 10 are connected to portions of the connection portions 8a exposed on the side of the second surface 3b as shown in
The gap between the semiconductor chip 9 and the wiring layer 3 after the FC connection is filled with an underfill resin 11 as shown in
As shown in
It is preferable that the entire shape (outer shape) of the sealing resin layer 12 has the shape as shown in
Thus, the forming regions of the wiring layers 3 according to the plural device forming regions X are made smaller than the sealing resin layer 12, and the forming region of the sealing resin layer 12 is made smaller than the separation layer 2, so that a stress concentration to the end portions of the wiring layers 3 in the separation step of the support substrate 2 is suppressed, and a stress concentration to the end portions of the sealing resin layer 12 is also suppressed. Therefore, the wiring layers 3 can be suppressed from being peeled or damaged. At the time of molding the sealing resin layer 12, the mold clamping surface of a mold is directly pushed against the exposed separation layer 2, and there is a possibility of causing flash that the molding resin leaks to the outer periphery, but it can be suppressed by lowering the modulus of elasticity of the thermoplastic resin forming the separation layer 2.
A resin sealing body 13 which has the plural wiring layers 3 and the semiconductor chips 9 and the sealing resin layer 12 is separated from the support substrate 1 and then cut off for singulation. To perform the step of fabricating the resin sealing body 13 only, it is preferable that the sealing resin layer 12 is formed with a cutout, a mark or the like (hereinbelow collectively called as the alignment portion) for alignment to identify a rotation direction of the resin sealing body 13. The cutout shape as the alignment portion includes a notch shape or an orientation flat shape. The method of forming the mark as the alignment portion includes a method of printing or marking a scratch or a dent on the sealing resin layer 12.
As shown in
For example, the heating temperature of the thermoplastic resin layer as the separation layer 2 is preferably in a range of 220 to 260° C. By heating at such temperatures, the support substrate 1 can be separated easily in a short time without causing a thermal damage to the semiconductor chips 9, deformation of FC connection portions or the wiring layers 3, or the like. The separated support substrate 1 can be used repeatedly. To facilitate the separation of the support substrate 1 and the resin sealing body 13 by the heating treatment, it is preferable that the thermoplastic resin forming the separation layer 2 has a viscosity of 100 Pa·s or less or a shear modulus of 100 kPa or less at 250° C.
When the support substrate 1 is separated by shearing the separation layer 2, a stress concentration to the edge surfaces of the wiring layers 3 at the time of shearing the separation layer 2 can be prevented because the edge surfaces of the individual wiring layers 3 are covered by the sealing resin layer 12 and the edge surfaces of the wiring layers 3 of the outermost periphery of the entire sealing resin layer 12 are also covered. In other words, the starting point of the stress concentration when the separation layer 2 is sheared becomes the sealing resin layer 12. In addition, a stress applied to the connection portions 8a can be reduced because the connection portions 8a exposed on the first surface 3a of the wiring layer 3 are formed to have the outer shape formed to become smaller from the second surface 3b toward the first surface 3a. Thus, the wiring layers 3 can be suppressed from being peeled or damaged. Therefore, the wiring is suppressed from being broken when the semiconductor device is undergone reflowing or TCT, and the semiconductor device having excellent reliability and durability can be provided.
The method of separating the support substrate 1 is not limited to the method that the separation layer 2 is sheared and the support substrate 1 is separated from the resin sealing body 13. For example, a Si wafer is used as the support substrate 1, the separation layer 2 is formed of a polyamide type thermoplastic resin, and they are placed with the Si wafer on the lower side on a hot plate and heated to 250° C. At 250° C., the polyamide type thermoplastic resin exceeds a glass transition point and becomes soft. It is preferable that the thermoplastic resin has a viscosity of 100 Pa·s or less or a shear modulus of 100 kPa or less at the temperature exceeding the glass transition point.
The laminated body of the Si wafer and the resin sealing body 13 in the heated state is moved onto an insulation plate of normal temperature and naturally cooled on it. For example, the glass transition point of the sealing resin layer 12 is 160° C., the thermal expansion coefficient is 33 ppm at a temperature of the glass transition point or more, and the thermal expansion coefficient is 7 ppm at a temperature of the glass transition point or less. Therefore, the sealing resin layer 12 shrinks considerably while it is being cooled. The glass transition point of the sealing resin layer 12 is preferably in a range of 120 to 170° C., and it is preferable that the thermal expansion coefficient at a temperature of the glass transition point or more is in a range of 30 to 60 ppm, and the thermal expansion coefficient at a temperature of less than the glass transition point is in a range of 6 to 30 ppm.
The resin sealing body 13 including the sealing resin layer 12 is adhered to the separation layer 2 which is formed of the thermoplastic resin layer, so that when the sealing resin layer 12 shrinks, a stress generates in a direction opposite to the support substrate (Si wafer) 1. Therefore, the support substrate (Si wafer) 1 peels from the outer periphery of the resin sealing body 13 at a temperature of the glass transition point or more of the thermoplastic resin. By using a difference in thermal expansion coefficient between the sealing resin layer 12 and the support substrate (Si wafer) 1, the support substrate 1 may be separated from the resin sealing body 13 by a thermal stress generated in the cooling step after heating. This method requires the hot plate only to separate the support substrate 1, and since the need for a large apparatus, a suction mechanism or the like can also be eliminated, it becomes possible to separate the support substrate 1 from the resin sealing body 13 at low cost.
A laser beam or ultraviolet light can also be used in the separation step of the support substrate 1 from the resin sealing body 13. For example, a glass substrate is used as the support substrate 1, the separation layer 2 is formed of a resin material which decomposes upon absorbing the laser beam or ultraviolet light, and the laser beam or ultraviolet light is irradiated to the separation layer 2 via the glass substrate. Since the separation layer 2 decomposes upon absorbing the laser beam or ultraviolet light, the support substrate 1 can be separated from the resin sealing body 13. It is appropriate when at least a portion of the separation layer 2 which forms the interface with the resin sealing body 13 decomposes when the laser beam or ultraviolet light is irradiated. The forming material for the separation layer 2 includes a thermoplastic resin having ability to absorb the laser beam or ultraviolet light. The separation layer 2 has preferably a thickness in a range of 1 to 20 μm.
In order to separate the support substrate 1 by irradiating the laser beam or ultraviolet light to the separation layer 2, the peeling or damage of the wiring layers 3 due to a local temperature increase caused when the laser beam or ultraviolet light is irradiated can be suppressed because the edge surfaces of the wiring layers 3 are covered by the sealing resin layer 12. If the edge surfaces of the wiring layers 3 are not covered by the sealing resin layer 12, a local stress is applied to the organic insulating film 4 of the wiring layers 3 due to the local temperature increase, and the wiring layers 3 might be caused to peel. But, the stress due to the local temperature increase can be dispersed by covering the edge surfaces of the wiring layers 3 by the sealing resin layer 12 and also dividing the wiring layers 3. Thus, it becomes possible to suppress the wiring layers 3 from being peeled or damaged when the support substrate 1 is separated.
When the separation layer 2 is sheared to separate the support substrate 1, a residual layer 2a of the separation layer 2 generates on the first surface 3a of the wiring layer 3 as shown in
If the separation layer 2 (may be the mixed layer of the separation layer 2 with the organic insulating film 4 or the sealing resin layer 12) remains partly on the first surface 3a (excepting the exposed portions of the connection portions 8a) of the wiring layer 3, the adhesiveness with the resin to be formed next becomes good, and the reliability of the semiconductor device can be improved. The mixed layer of the organic insulating film 4 and the separation layer 2 which is on the first surface 3a of the wiring layer 3 will be described in detail in a second embodiment. In the first embodiment, it is also preferable to have the mixed layer of the separation layer 2 and the organic insulating film 4 on the first surface 3a of the wiring layer 3 excepting the exposed portions of the connection portions 8a in the same manner as in the second embodiment. Thus, the reliability of the semiconductor device can be improved.
The resin sealing body 13 separated from the support substrate 1 is then cut along the dicing regions by a blade 19 as shown in
In the structure 20 provided with the wiring layer 3, the semiconductor chip 9 and the sealing resin layer 12, a width of the sealing resin layer 12 formed at the outer periphery portion of the wiring layer 3, namely the distance between edge surface of the wiring layer 3 and the outer periphery surface of the sealing resin layer 12 is preferably determined to be 50 μm or less. It is more preferable that the distance between the edge surface of the wiring layer 3 and the outer periphery surface of the sealing resin layer 12 is 30 μm or less. If the distance between the edge surface of the wiring layer 3 and the outer periphery surface of the sealing resin layer 12 is excessively large, an effective area of the wiring layer 3 decreases, and the semiconductor device becomes large.
The semiconductor device 20 manufactured through the above-described manufacturing process is used as, for example, a component part of the double-sided mount type semiconductor package (semiconductor part) 21 as shown in
A semiconductor device 26 having the semiconductor chips 9 and 23 mounted on both sides of the wiring layer 3 is configured because the first semiconductor chip 9 is mounted on the second surface 3b of the wiring layer 3. Then, the double-sided mount type semiconductor device 26 is mounted on a package substrate 27 by using a mount paste, and the semiconductor device 26 and the package substrate 27 are electrically connected through bonding wires (such as Au wires) 28. In addition, resin molding is performed to seal the semiconductor chip 23, and metal balls are mounted on the rear surface of the package substrate 27 to form outside connection terminals 29. Thus, the double-sided mount type semiconductor package 21 is completed.
The semiconductor package 21 manufactured according to the above-described manufacturing process is provided to a temperature cycle test (TCT) to examine its reliability. The temperature cycle test was performed with −55° C. (30 minutes)→25° C. (5 minutes)→125° C. (30 minutes) determined as one cycle. As a result, no occurrence of rupture was recognized at the FC-connected portions of each surface of the double-sided mount type semiconductor device 26 after 3000 cycles. The stress applied to the connection portions 8a becomes small because the connection portions 8a formed on the wiring layer 3 become smaller toward the separation layer 2 and the wiring layer 3 is suppressed from expanding and contracting by covering the outer periphery of the wiring layer 3 by the sealing resin layer 12. Thus, the connection portions 8a and the solder bumps 10 and 24 can be suppressed from breaking at the time of the TCT.
As shown in
In the manufacturing method of the embodiment, an example of the FC connection of the wiring layer 3 and the semiconductor chip 9 was described. The wiring layer 3 and the semiconductor chip 9 can also be connected electrically by applying wire bonding. That is, a semiconductor chip 33 formed to have a thickness of, for example, about 50 μm is mounted on the wiring layer 3 by a mount material 34 as shown in
The manufacturing method of the semiconductor device according to the second embodiment is described below with reference to
As shown in
Therefore, the mixed layer 42 in the opening portions 5 is removed before the curing treatment of the coating film 41 of the organic insulating material. The mixed layer 42 in the opening portions 5 is removed by, for example, dry etching or wet etching. For the dry etching, an aching device is used, and an O2 asher or the like is applied to remove the mixed layer 42. Etching conditions are selected such that the coating film 41 of the organic insulating material is left remained. Otherwise, etching may be performed under conditions that an etching rate of the mixed layer 42 becomes faster than that of the coating film 41 of the organic insulating material. Then, the coating film 41 of the organic insulating material is undergone a curing treatment to form the first organic insulating film 4A having the opening portions 5 as shown in
The above-described first organic insulating film 4A is used to form the wiring layer 3 in the same manner as in the first embodiment. Then, the semiconductor chip 9 is FC-mounted on the wiring layer 3 in the same manner as in the first embodiment, and the underfill resin 11 and the sealing resin layer 12 are additionally formed (
And, the resin sealing body 13 is cut off for individuating in the same manner as in the first embodiment to produce a structure (semiconductor device) 20 having the wiring layer 3, the semiconductor chip 9 and the sealing resin layer 12 (
In the semiconductor device 20 according to the second embodiment, the mixed layer 42 of the separation layer 2 and the organic insulating film material improves their adhesion strength. Therefore, delamination in a reflow step or TCT can be suppressed. A defective shape of the opening portions 5 can be suppressed from occurring because the mixed layer 42 in the opening portions 5 is removed previously. And, the front surfaces of the connection portions 8a can be exposed easily by removing the residue of the separation layer 2 after the separating step of the support substrate 1. In addition, since the mixed layer 42 is on the first surface 3a of the wiring layer 3 excepting the exposed surfaces of the connection portions 8a, it becomes possible to improve adhesiveness when another resin layer is formed later.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-068407 | Mar 2010 | JP | national |
