Semiconductor device and method of manufacture thereof

Abstract

The semiconductor device of present invention is provided with an impurity diffusion region formed in the surface part of a semiconductor layer and a metal silicide layer formed in the surface part of the impurity diffusion region. An interlayer insulating film is formed on the metal silicide layer, and a contact plug that passes through the interlayer insulating film and is electrically connected with the metal silicide layer is formed. The contact plug passing through the interlayer insulating film is formed in a region where the metal silicide layer has a sufficient film thickness, and a recess is formed in the metal silicide layer at the contact hole bottom. Moreover, the contact plug has a projection fitting to the recess of the metal silicide layer in a part of a contact surface with the metal silicide layer.

Description

BRIEF DESCRIPTION OF THE INVENTION

FIGS. 1A to 1C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 1 of the present invention.

FIGS. 2A to 2C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 1 of the present invention.

FIGS. 3A to 3C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 1 of the present invention.

FIGS. 4A and 4B are sectional views showing a manufacturing process of a semiconductor device in Embodiment 1 of the present invention.

FIGS. 5A to 5C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 2 of the present invention.

FIGS. 6A to 6C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 2 of the present invention.

FIGS. 7A and 7B are sectional views showing a manufacturing process of a semiconductor device in Embodiment 2 of the present invention.

FIGS. 8A to 8C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 3 of the present invention.

FIGS. 9A and 9B are sectional views showing a manufacturing process of a semiconductor device in Embodiment 3 of the present invention.

FIGS. 10A to 10C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 4 of the present invention.

FIGS. 11A to 11C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 4 of the present invention.

FIGS. 12A and 12B are sectional views showing a manufacturing process of a semiconductor device in Embodiment 4 of the present invention.

FIGS. 13A to 13C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 5 of the present invention.

FIGS. 14A to 14C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 5 of the present invention.

FIGS. 15A to 15C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 5 of the present invention.

FIGS. 16A to 16C are sectional views showing a manufacturing process of a semiconductor device in Embodiment 6 of the present invention.

FIGS. 17A to 17C are sectional views showing a manufacturing process of a prior semiconductor device.

FIG. 18 is a graph showing a relationship between the etching amount of contact bottom and the silicide area ratio of contact bottom.

FIG. 19 is a graph showing a relationship between the silicide area ratio of contact bottom and the contact resistance.

Claims

1. A semiconductor device provide with an impurity diffusion region formed in the surface part of a semiconductor layer, a metal silicide layer formed at the surface of the impurity diffusion region and a contact plug that passes through an interlayer insulating film formed on the metal silicide layer and is electrically connected with the metal silicide layer, comprising: a metal silicide layer having a recess at a contact surface with a contact plug; anda contact plug having a projection fitting to the recess in a part of contact surface with the metal silicide layer.

2. The semiconductor device according to claim 1 wherein the recess has a multi-step structure.

3. The semiconductor device according to claim 1 wherein the contact surface of the metal silicide layer with the contact plug is a concave curved surface.

4. The semiconductor device according to claim 1 wherein the main component of the semiconductor layer is silicon.

5. The semiconductor device according to claim 4 wherein the interlayer insulating film has a multilayer structure formed with a second insulating film on a first insulating film and the first insulating film functions as an etching stopper during an etching for forming a through hole in the second insulating film.

6. The semiconductor device according to claim 5 wherein the second insulating film is a silicon oxide film, a boron-phosphorus doped silicon oxide film or a phosphorus doped silicon oxide film.

7. The semiconductor device according to claim 5 wherein the first insulating film is a silicon nitride film or a silicon carbide film.

8. The semiconductor device according to claim 4 wherein the metal silicide layer is a nickel silicide layer.

9. A manufacturing method of semiconductor device provided with a contact plug electrically connected to an impurity diffusion region in the surface part of a semiconductor layer via a metal silicide layer, comprising the steps of: forming an impurity diffusion region in the surface part of a semiconductor layer;forming a metal silicide layer in the surface part of the impurity diffusion region;forming an interlayer insulating film on the semiconductor layer formed with the metal silicide layer;forming a mask pattern having an opening at a contact plug formation position on the interlayer insulating film;forming a through hole in the interlayer insulating film by etching via the mask pattern;forming a recess in the metal silicide layer by etching via the through hole;expanding the diameter of the through hole; andforming a contact plug by filling a conductor into the through hole with the expanded diameter.

10. The manufacturing method of semiconductor device according to claim 9 wherein the recess is formed by the etching for forming the through hole.

11. The manufacturing method of semiconductor device according to claim 9 further comprising the step of forming spacer at the inner wall of the through hole after the forming of the through hole, and wherein the recess is formed by etching via the through hole formed with the spacer and the diameter of the through hole is expanded by removing the spacer after the forming of the recess.

12. The manufacturing method of semiconductor device according to claim 9 wherein the forming of the recess and the expanding of the diameter of the through hole are alternately repeated and a multi-step structure is formed in the metal silicide layer.

13. The manufacturing method of semiconductor device according to claim 9 further comprising the step of forming a pattern for controlling the diameter of bottom of the through hole after the forming of the metal silicide layer, and wherein the recess is formed by etching via the control pattern and the diameter of the through hole is expanded by removing the control pattern after the forming of the recess.

14. The manufacturing method of semiconductor device according to claim 13 wherein the control pattern is a sidewall formed at a gate electrode adjacent to the through hole.

15. The manufacturing method of semiconductor device according to claim 9 further comprising the step of forming a concave curved surface in a region including a contact surface of the contact plug at the surface of the semiconductor layer by performing an isotropic etching of the semiconductor layer before the forming of the metal silicide layer.

16. The manufacturing method of semiconductor device according to claim 15 wherein the isotropic etching is performed with the sidewall formed in a gate electrode adjacent to the through hole as a mask.

17. The manufacturing method of semiconductor device according to claim 9 further comprising the step of removing a part of the metal silicide layer by an isotropic etching via the expanded through hole after the expanding of the diameter of the through hole.

18. The manufacturing method of semiconductor device according to claim 15 wherein the isotropic etching is a wet etching.

19. The manufacturing method of semiconductor device according to claim 9 wherein the main component of the semiconductor layer is silicon.

20. The manufacturing method of semiconductor device according to claim 19 wherein the interlayer insulating film has a multilayer structure formed with a second insulating film on a first insulating film, and the first insulating film functions as an etching stopper during the etching for forming the through hole in the second insulating film.

21. The manufacturing method of semiconductor device according to claim 20 wherein the second insulating film is a silicon oxide film, a boron-phosphorus doped silicon oxide film or a phosphorus doped silicon oxide film.

22. The manufacturing method of semiconductor device according to claim 20 wherein the first insulating film is a silicon nitride film or a silicon carbide film.

23. The manufacturing method of semiconductor device according to claim 19 wherein the metal silicide layer is a nickel silicide layer.