Embodiments described herein relate generally to a semiconductor device, a semiconductor storage device and a method of manufacturing the semiconductor device.
The resistance of a metal wire in a semiconductor integrated circuit increases as the wire is miniaturized. This reduces the circuit performance.
a) to 3(f) are cross-sectional views describing a process for manufacturing the semiconductor device in
According to an embodiment, a semiconductor device includes a plurality of wires provided on an insulating layer. Each of the wires includes one or more metal crystal grains. An average width of each of the wires and an average interval between the wires adjacent to each other are nearly equal to or less than a mean free path of free electrons in a bulk crystal of the metal. A specific crystal orientation in which size effect of electrical resistivity weakens due to anisotropy of Fermi velocity in the metal is substantially parallel to a current direction in at least a part of the crystal grains in each of the wires.
Before description of embodiments of the present invention, the background in which the present invention has been achieved by the inventor will be described.
It is known that, when the miniaturization of a metal wire progresses, the electric resistance increases more than the decrease in the cross-sectional area of the wire. This is because, as the miniaturization progresses, the effect of interface scattering of free electrons on wire's surface in electrical characteristics manifests itself and the electric resistivity, which is essentially constant in large crystal structure, increases. The phenomenon is referred to as “size effect of electrical resistivity” and well known.
The size effect of electrical resistivity occurs when the width or height of the wire is nearly equal to or less than the mean free path (MFP) (the average distance travelled by the free electrons without being scattered) of the free electrons carrying the current. The mean free path depends on the material (the constitute element, and the crystal structure) and the temperature. The value is about 10 to 50 nm at room temperatures. The minimum size of the wire used for an existing semiconductor integrated circuit is already equal to or less than the MFP in product level. Thus, the miniaturization rapidly increases the resistance of the wire. The electric signal delay in the wire caused by the rapid increase in the resistance increasingly dominates the performance of the whole circuit.
There is another problem that the progress of the miniaturization deteriorates the tolerance to the electromigration or the tolerance to the dielectric strength voltage between the wires. The realization of the decrease in the resistance and in the capacitance of the metal wire and the increase in the reliability is recognized as a challenge to be addressed in the development of next-generation semiconductor integrated circuits.
Polycrystalline copper (Cu) is generally used as a metal of the lowest wire layer (the wire layer nearest to the semiconductor substrate) that is mostly miniaturized in an existing semiconductor integrated circuit. Cu has a lower bulk resistivity and a higher tolerance for the electro migration than aluminum (Al) that has commonly been used in the past. These merits has progressed the introduction of Cu to semiconductor integrated circuits. However, the MFP of the free electrons in Cu is longer than that in Al. Thus, there is a problem that Cu is easily affected by the size effect, especially, in a miniaturized wire. A Cu wire is normally produced in a damascene process (a process in which an insulating layer is etched and Cu is embedded therein). As the miniaturization of the wire progresses, the miniaturization of the crystal grain progresses. The miniaturization of the crystal grain facilitates the size effect.
It is currently reported that patterning a miniaturized wire made of single crystal tungsten (W) having a body-centered cubic lattice (hereinafter, referred to as bcc) structure is performed such that the wire-length direction (the direction in which the current flows) is parallel to a <111> crystal orientation so that it can reduce the size effect of electrical resistivity. It is qualitatively explained that the phenomenon occurs because the Fermi velocity distribution (the velocity distribution of the free electrons travelling in a metal) of a W crystal has anisotropy and that causes the size effect of electrical resistivity to have the anisotropy therewith. Considering the Fermi velocity distribution of a W crystal, the anisotropy of velocity distribution on an octahedral Fermi surface is especially strong. The Fermi velocity is the velocity of the electrons that carry the current in a metal. Thus, if the distribution of the velocity has anisotropy, the frequency of collisions of the electrons with the interface of the wire can also have anisotropy.
The inventor has developed a Monte Carlo simulator for electron transport in metal. The Monte Carlo simulator considers the anisotropy of the Fermi velocity distribution of the W crystal obtained from a first principle calculation. The Monte Carlo simulator quantitatively reproduces the anisotropy of the size effect of electrical resistivity on the W crystal successfully. The Monte Carlo simulation is a type of particle simulations. As illustrated in
The inventor has incorporated the function for determining the velocity vectors of the electrons according to the W-crystal-specific Fermi velocity distribution in the Monte Carlo simulator for metal wires by applying a full-band Monte Carlo technique in the same manner as Monte Carlo method for a semiconductor device.
From the simulation, the inventor has further obtained important knowledge that the crystal orientation in which the size effect is reduced is not identified only according to the crystal structure.
On the other hand, as the height h of the wire increases, the resistivity in the <100> direction rapidly decreases. The resistivity in the <100> direction is minimized when the wire has the height h=160 nm. It can be considered that the phenomenon occurs because the anisotropy of the Fermi velocity distribution causes the wire parallel to the <100> direction to have a low size effect in the width direction (or have a small velocity component of electron in the width direction) and to have a high size effect in the height direction (or have a large velocity component of electron in the height direction). In other words, in the wire of which length direction is parallel to the <100> direction, as the height increases, the size effect in the height direction weakens and thus the resistivity decreases.
As described above, in a miniaturized wire made of a single crystal metal, the size effect of electrical resistivity has anisotropy according to the anisotropy of the crystal-specific Fermi velocity. The crystal orientation in which the size effect of electrical resistivity weakens is not identified according to the material but it depends on the shape and size of the cross-sectional surface and the crystal orientation of the surface of the wire. As for the anisotropy of the size effect of electrical resistivity in a single crystal, only the report about the anisotropy at a liquid nitrogen temperature and in an Al crystal in a millimeter-scale order is known. Only the experimental result of the miniaturized W wire is reported as an experimental result of a miniaturized wire at a room temperature.
The inventor invented the present invention based on their unique knowledge as described above. In other words, the inventors implements a miniaturized wire with a low resistance in which the size effect of electrical resistivity is weaken using noble metal (Cu, Ag, or Au), Al or Mo based on the knowledge obtained from the Monte Carlo simulation in consideration of the anisotropy of the Fermi velocity distribution in the metal crystal.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention.
The first embodiment relates to a Cu wire in which the upper surfaces and lower surfaces of main crystal grains are substantially orientated to a {100} surface.
In
The MgO(001) layer 20 is provided on the Si(001) substrate 10.
The wires 30 are provided on the MgO(001) layer 20 and extend in the y-direction. The average width of each of the wires 30 and the average interval between the adjacent wires 30 and 30 are nearly equal to or less than the mean free path of the free electrons in a Cu bulk crystal. In other words, each of the wires 30 has a size in which the size effect of electrical resistivity described above can occur. The cross-sectional surface of each of the wires 30 has an aspect ratio (height h/width w) of four or less.
The wires 30 each have a plurality of Cu crystal grains 31. The crystal grains 31 are arranged in the y-direction in each of the wires 30. A crystal grain boundary 32 exists between the crystal grains 31 and 31. Each of the wires 30 can be made of the single crystal grain 31.
The crystal grains 31 in the main part of each of the wires 30, namely, at least a part of the crystal grains 31 in each of the wires 30 are Cu crystal grains (Cu{100} crystal grains) having a face-centered cubic lattice (hereinafter, referred to as fcc) structure orientated to a (001) surface. In other words, the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31 in the main part of each of the wires 30 are substantially orientated to a {100} surface. The {100} surface is the crystal face equivalent to a (100) surface. Hereinafter, the Cu{100} wire means a Cu wire in which the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31 in the main part are substantially orientated to the {100} surface.
As described above, the crystal face on the upper surface of the Si(001) substrate 10, the crystal face on the upper surface of the MgO(001) layer 20, and the crystal faces on the upper surfaces of the crystal grains 31 in the main part of each of the wires 30 are substantially equivalent.
The specific crystal orientation in which the size effect of electrical resistivity weakens due to the anisotropy of the Fermi velocity in Cu, is substantially parallel to a current direction in which the current flows (the length direction of the wire 30 (the y-direction)) in the crystal grains 31 in the main part of each of the wires 30, namely, in at least a part of the crystal grains 31 in each of the wires 30. In the present embodiment, the specific crystal orientation is a <110> crystal orientation. The <110> crystal orientation is equivalent to a [110] direction.
In each of the wires 30, the current direction is not limited to the specific crystal orientation in the parts except for the main part and can be an arbitrary direction.
In each of the wires 30, the average crystal grain size of the crystal grains 31 in the current direction is larger enough than the mean free path of the free electrons in the Cu bulk crystal. In other words, the average crystal grain size is large enough to ignore the deterioration of the resistivity due to the crystal grain boundary 32.
In the present embodiment, the wire 30 has a rectangular cross-sectional shape. However, the cross-sectional shape can have a tapered structure or an inverted tapered structure. Alternatively, the corners of the wire 30 can be rounded.
Although not illustrated in the drawings, the semiconductor device can have a metal barrier layer, an insulating layer, a vacuum layer, or a layered structure including these layers between the wires 30 and 30 to prevent Cu atoms from diffusing.
a) to 3(f) are cross-sectional views describing a process for manufacturing the semiconductor device in
As illustrated in
As illustrated in
As illustrated in
After that, as illustrated in
Next, as illustrated in
In the production method described above, the wires 30 in which the current direction (length direction) is orientated to the <110> direction can be produced.
b), 4(c), and 4(d) plot the resistivity of the wire 30 having the heights h of 10 nm, the resistivity of the wire 30 having the heights h of 20 nm, and the resistivity of the wire 30 having the heights h of 40 nm, respectively, when each of the crystal orientations is rotated to a [010] direction based on the wire in a [100] direction in the (001) surface. As shown in the drawings, the crystal orientation in which the resistivity has the minimum value varies depending on the height h and width w of the wire 30. When the aspect ratio is equal to or less than four and the width is narrow (characteristics 401 and 402), the resistivity is lowered within a range of ±15 degrees from a [110] direction (45 degree on the horizontal axis). The present embodiment can reduce the resistivity using the characteristics.
On the other hand, when a miniaturized wire has the aspect ratio exceeding 4, for example, when w=5 nm or 10 nm holds (a characteristic 403) in
As described above, in the present embodiment, the current easily flows in the current direction because the cross-sectional surface of the wire 30 has an aspect ratio of four or less and the specific crystal orientation (the <110> crystal orientation) in which the size effect of electrical resistivity weakens is substantially parallel to the current direction. This suppresses the size effect of electrical resistivity and thus can reduce the wire resistance to the resistance lower than that of a conventional wire having the same cross-sectional surface area.
Note that a wire 30 made of a single crystal grain 31 but without a crystal grain boundary 32 does not cause Cu atoms to diffuse on the crystal grain boundary 32. This can improve the tolerance to the electromigration and thus can increase the reliability.
Furthermore, another insulating material or semi-insulating material can be used as the insulating layer instead of the MgO(001) layer 20 as long as the crystal grains 31 orientated as illustrated in
Furthermore, a vacuum layer can be inserted between the adjacent wires 30 and 30. This can reduce also the capacitance between the wires.
The second embodiment relates to a Cu{110} wire.
As for the wires 30a in the second embodiment, different from the first embodiment, the crystal grains 31a in the main part of each of the wires 30a are Cu{110} crystal grains each having an fcc structure, and the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31a are substantially orientated to a {110} surface, and also the cross-sectional surface of each of the wires 30a has an arbitrary aspect ratio.
The current direction is the same as in the first embodiment. A specific crystal orientation (the <110> crystal orientation) in which the size effect of electrical resistivity weakens is substantially parallel to the current direction in the main part of each of the wires 30a.
The crystal grain size of the crystal grains 31a, the average width of each of the wires 30a, and the average interval between the wires 30a and 30a are the same as those in the first embodiment.
Arranging the <110> crystal orientation of each of the crystal grains 31a substantially in parallel to the current direction as described above can suppress the size effect of electrical resistivity and thus can reduce the resistance of the wire 30a using Cu.
In the third embodiment, silver (Ag) or gold (Au) is used instead of Cu in the first or second embodiment.
The semiconductor device has the same structure as in the first or second embodiment. Thus, the drawing and the description will be omitted. Hereinafter, the different points from the first or second embodiment will mainly be described.
The Fermi surfaces of the fcc crystals of Ag and Au have very similar structures to the structure of Cu that is in the same group as Ag and Au in the periodic table. Thus, the anisotropy of the size effect of electrical resistivity of a wire using Ag or Au is similar to the anisotropy of the size effect of electrical resistivity of Cu.
As illustrated in
Thus, similarly to the first embodiment, the aspect ratio of the wire 30 is set at four or less and the <110> crystal orientation of each of the crystal grains 31 is arranged substantially in parallel to the current direction. This can suppress the size effect of electrical resistivity and reduce the resistance of the wire 30 using Ag or Au.
As illustrated in
Thus, similarly to the second embodiment, arranging the <110> crystal orientation of each of the crystal grains 31a substantially in parallel to the current direction as described above can suppress the size effect of electrical resistivity and thus can reduce the resistance of the wire 30a using Ag or Au.
The fourth embodiment relates to an Al{100} wire.
The crystal grains 31b in the main part of each of the wires 30b are Al{100} crystal grains each having an fcc structure. In other words, the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31b in the main part of each of the wires 30b are orientated substantially to a {100} surface. In the crystal grains 31b in the main part of the wire 30b, the <110> crystal orientation that is a specific crystal orientation is substantially parallel to a current direction.
The cross-sectional surface of each of the wires 30b has an aspect ratio of two or more. The average width of each of the wires 30b and the average interval between the wires 30b are nearly equal to or less than the mean free path of the free electrons in an Al bulk crystal. In each of the wires 30b, the average crystal grain size of the crystal grains 31b in the current direction is larger enough than the mean free path of the free electrons in the Al bulk crystal. In other words, the average crystal grain size is large enough to ignore the deterioration of the resistivity due to the crystal grain boundary 32b.
In the single crystal Al wire, the anisotropy of the size effect of electrical resistivity is generated due to the anisotropy of the Fermi velocity.
Thus, as described above, the aspect ratio of the wire 30b is set at two or more and the <110> crystal orientation of each of the crystal grains 31b is arranged substantially in parallel to the current direction. This can suppress the size effect of electrical resistivity and reduce the resistance of the wire 30b using Al.
The fifth embodiment relates to an Al{110} wire.
The crystal grains 31c in the main part of each of the wires 30c are Al{110} crystal grains each having an fcc structure. In other words, the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31c in the main part of the wire 30c are orientated substantially to a {110} surface.
In the crystal grains 31c in the main part of each of the wires 30c, the <111> crystal orientation that is a specific crystal orientation is substantially parallel to the current direction.
The cross-sectional surface of each of the wires 30c has an aspect ratio of two or more. The average crystal grain size, the average width of each of the wires 30c and the average interval between the wires 30c are the same as those in the fourth embodiment.
Thus, as described above, the aspect ratio of the wire 30c is set at two or more and the crystal orientation <111> of each of the crystal grains 31c is arranged substantially in parallel to the current direction. This can suppress the size effect of electrical resistivity and reduce the resistance of the wire 30c using Al.
The sixth embodiment relates to an Mo{110} wire using molybdenum (Mo).
The crystal grains 31d in the main part of each of the wires 30d are Mo{110} crystal grains each having a bcc structure. In other words, the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31d in the main part of each of the wires 30d are orientated substantially to a {110} surface.
In the crystal grains 31d in the main part of each of the wires 30d, the crystal orientation <111> that is a specific crystal orientation is substantially parallel to the current direction.
The cross-sectional surface of each of the wires 30d has an aspect ratio of four or less. The average width of each of the wires 30d and the average interval between the wires 30d are nearly equal to or less than the mean free path of the free electrons in an Mo bulk crystal. In each of the wires 30d, the average crystal grain size of the crystal grains 31d in the current direction is larger enough than the mean free path of the free electrons in the Mo bulk crystal. In other words, the average crystal grain size is large enough to ignore the deterioration of the resistivity due to the crystal grain boundary 32d.
Thus, as described above, the aspect ratio of the wire 30d is set at four or less and the crystal orientation <111> of each of the crystal grains 31d is arranged substantially in parallel to the current direction. This can suppress the size effect of electrical resistivity and reduce the resistance of the wire 30d using Mo.
The seventh embodiment relates to an Mo{100} wire.
The crystal grains 31e in the main part of each of the wires 30e are Mo{100} crystal grains each having a bcc structure. In other words, the crystal faces on the upper surfaces and lower surfaces of the crystal grains 31e in the main part of each of the wires 30e are orientated to a {100} surface.
In the crystal grains 31e in the main part of each of the wires 30e, the <110> crystal orientation that is a specific crystal orientation is substantially parallel to the current direction.
The cross-sectional surface of each of the wires 30e has an aspect ratio of two or more. The average crystal grain size, the average width of each of the wires 30e and the average interval between the wires 30e are the same as those in the sixth embodiment.
Thus, as described above, the aspect ratio of the wire 30e is set at two or more and the <110> crystal orientation of each of the crystal grains 31e is arranged substantially in parallel to the current direction. This can suppress the size effect of electrical resistivity and reduce the resistance of the wire 30e using Mo.
Note that each of the variations described in the first embodiment can also be applied to the second to seventh embodiments.
The eighth embodiment relates to a NAND type semiconductor storage device (flash memory) using the Cu{100} wire in the first embodiment as the bit lines.
As illustrated in
As illustrating
The memory cell MC is formed at the position in which the active region AA crosses the word lines WL. A select transistor ST1 is formed at the position in which the active region AA crosses the select gate line SGD. A select transistor ST2 is formed at the position in which the active region AA crosses the select gate line SGS.
As described below, the bit lines BL are provided under the active regions AA such that the active regions AA overlap with the bit lines BL. In other words, the word lines WL cross the bit lines BL.
The memory cells MC arranged in the x-direction and the select transistors ST1 and ST2 on both ends of the memory cells are included in a NAND string 80. An end of the NAND string 80, namely, the select transistor ST1 is electrically connected to the bit line BL through bit line contact BC. Although not illustrated in the drawings, the other end of the NAND string 80, namely, the select transistor ST2 is connected to a source line.
As illustrated in
The bit lines BL are provided on the MgO(001) layers 20 and extend in the x-direction. The MgO(001) layers 20 exist under the bit lines BL and do not exist between the adjacent bit lines BL and BL. This can reduce the wiring capacitance between the bit lines BL and BL.
Note that, when it is not necessary to reduce the wiring capacitance, the MgO(001) layers 20 can be provided without the intervals so as to cover the Si(001) substrate 10, similarly to the first embodiment.
Each of the bit lines BL has the same structure as the wire 30 in the first embodiment. In other words, each of the bit lines BL has one or more Cu crystal grains. At least a part of the crystal grains in each of the bit lines BL is Cu{100} crystal grain having an fcc structure. The average width of each of the bit lines BL and the average interval between the adjacent bit lines BL and BL are less than the mean free path of the free electrons in the Cu bulk crystal. The average interval between the adjacent bit lines BL and BL can be wider than the mean free path of the free electrons. The specific crystal orientation (a <110> crystal orientation) in which the size effect of electrical resistivity weakens due to the anisotropy of the Fermi velocity in Cu, is parallel to the x-direction in at least a part of the crystal grains in each of the bit lines BL. The cross-sectional surface of each of the bit lines BL has an aspect ratio of four or less. In each of the bit lines BL, the average crystal grain size of the crystal grains in the x-direction is larger enough than the mean free path of the free electrons in the Cu bulk crystal.
The second insulating film 50 covers the Si(001) substrate 10, the MgO(001) layer 20, and the bit lines BL. The upper portion of the second insulating film 50 is substantially flattened.
The memory cells MC are provided on the second insulating layer 50. In other words, the memory cells MC are supported with the Si(001) substrate 10.
The active regions AA of the memory cells MC are provided on the second insulating layer 50. The active regions AA are made, for example, of single crystal silicon, polysilicon, or amorphous silicon.
The element isolation insulating film 60 is provided between the adjacent active regions AA and AA. The element isolation insulating film 60 is made, for example, of a silicon oxide film.
The insulating films 70 are provided on the active regions AA. The floating gates FG are provided on the insulating films 70. The insulating film 71 is provided on the floating gates FG.
The insulating films 70 and 71 are made, for example, of a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. The floating gate FG is made, for example, of polysilicon, or a metal material such as TiN.
The word line WL extending in the y-direction is provided on the insulating film 71.
Next, a method for manufacturing the semiconductor storage device will be described. First, the processes in
Next, silicon is deposited on the insulating film 50. After that, similarly to the well-known manufacturing method, the silicon is processed to create the active regions AA. Next, the memory cells MC, the select transistor ST, and the like are created. After that, the bit line contacts BC and the like are created.
The present embodiment uses the wire 30 in the first embodiment as the bit line BL. This suppresses the size effect of electrical resistivity of the bit line BL, and thus can reduce the wire resistance from the conventional bit line having the same cross-sectional surface area. This can suppress the wire delay of the bit line BL.
Corresponding to an amount of which the resistance of the bit line BL is reduced, the wire width of the bit line BL can be reduced. Therefore, the rate of integration of the memory cells MC can be improved.
Note that, although the floating gate type memory cell MC has been described in the eighth embodiment, a charge trapping type memory cell can be used instead of the floating gate type memory cell MC to provide the same effect as described above.
The charge trapping type memory cell can be, for example, a MONOS type memory cell.
The ninth embodiment relates to a resistance change type semiconductor storage device using the Cu{100} wire in the first embodiment.
As illustrated in
As illustrated in
The memory cell MC is provided at the position at which the bit line BL crosses a pair of adjacent word lines WL and WL and between the pair of word lines WL and WL.
As illustrated in
The word lines WL are provided on the MgO(001) layers 20. Each of the word lines WL has the same structure as the wire 30 in the first embodiment. In other words, a specific crystal orientation (a <110> crystal orientation) is substantially parallel to the y-direction in at least a part of the crystal grains in each of the word lines WL. The description of the same structure in the word lines WL as the first embodiment will be omitted. Note that the average interval between the adjacent word lines WL and WL can be wider than the mean free path of the free electrons in the Cu bulk crystal.
The MgO(001) layers 20 exist under the word lines WL and do not exist between the adjacent word lines WL and WL. In other words, an opening penetrating the MgO(001) layer 20 is provided between the adjacent word lines WL and WL.
The source layer S1 in the field effect transistor T1 is an n+ type semiconductor layer, and is provided on the Si(001) substrate 10 in the opening penetrating the MgO(001) layer 20.
The channel layer C1 is a semiconductor layer and is provided at the position that is on the source layer S1 and faces the pair of word lines WL and WL.
The second insulating layer 90 is provided between the channel layer C1 and the pair of word lines WL and WL to function as a gate insulating film of the field effect transistor T1.
The drain layer D1 is an n+ type semiconductor layer, and is provided on the channel layer C1.
The source layer S1, the channel layer C1, and the drain layer D1 are made, for example, of single crystal silicon, polysilicon, or amorphous silicon.
The pair of word lines WL and WL functions as a gate electrode of the field effect transistor T1. The field effect transistor T1 is a vertical double-gate n-Si transistor.
The variable resistive layer 100 is provided above the drain layer D1 and is electrically connected to the drain layer D1. The variable resistive layer 100 varies the resistance value depending on at least one of the applied voltage and current.
As described above, the memory cell MC is supported with the Si(001) substrate 10. Furthermore, the source layer S1, the channel layer C1, the drain layer D1, and the variable resistive layer 100 are layered in the z-direction (a vertical direction). The second insulating layer 90 surrounds the periphery of the layered source layer S1, channel layer C1, drain layer D1, and variable resistive layer 100 to insulate the layers from the adjacent memory cells MC in the y-direction.
The bit line BL is provided above the word lines WL and above the variable resistive layer 100 and is electrically connected to the variable resistive layer 100 through the bit line contact BC.
Insulating layers 91 are provided between the bit line BL and the word lines WL. The insulating layer 91 can be formed integrally with the second insulating layer 90.
The source line SL is an n+ type conductive layer provided in the Si(001) substrate 10. The source line SL is electrically connected to the source layer S1 and extends in the x-direction while overlapping with the bit line BL.
An MgO(001) layer 21 extending in the x-direction is provided between the adjacent source lines SL and SL in the y-direction. The MgO(001) layer 21 insulates the source lines SL and SL. The MgO(001) layer 21 is embedded in a groove formed in the Si(001) substrate 10. The surface of the MgO(001) layer 21 is at the same level as the surface of the Si(001) substrate 10. The MgO(001) layer 21 can be grown in the same process as the MgO(001) layer 20.
The semiconductor storage device having the structure described above controls the current flowing in the field effect transistor T1 by applying the voltage in the bit line BL, the word lines WL, and the source lines SL in order to read, write, or delete the data in the memory cell MC.
The present embodiment suppresses the size effect of electrical resistivity of the word line WL, and thus can lower the wire resistance than the conventional word line having the same area of the cross-sectional surface because the wire 30 in the first embodiment is used as the word lines WL. This can suppress the wire delay of the word line WL.
Corresponding to an amount of which the resistance of the word line WL is reduced, the wire width of the word line WL can be reduced. Therefore, the rate of integration of the memory cells MC can be improved.
The tenth Embodiment relates to a resistance change type semiconductor storage device having a different structure from the ninth embodiment.
As illustrated in
As illustrated in
The source line SL extends in the y-direction between a pair of adjacent word lines WL and WL. A source line SL is not provided between a pair of word lines WL and WL that is adjacent to the pair of word lines WL and WL between which the source line SL is provided.
The memory cell MC is provided at the position at which the bit line BL crosses the source line SL and the word line WL.
As illustrated in
The word lines WL are provided on the MgO(001) layers 20. The detailed description of each of the word lines WL will be omitted because the word lines WL have the same structure as the word lines WL in the ninth embodiment.
The MgO(001) layers 20 exist under the word lines WL and do not exist between the adjacent word lines WL and WL.
The field effect transistor T1 includes a pair of the source layer S1 and drain layer D1 provided in the semiconductor substrate 10, so as to be located at both sides of the word line WL. The source layer S1 and drain layer D1 each are an n+ type semiconductor layer. The MgO(001) layer 20 functions as a gate insulating film of the field effect transistor T1. The word line WL functions as a gate electrode of the field effect transistor T1.
The variable resistive layer 100 is provided above the drain layer D1 and is electrically connected to the drain layer D1 through a drain contact DC.
As described above, the memory cell MC is supported with the Si(001) substrate 10.
The MgO(001) layer 21 extending in the x-direction is provided between the source layer S1 and S1, between channels, and between the drain layers D1 and D1, namely, between the adjacent field effect transistors T1 and T1 in the y-direction. The MgO(001) layer 21 insulates the field effect transistors from each other. The MgO(001) layer 21 is embedded in a groove formed in the Si(001) substrate 10. The surface of the MgO(001) layer 21 is at the same level as the surface of the Si(001) substrate 10.
The source line SL is provided above the source layer S1 and is electrically connected to the source layer S1 through a source contact SC.
The bit line BL is provided above the source lines SL and the word lines WL and above a variable resistive layer and is electrically connected to the variable resistive layer 100 through the bit line contact BC.
An insulating layer such as a silicon oxide film is provided between the source line SL and the bit line BL, between the source line SL and the word line WL, and between the word line WL and the bit line BL, and the like.
The two memory cells MC and MC that are adjacent to each other in the x-direction and holding a source line SL therebetween share the source layer S1, the source line contact SC, and the source line SL.
The semiconductor storage device operates in the same manner as the ninth embodiment.
The present embodiment can provide the same effect as the ninth embodiment. In addition, the MgO(001) layer 20 that is a high-k film is used as a gate insulating film in the field effect transistor T1. Therefore, there can be reduced the leakage current to the word line WL, that is a gate electrode, more than that in the case in which SiO2 is used as the gate insulating film.
Note that one of the wires in the second embodiment to the seventh embodiment can be used in the eighth to tenth embodiments instead of the Cu{100} wire.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based upon and claims the benefit of priority from the prior U.S. Provisional Patent Application No. 62/013,964, filed on Jun. 18, 2014, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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62013964 | Jun 2014 | US |