Claims
- 1. A semiconductor integrated circuit device comprising a semiconductor substrate having a semiconductor element formed on a main surface, a first pattern formed on said main surface or any layer on said main surface, and a second pattern formed on an upper layer of said first pattern, wherein:
said first pattern comprises a dummy pattern, and said second pattern comprises a pattern used for optical pattern recognition, and said pattern used for optical pattern recognition is formed so as to be enclosed within a flat shape of said dummy pattern.
- 2. A semiconductor integrated circuit device as defined in claim 1, wherein said first pattern comprises another dummy pattern having a smaller area than said dummy pattern.
- 3. A semiconductor integrated circuit device as defined in claim 2, wherein said dummy pattern and another dummy pattern are formed in a scribe region.
- 4. A semiconductor integrated circuit device as defined in claim 2, wherein said other dummy pattern is formed in a product region and a scribe region.
- 5. A semiconductor integrated circuit device as defined in claim 1, wherein said dummy pattern is formed with an area equal to or greater than that of a pattern prohibition region on the periphery of said pattern used for optical pattern recognition.
- 6. A semiconductor integrated circuit device as defined in claim 5, wherein said first pattern has patterning dimensions of the same order as a design rule of said semiconductor element and comprises another dummy pattern having a smaller area than said dummy pattern, and said other dummy pattern is not disposed in said pattern prohibition region.
- 7. A semiconductor integrated circuit device as defined in claim 6, wherein said dummy pattern is formed in a scribe region of a semiconductor wafer, and said other dummy pattern is formed in a product region and a scribe region of said semiconductor wafer.
- 8. A semiconductor integrated circuit device comprising a semiconductor substrate having a semiconductor element formed on a main surface, a first pattern formed on said main surface or any layer on said main surface, and a second pattern formed on an upper layer of said first pattern, wherein:
said first pattern comprises a first dummy pattern, said second pattern comprises a second dummy pattern having a pattern pitch and pattern width of identical design dimensions as said first dummy pattern, and said second dummy pattern is formed on a space of said first dummy pattern in its flat surface position.
- 9. A semiconductor integrated circuit device as defined in claim 8, wherein one of the side edges of said second dummy pattern is formed so as to overlap with said first dummy pattern in its flat surface position.
- 10. A semiconductor integrated circuit device as defined in claim 8, wherein said first dummy pattern and said second dummy pattern are offset by a distance of ½ pitch in its flat surface position.
- 11. A semiconductor integrated circuit device as defined in claim 8, wherein:
said first pattern further comprises another dummy pattern having a larger area than that of said first dummy pattern, said second pattern further comprises a pattern used for optical recognition, and said pattern used for optical recognition is formed so that it is enclosed within the flat shape of said other dummy pattern.
- 12. A semiconductor integrated circuit device as defined in claim 11, wherein:
said other dummy pattern is formed with an area equal to or greater than that of the pattern prohibition region on the periphery of the pattern used for optical pattern recognition, and said first dummy pattern is not disposed in said pattern prohibition region.
- 13. A semiconductor integrated circuit device as defined in claim 11, wherein:
said other dummy pattern is formed in a scribe region of a semiconductor wafer, and said first and second dummy patterns are formed in a product region and scribe region of said semiconductor wafer.
- 14. A semiconductor integrated circuit device as defined in claim 1, wherein:
said first pattern is an active region pattern formed on said main surface, and said second pattern is a pattern formed in the same layer as a gate electrode forming said semiconductor element.
- 15. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first pattern comprising a dummy pattern on a main surface or any component layer of a semiconductor substrate on said main surface, (b) depositing an insulating film on said main surface on which said first pattern is formed, or on a component patterned on said first pattern, and polishing said insulating film to flatten the surface, and (c) forming a second pattern containing a pattern used for optical pattern recognition on an upper layer of said flattened surface, wherein said pattern used for optical pattern recognition is formed so as to be enclosed within the flat shape of said dummy pattern.
- 16. A method of manufacturing a semiconductor integrated circuit device as defined in claim 15, further comprising a step for optically detecting said pattern used for optical pattern recognition, and performing positional alignment of said semiconductor substrate.
- 17. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a first pattern comprising a dummy pattern on a main surface or any component layer of a semiconductor substrate on said main surface, (b) forming a second pattern comprising a pattern used for optical pattern recognition on an upper layer of said first pattern, and (c) optically detecting the pattern used for optical pattern recognition, and performing positional alignment of said semiconductor substrate, wherein said pattern used for optical pattern recognition is formed so as to being enclosed within the flat shape of said dummy pattern.
- 18. A method of manufacturing a semiconductor integrated circuit device as defined in claim 15, wherein:
said dummy pattern is formed with an area equal to or greater than a pattern prohibition region on the periphery of said pattern used for optical pattern recognition.
- 19. A method of manufacturing a semiconductor integrated circuit device as defined in claim 15, wherein:
said first pattern further comprises a first dummy pattern, said second pattern further comprises a second dummy pattern having a pattern pitch and pattern width of identical design dimensions to said first dummy pattern, and said second dummy pattern is formed on a space of said first dummy pattern in its flat surface position.
- 20. A method of manufacturing a semiconductor integrated circuit device as defined in claim 19, said method having one of:
a first configuration wherein one of the side edges of said second dummy pattern is formed so as to overlap with said first dummy pattern in its flat surface position, and a second configuration wherein said first dummy pattern and said second dummy pattern are offset by a distance of ½ pitch in its flat surface position.
- 21. A method of manufacturing a semiconductor integrated circuit device as defined in claim 15, wherein:
said dummy pattern is formed in a scribe region of a semiconductor wafer, and said first and second dummy patterns are formed in a product region and scribe region of said semiconductor wafer.
- 22. A method of manufacturing a semiconductor integrated circuit device as defined in claim 15, wherein:
a component to which said first pattern is transferred is a semiconductor substrate, and a component to which said second pattern is transferred is a gate electrode.
- 23. A semiconductor integrated circuit device as defined in claim 8, wherein:
said first pattern is an active region pattern formed on said main surface, and said second pattern is a pattern formed in the same layer as a gate electrode forming said semiconductor element.
- 24. A method of manufacturing a semiconductor integrated circuit device as defined in claim 17, wherein:
said dummy pattern is formed with an area equal to or greater than that of a pattern prohibition region on the periphery of said pattern used for optical pattern recognition.
- 25. A method of manufacturing a semiconductor integrated circuit device as defined in claim 17, wherein:
said first pattern further comprises a first dummy pattern, said second pattern further comprises a second dummy pattern having a pattern pitch and pattern width of identical design dimensions as said first dummy pattern, and said second dummy pattern is formed on a space of said first dummy pattern in its flat surface position.
- 26. A method of manufacturing a semiconductor integrated circuit device as defined in claim 17, wherein:
said dummy pattern is formed in a scribe region of a semiconductor wafer, and said first and second dummy patterns are formed in a product region and scribe region of said semiconductor wafer.
- 27. A method of manufacturing a semiconductor integrated circuit device as defined in claim 17, wherein:
a component to which said first pattern is transferred is a semiconductor substrate, and a component to which said second pattern is transferred is a gate electrode.
- 28. A method of manufacturing a semiconductor integrated circuit device as defined in claim 25, wherein:
one of the side edges of said second dummy pattern is formed so as to overlap said first dummy pattern in its flat surface position.
Priority Claims (1)
Number |
Date |
Country |
Kind |
11-345429 |
Dec 1999 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATION
[0001] This is a continuation of U.S. application Serial No. 09/692,450, filed Oct. 20, 2000, the subject matter of which is incorporated by reference herein.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09692450 |
Oct 2000 |
US |
Child |
10405615 |
Apr 2003 |
US |