Patent Application
20200194341
The present invention relates to a semiconductor package and a method of fabricating such semiconductor package, and more particularly, to a semiconductor package and a method of fabricating a semiconductor package having better heat dissipation and a method of fabricating such semiconductor package.
A conventional semiconductor package typically has weak heat dissipation. Therefore, such conventional semiconductor package is vulnerable to concentrated heat and malfunctions consequently. Such heat concentration easily occurs during the fabrication process of the conventional semiconductor package. For preventing damages to the conventional semiconductor package caused by heat, such heat concentration is required to be removed or neutralized.
The present disclosure aims at disclosing a semiconductor package for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip and a housing lid. The chip is disposed on the substrate layer. Also, the chip is electrically coupled to the substrate layer. Additionally, the chip is smaller than the substrate layer in area. The housing lid is disposed above the chip. Moreover, the housing lid covers the chip and the substrate layer. The housing lid, the chip and the substrate layer form an internal space. The internal space fills with a thermal interface material (TIM).
In one example, the thermal interface material includes a heat conductive liquid. In one example, the thermal interface material includes a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive.
In one example, the housing lid includes an inlet hole. The inlet hole allows the liquid-form TIM to flow into the internal space.
In one example, the semiconductor package further includes an inlet plug. The inlet plug blocks the inlet hole for stopping other liquid-form TIM from flowing into the internal space. Such that the liquid-form TIM is sealed inside the internal space. The inlet plug includes a screw. The inlet hole includes a lateral thread. Also, the screw detachably engages with the lateral thread for blocking the inlet hole.
In one example, the housing lid further includes an outlet hole. The outlet hole allows the liquid-form TIM to flow out of the internal space. Also, in another example, the semiconductor package further includes an inlet plug. And the inlet plug blocks the inlet hole for stopping other liquid-form TIM from flowing into the internal space via the inlet hole. The outlet plug blocks the outlet hole for stopping the liquid-form TIM from flowing out of the internal space via the outlet hole. The inlet plug and the outlet plug additionally seal the liquid-form TIM inside the internal space.
In one example, the inlet plug includes an inlet screw. The outlet plug includes an outlet screw. The inlet hole includes a first lateral thread. And the outlet hole includes a second lateral thread. Also, the inlet screw detachably engages with the first lateral thread for blocking the inlet hole. Additionally, the outlet screw detachably engages with the second lateral thread for blocking the outlet hole.
In one example, the semiconductor package further includes an adhesive layer. The adhesive layer is disposed between the housing lid and the substrate layer. Also, the adhesive layer substantially contacts both the housing lid and the substrate layer. Such that the housing lid is adhered with the substrate layer.
In one example, the substrate layer further includes a plurality of solder bumps. The solder bumps are configured disposed between the substrate layer and an external printed circuit board (PCB). Such that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
In one example, the substrate layer further includes a plurality of solder bumps. The solder bumps are sandwiched between the substrate layer and the chip. Such that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
The present disclosure also discloses a method of fabricating a semiconductor package. In the disclosed method, first, a chip is disposed above a substrate layer. Such that the chip is electrically coupled to the substrate layer. Additionally, the chip is smaller than the substrate layer in area. Second, a housing lid is disposed to cover the chip and the substrate layer. Third, an internal space is formed between the housing lid, the chip and the substrate layer.
Last, the internal space is filled with a liquid-form TIM.
In one example, an inlet hole is drilled on the housing lid. And the conductive liquid flows into the internal space via the inlet hole.
In one example, the inlet hole is additionally blocked to stop other liquid-form TIM from flowing into the internal space via the inlet hole and to seal the liquid-form TIM inside the internal space.
In one example, an outlet hole is additionally drilled on the housing lid. Also, at least part of the liquid-form TIM is driven to flow out of the internal space via the outlet hole.
In one example, the inlet hole is blocked to stop other liquid-form TIM from flowing into the internal space via the inlet hole. Moreover, the outlet hole is blocked to stop the liquid-form TIM from flowing out of the internal space via the outlet hole.
In one example, the housing lid is additionally adhered to the substrate layer.
In one example, a plurality of solder bumps is sandwiched between the substrate layer and an external PCB in a way that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps.
In one example, a plurality of solder bumps is additionally sandwiched between the substrate layer and the chip in a way that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
As mentioned above, the present disclosure discloses a semiconductor package that can improve heat dissipation. In this way, the semiconductor package can be substantially prevented from being damaged by over-concentrated heat during its fabrication process.
The chip 120 is disposed on the substrate layer 110. Also, the chip 120 is electrically coupled to the substrate layer 110. Additionally, the chip 120's area is smaller than that of the substrate layer 110.
The housing lid 130 is disposed above the chip 120. Also, the housing lid 130 covers the chip 120 and the substrate layer 110 from their top side.
The housing lid 130, the chip 120 and the substrate layer 110 form an internal space 140. In some examples, the internal space 140 fills with a liquid-form thermal interface material (TIM). Such liquid-form TIM flows inside the semiconductor package 100 while fabricating the semiconductor package 100. In this way, heat inside the semiconductor package 100 can be dissipated externally, and the semiconductor package 100 can be prevented from being damaged by concentrated heat.
In some examples, the TIM include a heat conductive liquid. In some other examples, the heat conductive liquid may include a silicon oil, a thermal grease, a thermal gel, a phase change liquid material, and/or a thermal conductive adhesive. The abovementioned exemplary materials for implementing the TIM are qualified for efficiently dissipating heat from a highly concentrated heat source within the semiconductor package 100. In some examples, the liquid-form TIM's thermal conductivity exceeds 10 W/(cm*K) or even 150 W/(cm*K), depending on the semiconductor packages 110's different heat-dissipating requirements.
In some examples, the housing lid 130 includes an inlet hole 150 for receiving the liquid-form TIM, as illustrated in
In some other examples, the inlet plug 160 is implemented using a screw. In addition, the inlet hole 150 further includes a lateral thread for receiving the screw. Such that the screw is detachably engaged with the lateral thread for blocking the inlet hole 150. Similarly, the screw blocks the liquid-form TIM within the internal space 140 and stops external liquid-form TIM from flowing into the inlet hole 150.
In some examples, the housing lid 130 further includes an outlet hole 170, as illustrated in
Similarly, in some examples, besides the inlet plug 160, the semiconductor package 100 further includes an outlet plug 180 for blocking the outlet hole 170, as illustrated in
Similarly, in some examples, both the inlet plug 160 and the outlet plug 180 are implemented using screws. In addition, both the inlet hole 150 and the outlet hole 170 have lateral threads. Such that the inlet plug 160 screws into the inlet hole 150 for blocking the inlet hole 150, and the outlet plug 180 screws into the outlet hole 160 for blocking the outlet hole 160.
In some examples, the semiconductor package 100 applies various numbers of inlet holes 160 and/or outlet holes 180, according to various requirements of cooling/solidifying the liquid-form TIM sealed within the internal space 140.
In some examples, the semiconductor package 100 also applies at least one adhesive layer 210, as illustrated in
In some examples, the semiconductor package 100 applies solder bumps for improving its electronic operations. Optionally, as illustrated in
The present disclosure also introduces a method of fabricating the semiconductor package 100. First, the chip 120 is disposed above the substrate layer 110 to render the chip 120 to be electrically coupled to the substrate layer 110. Second, the housing lid 130 is disposed to cover the chip 120 and the substrate layer 110. Third, the internal space 140 is formed between the housing lid 130, the chip 120 and the substrate layer 110. Last, the liquid-form TIM is filled into the internal space 140. Additionally, after performing an appropriate baking procedure, the liquid-form TIM is solidified within the internal space 140, such that the semiconductor package 110's electronic properties become stable.
In some examples, the inlet hole 150 is additionally drilled on the housing lid 130 for allowing the liquid-form
TIM to flow into the internal space 140. Also, the inlet plug 160 is used for blocking the inlet hole 150 to seal the liquid-form TIM within the internal space 140.
Similarly, in some examples, the outlet hole 170 is further drilled on the housing lid 130 for allowing the liquid-form TIM to flow out of the internal space 140. Moreover, the outlet plug 180 is used for blocking the outlet hole 170 for sealing the liquid-form TIM within the internal space 140. In some examples, the housing lid 130 is at least partially adhered to the substrate layer, e.g., with the aid of the at least one adhesive layer 210.
In some examples, the solder bumps 220 are sandwiched between the substrate layer 110 and the external PCB for enabling mutual electronic operations. Similarly, in some examples, the solder bumps 230 are disposed between the substrate layer 110 and the chip 120 for enabling mutual electronic operations.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the benefit of U.S. Provisional Application No. 62/780,932, filed on Dec. 18, 2018 and entitled “ SEMICONDUCTOR TESTING DEVICE AND PACKAGE”, the contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62780932 | Dec 2018 | US |
