Patent Application
20250038145
The present invention relates to semiconductor technology, and, in particular, to a semiconductor package structure that includes a capacitor.
In addition to providing a semiconductor die with protection from environmental contaminants, a semiconductor package structure can also provide an electrical connection between the semiconductor die packaged inside it and a substrate such as a printed circuit board (PCB).
Although existing semiconductor package structures generally meet requirements, they have not been satisfactory in all respects. For example, more and more metal layers in the package substrate are needed to meet demands for high electrical signal performance. However, as the size of semiconductor package structures becomes larger, package substrate warpage becomes a critical issue. Therefore, further improvements in semiconductor package structures are required.
Semiconductor package structures are provided. An exemplary embodiment of a semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a core structure, an integrated capacitor structure, and a redistribution layer. The integrated capacitor structure is embedded in the core structure. The redistribution layer is disposed over the integrated capacitor structure. The semiconductor die is disposed over the package substrate and is thermally coupled to the integrated capacitor structure through the redistribution layer.
Another embodiment of a semiconductor package structure includes a package substrate. The package substrate includes a core structure, a first capacitor, a second capacitor, a first insulating filler, a first redistribution layer, and a second redistribution layer. The first capacitor and the second capacitor are stacked vertically and are embedded in the core structure. The first insulating filler is disposed in the core structure and surrounds the first capacitor and the second capacitor. The first redistribution layer is disposed below the core structure. The second redistribution layer is disposed over the core structure and is electrically coupled to the first capacitor and the second capacitor.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The present disclosure will be described with respect to particular embodiments and with reference to certain drawings, but the disclosure is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the disclosure.
Additional elements may be added on the basis of the embodiments described below. For example, the description of “a first element on/over a second element” may include embodiments in which the first element is in direct contact with the second element, and may also include embodiments in which additional elements are disposed between the first element and the second element such that the first element and the second element are not in direct contact.
Furthermore, the description of “a first element extending through a second element” may include embodiments in which the first element is disposed in the second element and extends from a side of the second element to an opposite side of the second element, wherein a surface of the first element may be substantially leveled with a surface of the second element, or a surface of the first element may be outside a surface of the second element.
The spatially relative descriptors of the first element and the second element may change as the structure is operated or used in different orientations. In addition, the present disclosure may repeat reference numerals and/or letters in the various embodiments. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.
In semiconductor packages, such as a laptop central processing unit (CPU) package structure, a silicon capacitor embedded in a substrate may be adopted for decoupling performance enhancement. However, the embedded solution is limited to thin core structure due to the thickness of the silicon capacitor. If the core structure which is not thick enough, the package substrate warpage may occur, and the warpage may become severe as the size of the package substrate increases.
In view of this, a semiconductor package structure including an integrated capacitor structure is described in accordance with some embodiments of the present disclosure. The integrated capacitor structure including stacked capacitors is embedded in a core structure. As such, the thickness of the core structure can be increased to fulfill requirement of large size of the package substrate.
As illustrated in
Then, a plurality of openings 104 and a cavity 112 are formed in the core structure 102, in accordance with some embodiments. The openings 104 and the cavity 112 may be formed through the core structure 102 by laser drilling or any suitable methods. According to some embodiments, the openings 104 and the cavity 112 are formed simultaneously.
Afterwards, as shown in
The capacitors 114 and 116 may include silicon capacitors. The thickness D1 of the core structure 102 may be substantially equal to the thickness D2 of the integrated capacitor structure 118. Since the thickness D2 of the embedded integrated capacitor structure 118 is greater than the thickness of any one of capacitors 114 and 116, the thickness D1 of the core structure 102 can be increased. As a result, the warpage of the package substrate can be reduced. Decoupling performance enhancement can be achieved as well.
In some embodiments, the thickness D2 of the integrated capacitor structure 118 is in a range of about 0.8 mm to about 1.4 mm, such as about 1.0 mm. The thickness D1 of the core structure 102 may be in a range of about 0.8 mm to about 1.4 mm, such as about 1.0 mm.
The capacitors 114 and 116 may be assembled back-to-back. In particular, the backside surface 114b of the capacitor 114 may face the backside surface 116b of the capacitor 116. The frontside surface 114f of the capacitor 114 may be substantially aligned with the bottom surface 102a of the core structure 112, and the frontside surface 116f of the capacitor 116 may be substantially aligned with a top surface 102b of the core structure 112. This allows subsequent layers (such as a redistribution layer) to be formed on flat surfaces.
The capacitors 114 and 116 may be bonded using an adhesive layer 115. The adhesive layer 115 may be a die attach film or any suitable materials. Alternatively, the capacitors 114 and 116 may be bonded using fusion bonding, hybrid bonding, or any suitable methods. Fusion bonding may include dielectric-to-dielectric bonding and/or conductor-to-conductor bonding. Hybrid bonding may be a combination of dielectric-to-dielectric bonding and conductor-to-conductor bonding, which may be metal-to-metal direct bonding, such as copper-to-copper direct bonding. When hybrid bonding or metal-to-metal bonding is utilized, the thermal dissipation efficiency may be further enhanced compared to dielectric-to-dielectric bonding or die attach film.
One or more active and passive devices (not shown) may also be disposed in the core structure 102 for the structural and functional requirements of the design. For example, the active and passive devices may include transistors, capacitors, resistors, the like, or a combination thereof.
Then, an insulating filler 120 is formed in the cavity 112 to secure the integrated capacitor structure 118, in accordance with some embodiments. The insulating filler 112 may be formed by filling an insulating material, such as resin, in the space between the cavity 112 and the integrated capacitor structure 118.
Due to the properties of the insulating filler 120, the thickness D3 of the insulating filler 120 may be equal to or less than 0.6 mm. Therefore, the top surface of the insulating filler 112 may be lower the top surface 102b of the core structure 102. The thickness D3 of the insulating filler 120 may be less than the thickness D1 of the core structure 102 and may be less than the thickness D2 of the integrated capacitor structure 118. That is, the insulating filler 120 may surround the bottom portion of the integrated capacitor structure 118 and may expose the top portion of the integrated capacitor structure 118.
Then, as shown in
Afterwards, an insulating filler 108 is formed in each of the through vias 106, in accordance with some embodiments. The insulating filler 108 may be formed by filling an insulating material, such as resin, in the space surrounded by the through vias 106. Then, grinding may be performed to remove excess insulating material to form a flat surface. The bottom surface of the insulating filler 108 and the bottom surface of the insulating filler 112 may be substantially coplanar with the bottom surface 102a of the core structure 102.
Afterwards, as shown in
Then, dielectric layers 122 are filled in the space remaining in the cavity 112, in accordance with some embodiments. The dielectric layers 122 may surround the top portion of the integrated capacitor structure 118 and may be in contact with the insulating filler 120. The dielectric layers 122 may be a build-up film, and may be formed of dielectric material, including Ajinomoto build-up film (ABF) or another suitable material. The dielectric layers 122 may be formed by a lamination process, a coating process, or another suitable process.
Additional dielectric layers 122 may be formed on opposite surfaces of the core structure 102 and may be patterned to form openings (not illustrated) therein. The openings may be through holes or trenches. Then, routing layers 124 may be formed in the openings. The routing layers 124 may include horizontal interconnects, such as conductive layers or conductive pads, and vertical interconnects, such as conductive vias. The conductive vias may electrically couple different levels of the conductive layers and the conductive pads. The routing layers 124 may be formed by plating or any suitable methods. The routing layers 124 may be formed of a material similar to that of the through vias 106, including copper, silver, gold, the like, an alloy thereof, or a combination thereof.
The routing layers 124 may be electrically coupled to the through vias 106 and the integrated capacitor structure 118. The dielectric layers 122 and the routing layers 124 may be referred to as a redistribution layer 126. The redistribution layer 126 on opposite surfaces of the core structure 102 may be electrically coupled to each other through the through vias 106.
Then, a solder resist 128 is formed over the dielectric layers 122 to protect the redistribution layer from external damage, in accordance with some embodiments. A package substrate 101 is formed.
Afterwards, as illustrated in
Afterwards, semiconductor dies 130 and 132 are disposed over the package substrate 101, in accordance with some embodiments. A plurality of conductive connectors 136 may be formed below the semiconductor dies 130 and 132 to connect the solder connectors 134. The semiconductor dies 130 and 132 may be electrically coupled to the routing layers 124 through the solder connectors 134 and the conductive connectors 136.
The conductive connectors 136 may include microbumps, controlled collapse chip connection (C4) bumps, conductive pillars, the like, or a combination thereof. The conductive connectors 136 may be formed of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, an alloy thereof, or a combination thereof.
In some embodiments, the semiconductor dies 130 and 132 each independently includes a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, the like, or a combination thereof. For example, the semiconductor dies 130 and 132 may include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a radio frequency front end (RFFE) die, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (IO) die, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) die, an application specific integrated circuit (ASIC) die, the like, or a combination thereof.
The integrated capacitor structure 118 may be electrically coupled to the semiconductor die 130 and/or semiconductor die 132 through the routing layer 124 and through vias 108. The integrated capacitor structure 118 may be placed closer to the semiconductor die that needs more power to prevent voltage drop, such as the semiconductor die 132. In other words, the integrated capacitor structure 118 may be placed directly under the semiconductor die 130 or the semiconductor die 132. For example, as shown in
It should be noted that the two semiconductor dies 130 and 132 are for illustrative purposes only, and more semiconductor dies may be disposed over the package substrate 101. In addition, one or more passive components (such as resistors, capacitors, or inductors) may also be disposed over the package substrate 101.
A plurality of conductive terminals 138 are disposed on the surface of the package substrate 101 opposite to the semiconductor dies 130 and 132, in accordance with some embodiments. A semiconductor package structure 100 is formed. The conductive terminals 138 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. The conductive terminals 138 may be formed of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, the like, an alloy thereof, or a combination thereof. The conductive terminals 138 may be electrically coupled to the routing layers 124.
As illustrated in
Then, as shown in
Afterwards, as illustrated in
As illustrated in
The thickness and width of the dummy die 202 and the thickness and width of the capacitor 116 may be substantially the same as illustrated, or may be different. The thickness of the dummy die 202 may be adjusted according to the required thickness of the core substrate 102.
As illustrated in
The integrated capacitor structure 118 may include a dummy die, such as the capacitor 114 or the capacitor 116 may be replaced with a dummy die, similar to those described with reference to
As illustrated in
According to some embodiments, the thicknesses of the capacitors 114 and 116 are different as well, similar to those described with reference to
The integrated capacitor structure 118 may include a dummy die, such as the capacitor 114 or the capacitor 116 may be replaced with a dummy die, similar to those described with reference to
As shown in
The capacitors 114 and 116 may be bonded using fusion bonding, hybrid bonding, or any suitable methods. In some embodiments, the capacitors 114 and 116 are assembled face-to-face, and the capacitors 114 and 116 are electrically coupled to the semiconductor die 130 and/or the semiconductor die 132 through the through vias 302 and the routing layers 124, as shown in
Although the sizes of the capacitors 114 and 116 are substantially the same as illustrated, the sizes of the capacitors 114 and 116 may be different, as those discussed in
As illustrated in
In summary, the semiconductor package structure according to the present disclosure includes an integrated capacitor structure which is embedded in a core structure of a package substrate. The integrated capacitor structure includes stacked capacitors. Therefore, the thickness of the core structure can be increased, so that the warpage of the package substrate can be reduced. Furthermore, decoupling performance enhancement can be achieved.
While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
This application claims the benefit of U.S. Provisional Application No. 63/516,179 filed on Jul. 28, 2023, the entirety of which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 63516179 | Jul 2023 | US |
