Patent Application
20110278739
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package having capacitively coupled signal pads.
2. Description of the Related Art
The conventional semiconductor package 1 has the following disadvantages. A dielectric layer 14 has to be disposed between the first chip 12 and the second substrate 15, so the thermal stability of fine pitch is decreased, the thickness of the semiconductor package 1 is increased and the manufacturing cost is increased.
Therefore, it is necessary to provide a semiconductor package to solve the above problems.
The present invention is directed to a semiconductor package. The semiconductor package comprises a substrate, a first chip and an interposer. The substrate has a receiving surface. The first chip is mechanically and electrically connected to the substrate. The first chip comprises a first major surface, a first back surface, a plurality of first signal pads, a plurality of second signal pads, at least one first power pad, at least one second power pad and at least one first through-chip via. The first back surface faces the receiving surface of the substrate. The first signal pads are disposed adjacent to the first major surface. The second signal pads are disposed adjacent to the first back surface, and the first signal pads are electrically connected to the substrate via the second signal pads. The first power pad is disposed adjacent to the first major surface. The second power pad is disposed adjacent to the first back surface. The first through-chip via electrically connects the first power pad and the second power pad.
The interposer is mechanically and electrically connected to the first chip. The interposer comprises a first surface, a second surface, a plurality of third signal pads, a redistribution layer, at least one first through silicon via, at least one third power pad and at least one second through silicon via. The first surface faces the first major surface of the first chip. The third signal pads are disposed adjacent to the first surface and capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. The redistribution layer is disposed adjacent to the second surface, and has a plurality of fourth signal pads and at least one fourth power pad. The first through silicon via electrically connects the third signal pads and the fourth signal pads. The third power pad is disposed adjacent to the first surface. The second through silicon via electrically connects the third power pad and the fourth power pad.
The present invention is further directed to a semiconductor package. The semiconductor package comprises a substrate, a third chip and a fourth chip. The substrate has a receiving surface. The third chip is electrically connected to the substrate. The third chip comprises a third major surface, a third back surface, a plurality of sixth signal pads, a plurality of seventh signal pads, at least one second through-chip via, at least one sixth power pad, at least one seventh power pad and at least one third through-chip via. The third major surface faces the receiving surface of the substrate. The is sixth signal pads are disposed adjacent to the third major surface. The seventh signal pads are disposed adjacent to the third back surface. The second through-chip via electrically connects the sixth signal pads and the seventh signal pads. The sixth power pad is disposed adjacent to the third major surface. The seventh power pad is disposed adjacent to the third back surface. The third through-chip via electrically connects the sixth power pad and the seventh power pad.
The fourth chip is electrically connected to the third chip. The fourth chip comprises a fourth major surface, a plurality of eighth signal pads and at least one eighth power pad. The fourth major surface faces the third back surface of the third chip. The eighth signal pads are disposed adjacent to the fourth major surface and capacitively coupled to the seventh signal pads of the third chip, so as to provide proximity communication between the third chip and the fourth chip. The eighth power pad is disposed adjacent to the fourth major surface and electrically connected to the seventh power pad of the third chip.
Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.
The substrate 21 has a receiving surface 211. The first chip 22 is mechanically and electrically connected to the substrate 21 by the first conductive element 25. The first chip 22 has an active circuitry (not shown) embedded therein. The first chip 22 comprises a first major surface 221, a first back surface 222, a plurality of first signal pads 223, a plurality of second signal pads 224, at least one first power pad 225, at least one second power pad 226, at least one first through-chip via 227, at least one first ground pad 228, at least one second ground pad 229 and at least one fourth through-chip via 230. The first back surface 222 faces the receiving surface 211 of the substrate 21. The first signal pads 223 are disposed adjacent to the first major surface 221. The second signal pads 224 are disposed adjacent to the first back surface 222, and the first signal pads 223 are electrically connected to the substrate 21 via the second signal pads 224, respectively. The first power pad 225 and the first ground pad 228 are disposed adjacent to the first major surface 221. The second power pad 226 and the second ground pad 229 are disposed adjacent to the first back surface 222. The first through-chip via 227 electrically connects the first power pad 225 and the second power pad 226. The first power pad 225 and the second power pad 226 are used for transmitting electrical power. The fourth through-chip via 230 electrically connects the first ground pad 228 and the second ground pad 229.
The interposer 23 is mechanically and electrically connected to the first chip 22. The interposer 23 may be formed from an inactive silicon wafer without an active circuitry embedded therein. The interposer 23 comprises a first surface 231, a second surface 232, a plurality of third signal pads 233, a redistribution layer 234, at least one first through silicon via 235, at least one third power pad 236, at least one second through silicon via 237, at least one third ground pad 241 and at least one fifth through silicon via 242. The first surface 231 faces the first major surface 221 of the first chip 22. The third signal pads 233 are disposed adjacent to the first surface 231 and capacitively coupled to the first signal pads 223 of the first chip 22, so as to provide proximity communication between the first chip 22 and the interposer 23. The redistribution layer 234 is disposed adjacent to the second surface 232, and has a plurality of fourth signal pads 238, at least one fourth power pad 239 and at least one fourth ground pad 243. The first through silicon via 235 electrically connects the third signal pads 233 and the fourth signal pads 238. The third power pad 236 and the third ground pad 241 are disposed adjacent to the first surface 231. The second through silicon via 237 electrically connects the third power pad 236 and the fourth power pad 239. The third power pad 236 and the fourth power pad 239 are used for transmitting electrical power. The fifth through silicon via 242 electrically connects the third ground pad 241 and the fourth ground pad 243.
It should be noted that the first chip 22 and the interposer 23 communicate with each other through proximity communication between the first signal pads 223 and the third signal pads 233, instead of direct electrical connections; however, electrical power or ground is transmitted between the first chip 22 and the interposer 23 through direct electrical connections (e.g., the second conductive element 26 such as solder bumps or copper pillars).
In order to achieve the function of proximity communication, part of the first chip 22 and the interposer 23 are placed face-to-face in a manner that aligns the transmitter circuit with the receiver circuit in extremely close proximity, for example, with only microns of separation between them. The signals between the transmitter circuit and the receiver circuit may be transmitted by inductive or capacitive coupling with low overall communication cost.
Take transmission by capacitive coupling for example. The first signal pads 223 of the first chip 22 and the third signal pads 233 of the interposer 23 are aligned with each other. Since the first signal pads 223 and the third signal pads 233 are not in physical contact with each other, there are capacitances between the first signal pads 223 of the first chip 22 and the third signal pads 233 of the interposer 23. It is this capacitive coupling that provides signal paths between the first chip 22 and the interposer 23. Changes in the electrical potential of the first signal pads 223 of the first chip 22 cause corresponding changes in the electrical potential of the corresponding third signal pads 233 of the interposer 23. Suitable drivers of the transmitter circuit and sensing circuits of the receiver circuit in the first chip 22 and the interposer 23 make communication through this small capacitance possible.
In the embodiment, the first passive device 24 is disposed adjacent to the interposer 23. The first conductive element 25 is used for connecting the first chip 22 and the substrate 21, and preferably, the first conductive element 25 is a solder ball. The second conductive element 26 is used for connecting the first chip 22 and the interposer 23, and preferably, the second conductive element 26 is a bump or a metal pillar.
In this embodiment, the interposer 23 is used for distributing finer pitch connections of the second chip 27 stacked above to the third signal pads 233 which are capable of capacitively coupling to the first signal pads 223 of the first chip 22.
The substrate 51 has a receiving surface 511. The third chip 52 is electrically connected to the substrate 51. The third chip 52 comprises a third major surface 521, a third back surface 522, a plurality of sixth signal pads 523, a plurality of seventh signal pads 524, at least one second through-chip via 525, at least one sixth power pad 526, at least one seventh power pad 527, at least one third through-chip via 528, at least one sixth ground pad 529, at least one seventh ground pad 530 and at least one fifth through-chip via 531. The third major surface 521 faces the receiving surface 511 of the substrate 51. The sixth signal pads 523 are disposed adjacent to the third major surface 521. The seventh signal pads 524 are disposed adjacent to the third back surface 522. The second through-chip via 525 electrically connects the sixth signal pads 523 and the seventh signal pads 524. The sixth power pad 526 and the sixth ground pad 529 are disposed adjacent to the third major surface 521. The seventh power pad 527 and the seventh ground pad 530 are disposed adjacent to the third back surface 522. The third through-chip via 528 electrically connects the sixth power pad 526 and the seventh power pad 527. The fifth through-chip via 531 electrically connects the sixth ground pad 529 and the seventh ground pad 530.
The fourth chip 53 is electrically connected to the third chip 52. The fourth chip 53 comprises a fourth major surface 531, a plurality of eighth signal pads 532, at least one eighth power pad 533, at least one eighth ground pad 534. The fourth major surface 531 faces the third back surface 522 of the third chip 52. The eighth signal pads 532 are disposed adjacent to the fourth major surface 531 and capacitively coupled to the seventh signal pads 524 of the third chip 52, so as to provide proximity communication between the third chip 52 and the fourth chip 53. The eighth power pad 533 and the eighth ground pad 534 are disposed adjacent to the fourth major surface 531 and electrically connected to the seventh power pad 527 and the seventh ground pad 530 of the third chip 52, respectively.
In the embodiment, the second passive device 54 is disposed adjacent to the third chip 52. The fourth conductive element 55 is used for connecting the third chip 52 and the substrate 51, and preferably, the fourth conductive element 55 is a solder ball. The fifth conductive element 56 is used for connecting the third chip 52 and the fourth chip 53, and preferably, the fifth conductive element 56 is a bump or a metal pillar.
The substrate 61 has a receiving surface 611. The interposer 62 is electrically connected to the substrate 61. The interposer 62 comprises a first surface 621, a second surface 622, a plurality of eighth signal pads 623, a plurality of ninth signal pads 624, at least one third through silicon via 625, at least one ninth power pad 626, at least one tenth power pad 627, at least one fourth through silicon via 628, at least one ninth ground pad 629, at least one tenth ground pad 630 and at least one sixth through silicon via 631. The first surface 621 faces the receiving surface 611 of the substrate 61. The eighth signal pads 623 are disposed adjacent to the first surface 621. The ninth signal pads 624 are disposed adjacent to the second surface 622. The third through silicon via 625 electrically connects the eighth signal pads 623 and the ninth signal pads 624. The ninth power pad 626 and the ninth ground pad 629 are disposed adjacent to the first surface 621. The tenth power pad 627 and the tenth ground pad 630 are disposed adjacent to the second surface 622. The fourth through silicon via 628 electrically connects the ninth power pad 626 and the tenth power pad 627. The sixth through silicon via 631 electrically connects the ninth ground pad 629 and the tenth ground pad 630.
The fifth chip 63 is electrically connected to the interposer 62. The fifth chip 63 comprises a fifth major surface 631, a plurality of tenth signal pads 632, at least one eleventh power pad 633 and at least one eleventh ground pad 634. The fifth major surface 631 faces the second surface 622 of the interposer 62. The tenth signal pads 632 are disposed adjacent to the fifth major surface 631 and capacitively coupled to the ninth signal pads 624 of the interposer 62, so as to provide proximity communication between the interposer 62 and the fifth chip 63. The eleventh power pad 633 and the eleventh ground pad 634 are disposed adjacent to the fifth major surface 631 and electrically connected to the tenth power pad 627 and the tenth ground pad 630 of the interposer 62, respectively. In the embodiment, the third passive device 64 is disposed adjacent to the interposer 62. The sixth conductive element 65 is used for connecting the interposer 62 and the substrate 61, and preferably, the sixth conductive element 65 is a solder ball. The seventh conductive element 66 is used for connecting the interposer 62 and the fifth chip 63, and preferably, the seventh conductive element 66 is a bump or a metal pillar.
Whereby, the capacitively coupled signal pads 223, 235, 524, 532, 624, 632 can be made in fine pitch, and therefore the size of the semiconductor package 2, 3, 4, 5, 6 is reduced and the density of the signal pads 223, 235, 524, 532, 624, 632 is increased.
While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined by the appended claims.
