The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of computation nodes.
As the artificial intellectual (AI) models have been applied to more and more fields, a demand for suitable hardware having greater computation capability also raises. Since the AI models usually require large amounts of parallel computing, most of the computation hardware includes multiple cores, which requires large circuit area. Furthermore, to improve the computation efficiency, data sharing and/or data switching among different cores is also desired. However, to enable data sharing and/or data switching, connections between cores can be complicated and require even larger area. Therefore, providing a semiconductor structure that can facilitate greater computation capability within a smaller area has become an issue to be solved.
One aspect of the present disclosure provides a semiconductor package. The semiconductor package includes a silicon interposer, a redistribution layer (RDL), a plurality of computation nodes, a plurality of through silicon vias (TSVs), and a plurality of bumps. The RDL is disposed on a first surface of the silicon interposer, and the plurality of computation nodes are disposed on the RDL. Each of the computation nodes includes a computation die. The RDL is disposed between the computation nodes and the silicon interposer. Each of computation dies of the computation nodes incudes a plurality of micro bumps, and the computation dies are bonded to the RDL through the micro bumps. The TSVs pass through the silicon interposer. The plurality of bumps are disposed on a second surface of the silicon interposer and coupled to the RDL through the TSVs. Each two adjacent computation nodes of the computation nodes are coupled to each other through the RDL. From the top view, the RDL includes interconnect structures distributed in portions that overlap the computation nodes and portions free from overlapping the computation nodes.
Another aspect of the present disclosure provides a semiconductor device. The semiconductor device include a printed circuit board (PCB) and the semiconductor package. The semiconductor package is bonded to the PCB through the plurality of bumps.
Another aspect of the present disclosure provides a method for manufacturing a semiconductor package. The method includes receiving a silicon interposer, forming a plurality of through silicon vias (TSVs) within the silicon interposer, forming a redistribution layer (RDL) on a first surface of the silicon interposer, receiving a plurality of computation nodes, disposing the computation nodes on the RDL, grinding a backside the silicon interposer to expose the plurality of TSVs, and forming a plurality of bumps on a second surface of the silicon interposer and coupled to the plurality of TSVs, wherein the bumps are coupled to the RDL through the TSVs. Each of the computation nodes includes a computation die, and each of computation dies of the computation nodes includes a plurality of micro bumps. The step of disposing the computation nodes on the RDL includes bonding the computation dies of the computation nodes to the RDL through the micro bumps, wherein the RDL is between the computation nodes and the silicon interposer. Each two adjacent computation nodes of the computation nodes are coupled to each other through the RDL. From a top view, the RDL includes interconnect structures distributed in portions that overlap the computation nodes and portions free from overlapping the computation nodes.
A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures.
The following description accompanies drawings, which are incorporated in and constitute a part of this specification, and which illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
References to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may
In order to make the present disclosure completely comprehensible, detailed steps and structures are provided in the following description. Obviously, implementation of the present disclosure does not limit special details known by persons skilled in the art. In addition, known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. Preferred embodiments of the present disclosure will be described below in detail. However, in addition to the detailed description, the present disclosure may also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, and is defined by the claims.
In the present embodiment, each of the computation nodes 130 may include a computation die 132. The computation die 132 can be a system on chip (SoC) that include one or more computation cores. Furthermore, each of computation dies 132 of the computation nodes 130 includes a plurality of micro bumps 1321. The computation dies 132 can be bonded to the RDL 120 through the micro bumps 1321. For example, the micro bumps 1321 can be bonded to conductive contacts 124 formed on the RDL 120. In the present embodiment, each two adjacent computation nodes 130 can be coupled with each other through the RDL 120. Thus, resources of adjacent computation nodes 130 can be shared each other, and the computation data can be transferred between adjacent computation nodes 130.
In some embodiments, each of the computation nodes 130 may be coupled to more than one computation node 130 so as to support a variety of computation flows more flexibly. Since communications between the computation nodes 130 can be achieved by utilizing intra-package traces provided by the RDL 120, the transmission time for resource sharing and data transferring can be shortened, therefore, the computing efficiency can be improved and the power consumption can be reduced.
In the present embodiment, each of the computation nodes 130 may further include a plurality of high bandwidth memory (HBM) dies 134. Each of the HBM dies is disposed on the RDL 120 in close proximity to the computation die 132. In some embodiments, each of the HBM dies can include micro bumps 1341, and the HBM dies can be bonded to the RDL 120 through the micro bumps 1341. For example, the micro bumps 1341 can be bonded to conductive contacts 124 formed on the RDL 120. Therefore, the computing core(s) in the computation dies 132 can access the memory spaces in the HBM dies 134 through the conductive traces provided by the RDL 120.
In the present embodiments, the semiconductor package 100 further includes a plurality of underfills 150 and an encapsulating layer 160 for protecting the computation nodes 130. As shown in
The encapsulating layer 160 can be disposed on the RDL 120 and surrounding each of the computation nodes 130. In such case, from a top view, the underfills 150 surrounding the computation nodes 130 can be isolated from each other by the encapsulating layer 160. However, the present disclosure is not limited thereto. In some embodiments, the underfills 150 and the encapsulating layer 160 can be replaced by using a molding underfill (MUF) material that can both underfill the gaps between the RDL 120 and the computation nodes 130 and mold the dies of the computation nodes 130 in one process.
Furthermore, as shown in
In the present embodiment, the semiconductor package 100 further includes a plurality of input/output dies 140. The input/output dies 140 can convert the digital signal generated by the computation nodes 130 into analog signal and transmit the analog signals to external circuits. Also, the input/output dies 140 can convert the analog signal received from external circuits into digital signals, and transmit the digital signals to the computation nodes 130.
In the present embodiment, the input/output dies 140 is disposed on the RDL 120 and surrounds the computation nodes 130.
As shown in
In addition, it may be noted that, in
Furthermore, in the embodiment shown in
In the present embodiment, the semiconductor package 100 can be a wafer level package (WLP), that is, the silicon interposer 110 can be a silicon wafer, and the RDL 120 can be formed on the silicon interposer 110 by semiconductor processes. Therefore, the computing power of the plurality of computation nodes 130 can be embedded within one package, thereby achieving a system on wafer (SoW) that has great computation capability within a small area.
According to method 200, the silicon interposer 110 is received in step S210, and the TSVs 170 can be formed in the silicon interposer 110 in step S220. After the TSVs 170 are formed, the RDL 120 can be formed on the first surface 110A of the silicon interposer 110 in step S230 so that the RDL 120 can be coupled to the TSVs 170. In some embodiments, to form the RDL 120 distributed over a large area for providing conductive paths connecting computation nodes, the step S230 may be performed with a mask stitching technique.
As shown in
In some embodiments, the four series of masks are adopted for lithography in an interactive manner. For example, to pattern a photoresist layer or an inter-layer insulating layer of the RDL 120, a first mask of the first series of masks is applied to expose patterns on the regions A1, and then a first mask of the second series of masks is applied to expose patterns on the regions B1. Sequentially, a first mask of the third series of masks is applied to expose patterns on the regions C1, and then a first mask of the fourth series of masks is applied to expose patterns on the regions D1. After the patterns are exposed on the regions A1, B1, C1, and D1, a solvent may be applied on the photoresist layer or the inter-layer insulating layer to develop the desired patterns of the RDL 120. Similarly, a second mask of the first series of mask, a second mask of the second series of mask, a second mask of the third series of mask, and a second mask of the fourth series of mask can be utilized sequentially to pattern a next photoresist layer or a next insulating layer, and so on.
In the present embodiment, since all the regions A1 are formed by the same series of masks, the first rectangular regions A1 will have same sizes and same patterns of interconnect structures 122. Similarly, the second rectangular regions B1 will have same sizes and same patterns of interconnect structures 122, the third rectangular regions C1 will have same sizes and same patterns of interconnect structures 122, and the fourth rectangular regions D1 will have same sizes and same patterns of interconnect structures 122.
In addition, as shown in
In addition, as shown in
Similarly, the RDL 120 may further includes rectangular regions E1, F1, G1, and H1 surrounding the first rectangular regions A1, B1, C1 and D1. The rectangular regions E1, F1, G1, and H1 may be formed by utilizing a fifth series of masks, a sixth series of masks, a seventh series of masks, and an eighth series of masks respectively. Therefore, the rectangular regions E1 may have same sizes and same patterns of interconnect structures 122, the rectangular regions F1 may have same sizes and same patterns of interconnect structures 122, the rectangular regions G1 may have same sizes and same patterns of interconnect structures 122, and the rectangular regions H1 may have same sizes and same patterns of interconnect structures 122, In the present embodiments the input/output dies 140 may be disposed on the rectangular regions E1, F1, G1, and H1 correspondingly.
In some embodiments, the sizes of the masks used to form the computation dies 132 and the first rectangular regions A1, B1, C1, and D1 may be substantially the same. For example, the computation dies 132 and the regions A1, B1, C1, and D1 may all have sizes around 26 mm×33 mm. However, by stitching different series of masks, the total area of the semiconductor package 100 can be 200 mm×200 mm or even larger.
Furthermore, in some embodiments, to accommodate the interconnect structures 122 used for connections between the computation nodes 130, adjacent computation nodes 130 may be disposed by a certain spacing. For example, a spacing between each adjacent computation nodes 130 may be greater than one third of a length of each computation node 130. As shown in
In addition, to ensure the integrity of the conductive paths that cross boundaries between two different regions formed by different series of masks, certain design rules may be followed. For example, as shown in
Although the RDL 120 of the semiconductor package 100 includes eight types of regions A1, B1, C1, D1, E1, F1, G1, and H1 and is formed by stitching eighth series of masks, the present disclosure is not limited thereto.
In such case, from the top view, each of the computation nodes 230 may overlap one rectangular region A2 and one rectangular region B2. Also, the input/output dies 140 may be each disposed in a rectangular region E2 or G2. Furthermore, in some embodiments, the RDL may be formed by stitching by even more series of masks (e.g. more than eight), according to the needs.
After the RDL 120 is formed, the computation nodes 130 including the computation dies 132, the HBM dies 134 can be received in steps S240. Also, as shown in
In step S260, gaps between the RDL 120 and the computation nodes 130 can be filled by utilizing a plurality of underfills 150 that surrounds the micro bumps 1321 of each of the computation dies 132 and the micro bumps 1341 of each of the HBM dies 134. In step S270, an encapsulating layer 160 can be applied on the RDL 120 and surrounding each of the computation nodes 130. In some embodiments, from the top view, the underfills 150 surrounding the computation nodes 130 can be isolated from each other by the encapsulating layer 160. Furthermore, in the present embodiment, the encapsulating layer 160 can be grinded to expose the backsides of the computation dies 132, the HBM dies 134, and the input/output dies 140 so as to reduce the thickness of the semiconductor package 100. However, the present disclosure is not limited thereto.
In step S280, the backside of the silicon interposer 110 is grinded so as to expose the TSVs 170, and thus, in step S290, the bumps 180 can be formed on the second surface 110B of the silicon interposer 110 and coupled to the TSVs 170. In the present embodiment, the bumps 180 can be coupled to the RDL 120 through the TSVs 170. As a result, the semiconductor package 100 can be formed.
In summary, the semiconductor packages, the semiconductor devices and the method for manufacturing the semiconductor packages can include a plurality of computation nodes in a wafer level package (WLP) so as to allow fast data sharing between different computation nodes and support a variety of computation flows more flexibly. As a result, compared to the conventional package, the semiconductor package provided by the embodiments of the present disclosure can achieve greater computation capability within a smaller area.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.
This application claims the benefit of prior-filed U.S. provisional application No. 63/479,582, filed on Jan. 12, 2023, which is incorporated by reference in its entirety.
Number | Date | Country | |
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63479582 | Jan 2023 | US |