Patent Application
20250006685
The present application generally relates to semiconductor technologies, and more particularly, to a semiconductor package with multiple types of conductive components.
The wiring used for interconnection within a semiconductor chip is extremely fine, being of the order of a few microns, or less, in width. The ability to form such wires has made possible for semiconductor chips containing millions or more interconnected components. At some point, however, contacts are required between the chips and the outside world where working to such small tolerances of wiring is not possible.
In order for connecting semiconductor chips to external devices or systems, printed circuit boards (PCB), interposers, or other similar substrates are widely used for mounting the chips thereon, thereby forming semiconductor packages having bigger sizes. The wiring on a PCB is much coarser than on a chip, being typically measured in millimeters. It is not practical to connect chip wiring directly to PCB wiring. Therefore, an intermediate structure, capable of handling both ends of this wire-width spectrum, is needed.
An example of such a structure is a ball grid array (BGA). BGA packaging technology is a surface mounting technology applied to integrated circuits, which is commonly used to permanently fix devices such as microprocessors. The BGA package is an array on the bottom of a package substrate, and solder balls are used as input/output (I/O) terminals of the circuits and connected to a PCB.
The solder ball has the function of signal conduction, electrical connection, and heat conduction. In the existing BGA package, the solder balls on the package substrate are generally the same. The larger the solder ball, the stronger the heat transfer capability. However, at the same time, the larger the solder ball, the larger the substrate area occupied, which is contrary to the high density and high pin output of the BGA.
Therefore, a need exists for further improvement to semiconductor packages.
An objective of the present application is to provide a semiconductor package structure with improved heat dissipation efficiency.
According to an aspect of the present application, a semiconductor package is disclosed. The semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; a plurality of electronic components mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the plurality sets of front conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the first-type conductive components are connected to a first electronic component of the plurality of electronic components, and the second-type conductive components are connected to a second electronic component of the plurality of electronic components; and wherein a thermal conductivity of the first-type conductive components is higher than that of the second-type conductive components, and a power consumption of the first electronic component is higher than that of the second electronic component.
According to another aspect of the present application, a semiconductor package is disclosed. The semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; an electronic component package mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the electronic component package comprises a plurality of circuit functional parts, wherein the plurality sets of front conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the set of first-type conductive components are connected to a first circuit functional part of the plurality of circuit functional parts, and the set of second-type conductive components are connected to a second circuit functional part of the plurality of circuit functional parts; and wherein a thermal conductivity of the first-type conductive components is higher than the second-type conductive components, and a power consumption of the first circuit functional part is higher than that of the second circuit functional part.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention. Further, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The drawings referenced herein form a part of the specification. Features shown in the drawing illustrate only some embodiments of the application, and not of all embodiments of the application, unless the detailed description explicitly indicates otherwise, and readers of the specification should not make implications to the contrary.
The same reference numbers will be used throughout the drawings to refer to the same or like parts.
The following detailed description of exemplary embodiments of the application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the application. Those skilled in the art may further utilize other embodiments of the application, and make logical, mechanical, and other changes without departing from the spirit or scope of the application. Readers of the following detailed description should, therefore, not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiment of the application.
In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of “or” means “and/or” unless stated otherwise. Furthermore, the use of the term “including” as well as other forms such as “includes” and “included” is not limiting. In addition, terms such as “element” or “component” encompass both elements and components including one unit, and elements and components that include more than one subunit, unless specifically stated otherwise. Additionally, the section headings used herein are for organizational purposes only, and are not to be construed as limiting the subject matter described.
As used herein, spatially relative terms, such as “beneath”, “below”, “above”, “over”, “on”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “side” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
The inventors of the present application have found that, due to increased integration, many semiconductor packages will mount multiple semiconductor chips to a same substrate, or mount an electronic component package integrated with multiple circuit functional parts to a same substrate. These different semiconductor chips or circuit functional parts often have different power consumption, which leads to different requirements of heat dissipation capabilities. When heat is generated by the semiconductor chips and the package, most of the heat is transferred to the outside of the semiconductor packages through the package substrate where they are located. But the package structures are generally made of epoxy resin and filler and other low thermal conductivity materials. Therefore, when the semiconductor chips, due to a long time of operation, produce a lot of heat, the package structures may not be able to conduct heat in time, resulting in the heat being trapped in the chips.
In order to resolve at least one of the problems described above, a multiple-type conductive component array is proposed by the inventors of the present application to interconnect electronic component or electronic component package with package substrates. For example, solder balls with copper cores or similar higher thermal conductivity materials may be used, as well as solder balls made of lower thermal conductivity soldering material such as tin. These high thermal conductivity conductive components may establish thermal paths with improved heat dissipation capability for the semiconductor package, thereby reducing significantly the risk of failures of the semiconductor packages due to accumulated heat.
As shown in
The package substrate 125 further includes a set of front conductive patterns 110, such as contact pads, formed on the front surface 119, and a set of rear conductive patterns 120, such as contact pads, formed on the rear surface 129. The front and rear conductive patterns may be respective end surfaces of a set of interconnect s 130 embedded in the insulating layer of the package substrate 125, which are exposed from either the front surface 119 or the rear surface 129. The set of interconnects 130 can electrically couple the set of front conductive patterns 110 with the set of rear conductive patterns 120, respectively. In some embodiments, the interconnects 130 may include conductive wiring or vias to route signals through the insulating layer, as aforementioned.
At least one electronic component 115 is mounted to the front surface 119 of the package substrate 125. The electronic component or components can be in the form of a semiconductor die or dice. In some embodiments, the at least one electronic component 115 may include one or more digital chips, analog chips or mixed signal chips, such as application-specific integrated circuit (“ASIC”) chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. In some other embodiments, the at least one electronic component 115 may also include one or more passive electrical components such as resistors, capacitors, inductors, etc. In the embodiment shown in
The semiconductor package 100 further includes a set of front solder balls 210 and a set of rear solder balls 220. As front conductive components and rear conductive components, front solder balls 210 and rear solder balls 220 are electrically connected to the set of front and rear conductive patterns 110, 120, respectively. The electronic component 115 is electrically coupled to the set of front conductive patterns 110 via the set of front solder balls 210 to establish electrical connection with the package substrate 125.
In particular, the front and rear solder balls 210 and 220 can be deposited on the package substrate 125 in the form of balls or similar structures. As can be seen from
The set of front solder balls 210 include at least two types of solder balls, i.e., a plurality of first-type solder balls 111 and a plurality of second-type solder balls 112. Similarly, the set of rear solder balls 220 include at least two types of solder balls, i.e., a plurality of first-type solder balls 121 and a plurality of second-type solder balls 122. In the illustrated embodiments, the first-type solder balls 111, 121 can include a copper core and a soldering material coating outside the copper core, while the second-type solder balls 112, 122 can be made solely of the soldering material such as tin. In some other embodiments, the first-type solder balls 111, 121 may be made of other soldering material(s) that have better thermal conductivity. Compared to the second-type solder balls 112, 122, the first-type solder balls 111, 121 may have a greater thermal and electrical conductivity, therefore allowing better heat conductivity and lower electrical resistance. In some embodiments, the first-type solder balls 111, 121 are preferably located in a region of the electronic component 115 that consumes more power and generate more heat than the other regions of the electronic component 115, because more heat is required to be conducted through the first-type solder balls 111, 121. In some embodiments, the electronic component 115 is a semiconductor chip, which may have different circuit functional parts, such as a logic circuit part, a power circuit part, a control circuit part or a storage circuit part and so on. Among them, because complex operations such as logic operations are required, the logic circuit part usually has a relatively high power consumption; and the power circuit part usually also has a relatively high power consumption due to power supply and other requirements; while the control circuit or storage circuit has a relatively low power consumption. Therefore, the first-type solder balls 111 and/or 121 can be arranged in a region of the electronic component 115 corresponding to the logic circuit part, the power circuit part, while the second-type solder balls 112 and/or 122 can be arranged in the region of the electronic component 115 corresponding to the control circuit or the storage circuit. In some other embodiments, the first-type solder balls 111, 121 are preferably located in a region of the electronic component 115 that needs better heat dissipation than the other regions of the electronic component 115. For example, the first-type solder balls 111, 121 are at least located in a central region of the package substrate 125, which may have the longest heat dissipation path than the other regions (e.g., peripheral regions) of the package substrate 125. Furthermore, as mentioned above, the first-type solder ball 121 on the back side of the package substrate 125 can further improve the heat transfer capability of the semiconductor package 100, especially for those regions that require better heat dissipation.
Although thermal conductivity may be a factor desired to be considered for the multiple types of solder balls mounted on the package substrate 125, some other factors or characteristics may be considered as well. In some embodiments, at least one set of the sets of front solder balls 210 and the set of rear solder balls 220 may further include one or more third-type solder balls, which may be made at least partially of a material having a thermal expansion coefficient smaller than the first-type solder balls and the second-type solder balls, or at least close to the substrate material (for example, resin) of the package substrate 125. For example, in the embodiment shown in
In some preferred embodiments, such as the embodiment shown in
The semiconductor package 100 may further include at least one encapsulant layer 116 extending at least partially on the substrate 125 and covering the at least one electronic component 115. The encapsulant layer 116 may provide protection for the electronic component 115. In some embodiments, a shielding layer (not shown) may be further formed over the encapsulant layer 116 for electromagnetic interference shielding purpose.
In the embodiment, a set of front solder balls 410 is mounted on a front surface of a package substrate 425. The set of front solder balls 410 include, at a central region of the package substrate 425 below the logic circuit chip, a plurality of first-type solder balls 411, for electrical and thermal conduction, coupled respectively to a first-type solder ball 421 belonging to a set of rear solder balls 420 which are mounted on a rear surface of the package substrate 425. The set of front solder balls 410 further includes, below the power chip, a plurality of first-type solder balls 411, for high current transmission, coupled respectively to second-type and third-type solder balls 422 and 423 belonging to the set of rear solder balls 420. The set of front solder balls 410 further includes, below the control chip, a plurality of second-type solder balls 412, for weak current transmission, coupled respectively to second-type and third-type solder balls 422 and 423 belonging to the set of rear solder balls 420. It can be understood that, compared with the control circuit chip connected by the second-type solder balls 412, the logic circuit chip and the power circuit chip connected by the first-type solder balls 411 have significantly higher power consumption, therefore, the first-type solder balls 411 having relatively high thermal conductivity can better assist logic circuit chip and power circuit chip to dissipate heat through the package substrate 425.
As illustrated in
In some embodiments, the electronic components encapsulated in the semiconductor packages may be other components such as chip-lets or other similar smaller packages.
Similar as the embodiment shown in
In some examples, the front conductive components 810 may employ multiple different types of components to connect different electronic components 815 to the package substrate 825, specifically, to respective interconnect paths 850 in the package substrate 825. Specifically, the front conductive component 810 includes a first-type solder ball 811 under the power chip, a second-type solder ball 812 under the control chip, and a plurality of conductive pillars 813 under the logic circuit chip in the central region of the package substrate 825. It can be seen that, compared with the semiconductor package 400 shown in
It can be understood that, similar to the semiconductor package 400 shown in
For the rear conductive components 820, rear solder balls 420 similar to those shown in
It can be seen that different types of electronic components 815 are connected through a variety of different types of conductive components 810, especially according to the heat dissipation requirements of different types of chips, which can satisfy the requirement of these electronic components 815 to achieve better heat dissipation, thereby improving the reliability of the overall semiconductor package. It should be noted that although a plurality of electronic components 815 are shown in
While the semiconductor package of the present application is described in conjunction with corresponding figures, it will be understood by those skilled in the art that modifications and adaptations to the semiconductor package may be made without departing from the scope of the present invention.
The discussion herein includes numerous illustrative figures that show various portions of a semiconductor package. For illustrative clarity, such figures do not show all aspects of each example semiconductor package. Any of the example semiconductor packages provided herein may share any or all characteristics with any or all other semiconductor packages provided herein.
Various embodiments have been described herein with reference to the accompanying drawings. It will, however, be evident that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the claims that follow. Further, other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of one or more embodiments of the invention disclosed herein. It is intended, therefore, that this application and the examples herein be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following listing of exemplary claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310802142.9 | Jun 2023 | CN | national |
