Semiconductor substrates having low defects and methods of manufacturing the same

Abstract

A semiconductor substrate includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. At least one amorphous region and at least one crystalloid region are formed in the first semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer and is crystal-grown from the at least one crystalloid region. A method of manufacturing a semiconductor substrate includes preparing a growth substrate; crystal-growing the first semiconductor layer on the growth substrate; forming the at least one amorphous region and the at least one crystalloid region in the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer using the at least one amorphous region as a mask and the at least one crystalloid region as a seed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects and advantages will become more apparent and more readily appreciated from the following detailed description of example embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic cross-sectional view of a semiconductor substrate according to an example embodiment;

FIGS. 2A through 2G illustrate a method of manufacturing a semiconductor substrate according to an example embodiment;

FIGS. 3A through 3F illustrate a method of manufacturing a semiconductor substrate according to another example embodiment;

FIG. 4 is a schematic cross-sectional view of a light-emitting device according to an example embodiment; and

FIGS. 5A through 5C illustrate a method of manufacturing a light-emitting device according to an example embodiment.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference to the accompanying drawings. Embodiments, however, may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

It will be understood that when an element is referred to as being “on,” “connected to,” or “coupled to” to another component, it may be directly on, connected to, or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element component, region, layer, and/or section from another element, component, region, layer, and/or section. For example, a first element, component, region, layer, and/or section could be termed a second element, component, region, layer, and/or section without departing from the teachings of the example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one component and/or feature to another component and/or feature, or other component(s) and/or feature(s), as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Reference will now be made to example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like components throughout.

FIG. 1 is a schematic cross-sectional view of a semiconductor substrate according to an example embodiment. Referring to FIG. 1, the semiconductor substrate may include a first semiconductor layer 12 and/or a second semiconductor layer 20 that are sequentially formed on the growth substrate 10.

The first semiconductor layer 12 may be formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. An amorphous region 12b formed by ion-bombardment damage and/or a crystalloid region 12a that results from non-bombardment may be formed in the first semiconductor layer 12. At this time, the amorphous region 12b and the crystalloid region 12a may be repeatedly and/or alternately formed on the first semiconductor layer 12. And the second semiconductor layer 20 may include at least one vertical growth region 20a crystal-grown vertically from the at least one crystalloid region 12a and at least one lateral growth region 20b crystal-grown laterally from the at least one vertical growth region 20a.

Since the growth substrate 10 may include one or more of sapphire, 6H—SiC, MgAl₂O₃, Si(111), and ZnO, generally, the first semiconductor layer 12 formed on the different kind of growth substrate 10 may be formed to have a thickness greater than or equal to about 1 μm and less than or equal to about 5 μm and may include a defect density greater than or equal to about 10⁸ defects/cm² and less than or equal to about 10¹⁰ defects/cm². However, in the structure of the semiconductor substrate of FIG. 1, a defect density of the second semiconductor layer 20 epitaxially grown on the first semiconductor layer 12 may be greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm². In detail, the at least one crystalloid region 12a may be vertically, laterally, or vertically and laterally crystal-grown by, for example, metal organic chemical vapor deposition (MOCVD) using the at least one amorphous region 12b as one or more masks for suppressing crystal growth and using the at least one crystalloid region 12a as one or more seeds for crystal growth, thereby forming the second semiconductor layer 20, having a lower defect density than that of the first semiconductor layer 12, on the first semiconductor layer 12. Here, a defect density of the at least one vertical growth region 20a may be greater than or equal to about 10⁸ defects/cm² and less than or equal to about 10¹⁰ defects/cm² and a defect density of the at least one lateral growth region 20b may be greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm².

In this case, the second semiconductor layer 20 may be formed of material having the same lattice parameter and thermal expansion coefficient as that of material used in forming the first semiconductor layer 12 (or material having a sufficiently small difference in lattice parameter and thermal expansion coefficient from that of material used in forming the first semiconductor layer 12) so that epitaxial growth can be easily performed. For example, the second semiconductor layer 20 may be formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material, that may be the same material or materials used in forming the first semiconductor layer 12. Here, the II-VI-group semiconductor material may include, for example, ZnO and the III-V-group semiconductor material may include, for example, one or more of GaN, GaAs, and InP.

The width of the at least one amorphous region 12b may be greater than or equal to about 2 μm and less than or equal to about 30 μm, which is a value obtained by considering the efficiency of lateral growth using the seed. The second semiconductor layer 20 may be effectively epitaxially-grown within a width range greater than or equal to about 2 μm and less than or equal to about 30 μm in a short time. A thickness of the at least one amorphous region 12b may be greater than or equal to about 1 Å and less than or equal to about 5000 Å. The at least one amorphous region 12b should be thick enough to function as a mask for suppressing crystal growth, but does not need to be thicker than about 5000 Å. For a similar reason, when the thickness of the at least one amorphous region 12b is too small, that is, is less than about 1 Å, the at least one amorphous region 12b may not function as the mask. As a result, the thickness of the at least one amorphous region 12b should be greater than or equal to about 1 Å.

The width of the at least one crystalloid region 12a may be greater than or equal to about 1 μm and less than or equal to about 20 μm, which is a value obtained by considering a size suitable for serving as the seed for crystal growth. Here, since the amorphous region 12b and the crystalloid region 12a may be repeatedly and/or alternately formed on the first semiconductor layer 12, there is a correlation between the disposal and arrangement thereof, but many shape(s) and/or pattern(s) may be used. For example, the at least one crystalloid region 12a may be formed in a dot pattern or patterns, or in a substantially circular pattern. In addition, the at least one amorphous region 12b and the at least one crystalloid region 12a may be formed in a striped pattern or patterns. The striped pattern or patterns may be formed in or substantially in a <1-100> direction so that the lateral growth may be performed in or substantially in a <11-20> direction. As a result of the lateral growth, a coalescence region of the second semiconductor layer 20 may be formed on the at least one amorphous region 12b and a surface morphology property may be shown in the coalescence region. A sound zone shown in FIG. 1 denotes a low-defect density region that may be caused by the lateral growth.

According to example embodiments, since a mask made of a different material such as SiO₂ or SiN_x in related art GaN growth using epitaxial lateral overgrowth (ELOG) or Pendeo-epitaxy is not used, but the at least one amorphous region 12b formed by ion-bombardment damage is used as a mask, strain may be uniformly distributed in the GaN thin film, that is, in the second semiconductor layer 20. In addition, since the thermal conductivity of the at least one amorphous region 12b is higher than that of SiO₂, the thermal reliability of an optoelectronic device, such as a light-emitting diode (LED) or a laser diode (LD), implemented on the at least one amorphous region 12b, may be improved.

FIGS. 2A through 2G illustrate a method of manufacturing a semiconductor substrate according to an example embodiment. Here, each material layer may be formed by halide or hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), and/or vapor deposition, such as sputtering and/or evaporation.

Referring to FIG. 2A, a growth substrate 10 suitable for lattice matching for the growth of II-VI-group semiconductor layer(s) and/or III-V-group semiconductor layer(s) may be prepared. For example, the growth substrate 10 may include one or more of sapphire, 6H—SiC, MgAl₂O₃, Si(111), and ZnO. Next, a first semiconductor layer 12 is crystal-grown on the growth substrate 10 using II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. Here, the II-VI-group semiconductor material may include, for example, ZnO, and the III-V-group semiconductor material may include, for example, one or more of GaN, GaAs, and InP. The thickness of the first semiconductor layer 12 may be greater than or equal to about 1 μm and less than or equal to about 5 μm. And a defect density of the first semiconductor layer 12 grown on a different kind of the growth substrate 10 in this way may include a defect density greater than or equal to about 10⁸ defects/cm² and less than or equal to about 10¹⁰ defects/cm².

Referring to FIGS. 2B through 2D, the amorphous region 12b caused by a bombardment damage and the crystalloid region 12a that results from non-bombardment may be repeatedly and/or alternately formed on the first semiconductor layer 12 by applying ion bombardment to a portion of the surface of the first semiconductor layer 12.

Specifically, first, referring to FIG. 2B, a mask layer 100 in a pattern (such as a pattern or patterns of posts, a dot pattern or patterns, and/or a striped pattern or patterns) for partly exposing the top surface of the first semiconductor layer 12 may be formed on the first semiconductor layer 12. The mask layer 100 may be formed, for example, of photoresist, metal, or photoresist and metal.

Referring to FIG. 2C, the at least one amorphous region 12b caused by ion-bombardment damage is formed by applying ion bombardment to the exposed top surface of the first semiconductor layer 12 according to the pattern of the mask layer 100. The ion bombardment may include ions from one or more of B, P, As, Sb, BF₂, In, Ar, N, and Zn. And the ion bombardment may be performed at an absolute pressure of less than about 10⁻⁵ torr. In detail, the ions may be supplied by one or more of a radio frequency (RF)-ion source, a discharge-type ion source, a surface ionization source, and a hot electron source.

The thickness of the at least one amorphous region 12b may be greater than or equal to about 1 Å and less than or equal to about 5000 Å, and the width thereof may be greater than or equal to about 2 μm and less than or equal to about 30 μm. The at least one amorphous region 12b should be thick enough to function as a mask for suppressing crystal growth, but does not need to be thicker than about 5000 Å. For a similar reason, when the thickness of the at least one amorphous region 12b is too small, that is, is less than about 1 Å, the at least one amorphous region 12b may not function as the mask. As a result, the thickness of the at least one amorphous region 12b should be greater than or equal to about 1 Å.

Referring to FIG. 2D, the at least one crystalloid region 12a that results from non-bombardment may be exposed by removing the mask layer 100. The width of the at least one crystalloid region 12a may be greater than or equal to about 1 μm and less than or equal to about 20 μm. The width may be very suitable as a seed for crystal growth.

Referring to FIGS. 2E through 2G, the at least one crystalloid region 12a may be vertically, laterally, or vertically and laterally crystal-grown by, for example, metal organic chemical vapor deposition (MOCVD) using the at least one amorphous region 12b as a mask for suppressing crystal growth and using the at least one crystalloid region 12a as a seed for crystal growth, thereby forming a second semiconductor layer 20, that may have a lower defect density than that of the first semiconductor layer 12, on the first semiconductor layer 12. The second semiconductor layer 20 may include at least one vertical growth region 20a crystal-grown vertically from the at least one amorphous region 12b and at least one lateral growth region 20b crystal-grown laterally from the at least one vertical growth region 20a. A defect density of the second semiconductor layer 20 may be greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm². In detail, a defect density of the vertical growth region 20a may be greater than or equal to about 10⁸ defects/cm² and less than or equal to about 10¹⁰ defects/cm² and a defect density of the lateral growth region 20b may be greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm². In this case, the second semiconductor layer 20 may be formed of material having the same lattice parameter and thermal expansion coefficient as that of material used in forming the first semiconductor layer 12 (or material having a sufficiently small difference in lattice parameter and thermal expansion coefficient from that of material used in forming the first semiconductor layer 12) so that epitaxial growth can be easily performed. For example, the second semiconductor layer 20 may be formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material, that may be the same material or materials used in forming the first semiconductor layer 12.

In the current embodiment, the at least one amorphous region 12b and the at least one crystalloid region 12a may be formed in a striped pattern or patterns in or substantially in a <1-100> direction. As a result, the lateral growth of the at least one amorphous region 12b may be performed in or substantially in a <11-20> direction. In particular, GaN may show an excellent growth property in or substantially in the <11-20> direction.

FIGS. 3A through 3F illustrate a method of manufacturing a semiconductor substrate according to another example embodiment. Most processes of the current embodiment are similar to those of the example embodiments of FIGS. 2A through 2G. Thus, a description of repeated processes will be omitted and the current example embodiment will be described with reference to differences in the processes.

Referring to FIGS. 3A and 3B, a first semiconductor layer 42 may be crystal-grown on a growth substrate 40 using II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. Then, a mask layer 100 in a pattern (such as a pattern or patterns of posts, a dot pattern or patterns, and/or a striped pattern or patterns) for partly exposing the top surface of the first semiconductor layer 42 may be formed on the first semiconductor layer 42. These processes may be similar to those of the embodiment of FIGS. 2A and 2B.

Referring to FIG. 3C, at least one amorphous region 42b caused by bombardment damage is formed by applying ion bombardment to the exposed top surface of the first semiconductor layer 42 according to the pattern of the mask layer 100. In this case, there is a difference between the current embodiment and the previous embodiment of FIGS. 2A through 2G in that a depth of greater than or equal to about 0.1 μm and less than or equal to about 4 μm is etched from the exposed top surface of the first semiconductor layer 42 by applying the ion bombardment and the at least one amorphous region 42b is formed in the first semiconductor layer 42 on the etched surface.

As in the previous embodiment of FIGS. 2A through 2G, the ion bombardment may include ions from one or more of B, P, As, Sb, BF₂, In, Ar, N, and Zn. And the ion bombardment may be performed at an absolute pressure of less than about 10⁻⁵ torr. In detail, the ions may be supplied by one or more of a radio frequency (RF)-ion source, a discharge-type ion source, a surface ionization source, and a hot electron source. In addition, the thickness of the at least one amorphous region 42b may be greater than or equal to about 1 Å and less than or equal to about 5000 Å, and the width thereof may be greater than or equal to about 2 μm and less than or equal to about 30 μm.

Referring to FIG. 3D, the at least one crystalloid region 42a that results from non-bombardment may be exposed by removing the mask layer 100. As a result of etching, the at least one crystalloid region 42a may have a three-dimensional (3D) shape, that is, a protruded shape. This protruded shape may be more advantageous to crystal growth to a lateral side. The width of the at least one crystalloid region 42a may be greater than or equal to about 1 μm and less than or equal to about 20 μm. A scanning electron microscopy (SEM) photo showing the surface of the first semiconductor layer 42 patterned by the etching is shown in FIG. 3D.

Referring to FIGS. 3E and 3F, the at least one crystalloid region 42a may be vertically, laterally, or vertically and laterally crystal-grown by, for example, metal organic chemical vapor deposition (MOCVD) using the at least one amorphous region 42b as a mask for suppressing crystal growth and using the at least one crystalloid region 42a as a seed for crystal growth, thereby forming a second semiconductor layer 50, having a lower defect density than that of the first semiconductor layer 42, on the first semiconductor layer 42. The second semiconductor layer 50 may include at least one vertical growth region 50a crystal-grown vertically from the at least one crystalloid region 42a and at least one lateral growth region 50b crystal-grown laterally from the at least one crystalloid region 42a. A defect density of the second semiconductor layer 50 may be greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm². In detail, a defect density of the at least one vertical growth region 50a may be greater than or equal to about 10⁸ defects/cm² and less than or equal to about 10¹⁰ defects/cm² and a defect density of the at least one lateral growth region 50b may be greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm².

FIG. 4 is a schematic cross-sectional view of a semiconductor light-emitting device according to an example embodiment. Referring to FIG. 4, the semiconductor light-emitting device may be characterized by including a semiconductor substrate manufactured according to FIGS. 2A through 2G and a semiconductor chip may be formed on the semiconductor substrate.

The semiconductor substrate may include a first semiconductor layer 12 and a second semiconductor layer 20 that may be sequentially formed on a growth substrate 10. The first semiconductor layer 12 may be formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. The first semiconductor layer 12 may include an amorphous region 12b formed by ion-bombardment damage and a crystalloid region 12a that results from non-bombardment. In this case, the amorphous region 12b and the crystalloid region 12a may be repeatedly and/or alternately formed on the first semiconductor layer 12. The second semiconductor layer 20 may include at least one vertical growth region 20a crystal-grown vertically from the at least one crystalloid region 12a and at least one lateral growth region 20b crystal-grown laterally from the at least one vertical growth region 20a. Here, the structure of the semiconductor substrate manufactured according to FIGS. 2A through 2G and a method of manufacturing the same have been already described. Thus, a repeated description of the semiconductor substrate will be omitted and the structure of the semiconductor chip will be described.

The semiconductor chip may include an n-electrode 120, a p-electrode 140, an n-type semiconductor layer 110 disposed therebetween, an active layer 112, and/or a p-type semiconductor layer 114. In detail, the n-type semiconductor layer 110, the active layer 112, and/or the p-type semiconductor layer 114 may be sequentially stacked on the second semiconductor layer 20, and a portion of the uppermost surface of the p-type semiconductor layer 114 may be etched to about a depth of the n-type semiconductor layer 110 so that the n-type semiconductor layer 110 may be exposed. The n-electrode 120 may be formed on the exposed surface of the n-type semiconductor layer 110, and the p-electrode 140 may be formed on the uppermost surface of the p-type semiconductor layer 114. In a GaN-based semiconductor light-emitting device having the above structure, if a voltage is applied between the n-electrode 120 and the p-electrode 140, electrons and holes may be injected into the active layer 112 from the n-type semiconductor layer 110 and the p-type semiconductor layer 114, respectively, and the electrons and the holes may coalesce within the active layer 112 so that light can be emitted from the active layer 112.

According to example embodiments, since the second semiconductor layer 20 may have a low defect density, greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm², and an excellent surface morphology property, the optical output property of the light-emitting device implemented on the second semiconductor layer 20 may be improved and the thermal reliability of the light-emitting device may be improved so that the life time of the light-emitting device may be increased.

The n-type semiconductor layer 110 may be formed of an AlInGaN-based III-V-group nitride semiconductor material, for example, an n-GaN layer. The active layer 112 may be a GaN-based III-V-group nitride semiconductor layer that is In_xAl_yGa_1-x-yN (0≦x≦1, 0≦y≦1 and 0≦x+y≦1), for example, an InGaN layer or an AlGaN layer. Here, the active layer 112 may be formed, for example, of multi-quantum well (hereinafter, referred to as ‘MQW’) structure and/or single quantum well structure. One of ordinary skill in the art may envision other structures for the active layer 112. For example, the active layer 112 may be formed of a GaN/InGaN/GaN MQW or GaN/AlGaN/GaN MQW structure. And the p-type semiconductor layer 114 may be a p-GaN-based III-V-group nitride semiconductor layer, for example, a p-GaN layer or a p-GaN/AlGaN layer.

The n-electrode 120 and the p-electrode 140 may be formed of conductive material, for example, metal(s) such as Au, Al, or Ag, or transparent conductive oxide. The transparent conductive oxide may include one or more of indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), In₄Sn₃O₁₂, and Zn_1-xMg_xO(Zinc Magnesium Oxide, 0≦x≦1). Examples include Zn₂In₂O₅, GaInO₃, ZnSnO₃, F-doped SnO₂, Al-doped ZnO, Ga-doped ZnO, MgO, and ZnO.

FIGS. 5A through 5C illustrate a method of manufacturing a semiconductor light-emitting device according to an example embodiment. Methods of manufacturing semiconductor substrates illustrated in FIGS. 2A through 2G have been already described. Thus, a repeated description of the semiconductor substrate will be omitted and a method of manufacturing a semiconductor chip will be described. Here, each material layer may be formed by halide or hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), and/or vapor deposition, such as sputtering and/or evaporation. These methods are well-known and, thus, a detailed description thereof will be omitted.

Referring to FIG. 5A, after a semiconductor substrate may be manufactured according to FIGS. 2A through 2G, a n-type semiconductor layer 110, an active layer 112, and/or a p-type semiconductor layer 114 may be sequentially formed on the semiconductor substrate.

Specifically, after a growth substrate 10 suitable for lattice matching for the growth of a II-VI-group semiconductor layer and/or a III-V-group semiconductor layer is prepared, a first semiconductor layer 12 is crystal-grown on the growth substrate 10 using II-VI-group semiconductor material, III-VI-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. Then, an amorphous region 12b caused by a bombardment damage and a crystalloid region 12a that results from non-bombardment may be repeatedly and/or alternately formed on the first semiconductor layer 12 by partly applying ion bombardment to the surface of the first semiconductor layer 12. Next, the at least one crystalloid region 12a may be vertically, laterally, or vertically and laterally crystal-grown by, for example, metal organic chemical vapor deposition (MOCVD) using the at least one amorphous region 12b as a mask for suppressing crystal growth and using the at least one crystalloid region 12a as a seed for crystal growth, thereby forming a second semiconductor layer 20, having a lower defect density than that of the first semiconductor layer 12, on the first semiconductor layer 12.

Next, the n-type semiconductor layer 110, the active layer 112, and/or the p-type semiconductor layer 114 may be sequentially formed on the second semiconductor layer 20. The n-type semiconductor layer 110 may be formed of an AlInGaN-based III-V-group nitride semiconductor material, for example, an n-GaN layer. The active layer 112 may be a GaN-based III-V-group nitride semiconductor layer that is In_xAl_yGa_1-x-yN (0≦x≦1, 0≦y≦1, and 0≦x+y≦1), for example, an InGaN layer and/or an AlGaN layer. Here, the active layer 112 may be formed, for example, of MQW structure and/or single quantum well structure. One of ordinary skill in the art may envision other structures for the active layer 112. For example, the active layer 112 may be formed of a GaN/InGaN/GaN MQW and/or GaN/AlGaN/GaN MQW structure. And, the p-type semiconductor layer 114 may be a p-GaN-based III-V-group nitride semiconductor layer, for example, a p-GaN layer or a p-GaN/AlGaN layer.

Referring to FIGS. 5B and 5C, a region of a top surface of the p-type semiconductor layer 114 may be etched to about a depth of the n-type semiconductor layer 110, thereby forming an etched surface in the n-type semiconductor layer 110. Then, an n-electrode 120 and a p-electrode 140 may be formed using conductive material, for example, metal(s) such as Au, Al, or Ag, or a transparent conductive oxide, on the etched surface of the n-type semiconductor layer 110 and on the p-type semiconductor layer 114.

According to example embodiments, a low-defect semiconductor substrate having a low defect density, greater than or equal to about 10⁴ defects/cm² and less than or equal to about 10⁷ defects/cm², and having an excellent surface morphology property may be manufactured by a simple and easy process. The semiconductor substrate may be used as a substrate for manufacturing optoelectronic devices such as GaN-based light-emitting diodes (LED) or laser diodes (LD) such that the life time and/or reliability of the optoelectronic devices are improved.

While example embodiments have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A semiconductor substrate, comprising: a first semiconductor layer; anda second semiconductor layer;wherein the first semiconductor layer is formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material,wherein at least one amorphous region is formed in the first semiconductor layer,wherein at least one crystalloid region is formed in the first semiconductor layer,wherein the second semiconductor layer is formed on the first semiconductor layer, andwherein the second semiconductor layer is crystal-grown from the at least one crystalloid region.

2. The semiconductor substrate of claim 1, wherein the at least one amorphous region is formed by ion-bombardment damage.

3. The semiconductor substrate of claim 1, wherein the second semiconductor layer comprises: at least one vertical growth region crystal-grown vertically from the at least one crystalloid region; andat least one lateral growth region crystal-grown laterally from the at least one vertical growth region.

4. The semiconductor substrate of claim 1, wherein the III-V-group semiconductor material comprises one or more of GaN, GaAs, and InP.

5. The semiconductor substrate of claim 1, wherein a thickness of the first semiconductor layer is greater than or equal to about 1 μm and less than or equal to about 5 μm.

6. The semiconductor substrate of claim 1, wherein a width of the at least one amorphous region is greater than or equal to about 2 μm and less than or equal to about 30 μm.

7. The semiconductor substrate of claim 1, wherein a thickness of the at least one amorphous region is greater than or equal to about 1 Å and less than or equal to about 5000 Å.

8. The semiconductor substrate of claim 1, wherein a width of the at least one crystalloid region is greater than or equal to about 1 μm and less than or equal to about 20 μm.

9. The semiconductor substrate of claim 1, wherein the at least one amorphous region and the at least one crystalloid region are formed in a striped pattern or patterns.

10. The semiconductor substrate of claim 9, wherein the striped pattern is formed or the striped patterns are formed substantially in a <1-100> direction.

11. The semiconductor substrate of claim 3, wherein the lateral growth occurs substantially in a <11-20> direction.

12. The semiconductor substrate of claim 1, wherein a defect density of the first semiconductor layer is greater than or equal to about 108 defects/cm2 and less than or equal to about 1010 defects/cm2.

13. The semiconductor substrate of claim 1, wherein a defect density of the second semiconductor layer is greater than or equal to about 104 defects/cm2 and less than or equal to about 107 defects/cm2.

14. The semiconductor substrate of claim 3, wherein a defect density of the at least one vertical growth region is greater than or equal to about 108 defects/cm2 and less than or equal to about 1010 defects/cm2.

15. The semiconductor substrate of claim 3, wherein a defect density of the at least one lateral growth region is greater than or equal to about 104 defects/cm2 and less than or equal to about 107 defects/cm2.

16. The semiconductor substrate of claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed of one or more nitride semiconductors.

17. A method of manufacturing a semiconductor substrate, the method comprising: preparing a growth substrate;crystal-growing a first semiconductor layer on the growth substrate using II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material;forming at least one amorphous region in the first semiconductor layer;forming at least one crystalloid region in the first semiconductor layer; andforming a second semiconductor layer on the first semiconductor layer using the at least one amorphous region as a mask and the at least one crystalloid region as a seed;wherein the second semiconductor layer has a lower defect density than the first semiconductor layer.

18. The method of claim 17, wherein the at least one amorphous region is formed by applying ion bombardment to a portion of a surface of the first semiconductor layer.

19. The method of claim 17, wherein the second semiconductor layer is formed using metal organic chemical vapor deposition (MOCVD).

20. The method of claim 17, wherein the forming of the at least one amorphous region and the at least one crystalloid region comprises: forming a mask layer, comprising one or more patterns, on the first semiconductor layer;forming the at least one amorphous region by applying ion bombardment to an exposed top surface of the first semiconductor layer according to the mask layer; andforming the at least one crystalloid region, through exposing the at least one crystalloid region that results from non-bombardment, by removing the mask layer.

21. The method of claim 20, wherein the mask layer comprises photoresist, metal, or photoresist and metal.

22. The method of claim 20, wherein the mask layer comprises a striped pattern or patterns, and wherein the striped pattern is formed or the striped patterns are formed substantially in a <1-100> direction.

23. The method of claim 20, wherein a depth of greater than or equal to about 0.1 μm and less than or equal to about 4 μm is etched from the exposed top surface of the first semiconductor layer.

24. The method of claim 17, wherein the growth substrate comprises one or more of sapphire, 6H—SiC, MgAl2O3, Si(111), and ZnO.

25. The method of claim 17, wherein the III-V-group semiconductor material comprises one or more of GaN, GaAs, and InP.

26. The method of claim 18, wherein the ion bombardment comprises ions from one or more of B, P, As, Sb, BF2, In, Ar, N, and Zn.

27. The method of claim 18, wherein the ion bombardment is performed at an absolute pressure of less than about 10−5 torr.

28. The method of claim 18, wherein ions for the ion bombardment are supplied by one or more of a radio frequency (RF)-ion source, a discharge-type ion source, a surface-ionization source, and a hot electron source.

29. The method of claim 17, wherein a thickness of the first semiconductor layer is greater than or equal to about 1 μm and less than or equal to about 5 μm.

30. The method of claim 17, wherein a width of the at least one amorphous region is greater than or equal to about 2 μm and less than or equal to about 30 μm.

31. The method of claim 17, wherein a thickness of the at least one amorphous region is greater than or equal to about 1 Å and less than or equal to about 5000 Å.

32. The method of claim 17, wherein a width of the at least one crystalloid region is greater than or equal to about 1 μm and less than or equal to about 20 μm.

33. The method of claim 17, wherein the at least one amorphous region and the at least one crystalloid region are formed in a striped pattern or patterns.

34. The method of claim 33, wherein the striped pattern is formed or the striped patterns are formed substantially in a <1-100> direction.

35. The method of claim 17, wherein the second semiconductor layer is formed by growing the at least one crystalloid region substantially in a <11-20> direction.

36. The method of claim 17, wherein a defect density of the first semiconductor layer is greater than or equal to about 108 defects/cm2 and less than or equal to about 1010 defects/cm2.

37. The method of claim 17, wherein a defect density of the second semiconductor layer is greater than or equal to about 104 defects/cm2 and less than or equal to about 107 defects/cm2.

38. The method of claim 17, wherein the first semiconductor layer and the second semiconductor layer are formed of one or more nitride semiconductors.

39. A semiconductor light-emitting device, comprising: the semiconductor substrate of claim 1; anda semiconductor chip;wherein the second semiconductor layer comprises: at least one vertical growth region crystal-grown vertically from the at least one crystalloid region; andat least one lateral growth region crystal-grown laterally from the at least one vertical growth region;wherein the semiconductor chip is formed on the second semiconductor layer,wherein the semiconductor chip comprises: an n-type semiconductor layer;an active layer; anda p-type semiconductor layer; andwherein the n-type semiconductor layer, the active layer, and the p-type semiconductor layer are sequentially stacked on the second semiconductor layer.

40. A method of manufacturing a semiconductor light-emitting device, the method comprising: manufacturing a semiconductor substrate according to the method of claim 17; andsequentially forming an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the second semiconductor layer.