The field relates to bonded structures with a protective material and methods for forming bonded structures with a protective material.
In various packaging arrangements, it can be advantageous to provide thinned integrated device dies, e.g., to enable the use of multiple integrated device dies within a low-profile package. For example, three-dimensional (3D) integration techniques often utilize packages in which two or more integrated device dies are stacked on top of and electrically connected to one another. Conventional methods for die thinning and/or 3D integration may have limited product yield because stresses imparted to the dies during assembly may damage dies in the stack. Moreover, it can be challenging to stack dies which have different thicknesses and which may originate from different types of substrates and/or wafers. Accordingly, there remains a continuing need for improved systems and methods for stacking integrated device dies.
These aspects and others will be apparent from the following description of preferred embodiments and the accompanying drawing, which is meant to illustrate and not to limit the invention, wherein:
Various embodiments disclosed herein enable singulated integrated device dies to be mounted to a packaging structure (e.g., a package substrate, a wafer, another integrated device die, etc.) and to be thinned after mounting. Thinning the singulated integrated device die can aid in various aspects of package assembly, including, e.g., exposing or forming interconnects (such as through-silicon vias or TSVs). However, thinning the die by polishing or grinding may induce stresses in the die, which may damage or break edges of the die. In some embodiments, a protective material (which may comprise one or more protective layers) can be applied over and/or around the integrated device die to protect the die during thinning and, in some arrangements, during subsequent processing steps.
Moreover, various embodiments disclosed herein facilitate the efficient stacking of integrated device dies with an improved yield and reduced damage and stresses imparted to the dies. Integrated device packages and larger electronic systems may incorporate different types of integrated device dies, e.g., dies that have different functionality, dies that are formed of different material sets, and/or dies that have different thicknesses. It can be challenging to incorporate such diverse integrated device dies into a package, and/or to arrange different types of dies in a stacked relationship. For example, it may be difficult to bond two dies that are formed of, or are coated with, different materials. The material mismatch may introduce thermal and/or chemical bonding challenges for the stacked dies. Moreover, stacking dies with different thicknesses may unnecessarily increase the overall package height and/or may involve alignment challenges. Advantageously, the embodiments disclosed herein also enable the stacking of integrated device dies which have arbitrary initial thicknesses.
Accordingly, in various embodiments, a first integrated device die can be mounted to a carrier, such as a substrate (e.g., a wafer, a printed circuit board, flat panel, glass surface, surface comprising a dielectric layer, surface comprising a conductive layer or sections etc.). After mounting the first die to the carrier, the first integrated device die can be thinned. Advantageously, the first integrated device die, and subsequent dies, can be thinned on the carrier to a desired thickness. In various embodiments, the thinned die(s) can be made ultra-thin which can reduce the overall package height and enable the use of numerous dies within a particular die stack. Thinning can also facilitate exposing previously formed interconnects, or forming interconnects after thinning, such as through silicon vias (TSVs). In some arrangements, multiple dies can be mounted adjacent one another on the carrier and can be thinned using a grinding process, a polishing process, an etching process, or any other suitable process. In some arrangements, for example, when multiple adjacent dies are thinned and/or planarized by grinding, the edges of the dies may be subjected to stresses which can cause the edges of the dies to break, crack, or otherwise be damaged. To reduce incidence of die edge loss, additional materials from the die edge may be removed by low stress removal methods such as wet etch or dry etch or combinations thereof.
In some embodiments, the first integrated device die (and adjacent device dies) can be thinned with an etching process. Thinning can expose interconnects (e.g., through silicon vias, traces, contact pads, etc.) useful for electrically connecting stacked dies, or can facilitate formation of such interconnects. The first die disposed on the carrier can be coated with a protective material, including a first protective layer which acts to protect the die (including the die edges) during a grinding or polishing operation. In some embodiments, a second layer can be provided over the first layer to fill lateral gaps in the first layer. At least a portion of the second layer and the first layer can be removed. Removal of the portions of the second layer and the first layer can expose one or more electrical interconnects formed through the first integrated device die. A second integrated device die can be stacked on the first integrated device die. In some embodiments, non-conductive regions of the second die are directly bonded to corresponding non-conductive regions of the first die without an intervening adhesive. In some embodiments, both non-conductive regions and electrical interconnects of the second die are directly bonded to corresponding non-conductive regions and electrical interconnects, respectively, of the first die without an intervening adhesive.
The first integrated device die(s) 3 can comprise any suitable type of device die. For example, each of the first die(s) 3a, 3b can comprise a processor die, a memory die, a microelectromechanical systems (MEMS) die, a passive component, an optical device, or any other suitable type of device die. Circuitry (such as active components like transistors) can be patterned at or near active surfaces 6 of the die(s) 3a, 3b in various embodiments. The active surfaces 6 may be on a side of the dies 3a, 3b which is opposite respective backsides 18 of the dies 3a, 3b. The backsides 18 may or may not include any active circuitry or passive devices. The first dies 3a, 3b may be the same type of integrated device die or a different type of device die. As shown in
Conductive elements can be provided in one or more layers on the upper surface 8 of the substrate 2 to provide electrical connection to other devices and/or routing to other components within the substrate 2. In some embodiments, the one or more layers can comprise a routing layer 34 and a buffer layer 5, as shown in
One or more electrical interconnects 10 may be formed through at least a portion of each first die 3a, 3b. Each interconnect 10 may be formed inside a non-conductive liner 9. In various embodiments, the interconnects 10 and liners 9 may be formed using a damascene process in which one or more cavities are formed, and the liners 9 and interconnects 10 can be deposited in the cavities (e.g., trenches). In various embodiments, the interconnects 10 can comprise through substrate vias (TSVs), traces, or both. In some embodiments, the interconnects 10 can comprise traces or contact pads which are exposed at the surface of the dies 3a, 3b. As shown in
Advantageously, the methods disclosed herein can be utilized with dies 3a, 3b that have any suitable initial thickness ti, including thin dies, thick dies, intermediate-size dies, or any other arbitrary die thickness. Moreover, although the dies 3a, 3b shown in
The first dies 3a, 3b can be attached to the substrate 2 using any suitable method. For example, in the illustrated embodiment, the first dies 3a, 3b can be directly bonded to the substrate 2 without an intervening adhesive. In direct bonding arrangements, non-conductive field regions 20 of the dies 3a, 3b can directly contact and be directly bonded with corresponding non-conductive regions of the substrate 2. The bond pads or traces at the active surfaces 6, such as those connected to conductive interconnects 10, can contact and be directly bonded to corresponding metallic pads (or traces or other conducting features) of the routing layer 34, which may be exposed through openings in the buffer layer 5, and may protrude or be recessed.
In some embodiments, some or all of the bond pads or traces at the active surfaces 6, such as those connected to conductive interconnects 10, can be directly bonded to non-conductive features of the routing layer 34. In such embodiments, in subsequent steps, the substrate 2 can be thinned from the backside and conductive contacts can be formed from the thinned substrate 2 to electrically couple to the conductive bond pads or traces on the active surface of the dies 3a and/or 3b. In other embodiments, the dies 3a, 3b can be adhered to the substrate 2 with any suitable adhesive, such as solder, a conductive epoxy, anisotropic conductive film, etc.
To accomplish the direct bonding, in some embodiments, the bonding surfaces of the dies 3a, 3b and the substrate 2 can be prepared for bonding. The first dies 3a, 3b can be polished to a very high degree of smoothness (e.g., less than 20 nm surface roughness, or more particularly, less than 5 nm surface roughness). In some embodiments, a bonding layer 11 (e.g., a dielectric such as silicon oxide) may be deposited on the active surfaces 6 of the dies 3a, 3b and polished to a very high degree of smoothness. Similarly, the bonding surface of the substrate 2 (e.g., the upper surface 8 of the substrate 2 or the upper surface of the buffer layer 5) may be polished to a very high degree of smoothness (e.g., less than 20 nm surface roughness, or more particularly, less than 5 nm surface roughness). In some embodiments, the bonding surfaces (e.g., the buffer layer 5, the upper surface 8 of the substrate 2, the bonding layer 11, and/or the active surface 6) may be fluorinated to improve bonding. The bonding surfaces may also include conductive features, such as bond pads. In some embodiments, the surfaces to be bonded may be terminated with a suitable species and activated prior to bonding. For example, in some embodiments, the surfaces to be bonded may be very lightly etched for activation and exposed to a nitrogen-containing solution and terminated with a nitrogen-containing species. As one example, the surfaces to be bonded may be exposed to an ammonia dip after a very slight etch, and/or a nitrogen-containing plasma (with or without a separate etch).
Once the surfaces are prepared, the nonconductive field regions 20 of the dies 3a, 3b can be brought into contact with corresponding nonconductive regions of the substrate 2. The interaction of the activated surfaces can cause the nonconductive regions 20 of the dies 3a, 3b to directly bond with the corresponding nonconductive regions of the substrate 2 without an intervening adhesive, without application of external pressure, without application of voltage, and at room temperature. In various embodiments, the bonding forces of the nonconductive regions can be covalent bonds that are greater than Van der Waals bonds and exert significant forces between the conductive features on the surface of dies 3a and the corresponding contact pads of the substrate 2. In some embodiments, the interconnects 10 and/or the contact pads are flush with the exterior surfaces of the dies 3a, 3b and the substrate 2. In other embodiments, the interconnects 10 and/or the contact pads may extend above the exterior surfaces of the dies 3a, 3b and the substrate 2. In still other embodiments, the interconnects 10 and/or the contact pads are recessed relative to the exterior surfaces (e.g., oxide field regions) of the dies 3a, 3b and the substrate 2. In various embodiments, the substrate 2 and dies 3a, 3b may be heated after bonding to strengthen the bonds between the nonconductive regions, between the conductive regions, and/or between opposing conductive and non-conductive regions, to cause the dies 3a, 3b to bond with the substrate 2. Additional details of the direct bonding processes may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; and 8,735,219, and throughout U.S. patent application Ser. Nos. 14/835,379; 62/278,354; and 62/303,930, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes.
Although the embodiment of
Turning to
In various embodiments, the final thickness tf of the dies 3a, 3b may be less than 40 microns, less than 30 microns, or less than 20 microns. The final thickness tf of the dies 3a, 3b may be in a range of 5 microns to 30 microns, or more particularly, in a range of 5 microns to 15 microns, or more particularly, in a range of 5 microns to 10 microns. The final thickness tf of the dies 3a, 3b may be the same or may be different from one another. In various embodiments, the final thickness tf of the dies 3a, 3b may be less than 300 microns, less than 200 microns, or less than 100 microns. The final thickness tf of the dies 3a, 3b may be in a range of 40 to 100 microns in some embodiments.
Turning to
Advantageously, the first layer 12 can act as a protective layer to protect the dies 3a, 3b during subsequent processing steps. For example, as explained below in connection with
The first layer 12 may be harder than the exposed back surface 19 of the dies 3a, 3b in some embodiments. The first layer 12 may be hard and dense compared to unfilled polyimide or epoxy resin coating so as to protect the dies 3a, 3b. For example, the first layer 12 can have a relatively high Young's modulus in a range of 12 GPa to 500 GPa, or more particularly, in a range of 20 GPa to 200 GPa. Beneficially, the first layer 12 can have a coefficient of thermal expansion which is substantially matched with the coefficient of thermal expansion of the substrate 2. Matching the thermal expansion coefficients can advantageously reduce thermally-induced stress on the dies 3a, 3b. In some embodiments, the coefficient of thermal expansion of the first layer 12 can be within 25 ppm/° C. of the coefficient of thermal expansion of the first dies 3a, 3b, or more particularly within 20 ppm/° C. of the coefficient of thermal expansion of the first dies 3a, 3b. For example, the coefficient of thermal expansion of the first layer 12 can be in a range of 0.3 ppm/° C. to 22 ppm/° C., in a range of 0.5 ppm/° C. to 15 ppm/° C., in a range of 2 ppm/° C. to 15 ppm/° C., or more particularly, in a range of 0.5 ppm/° C. to 12 ppm/° C., or more particularly, in a range of 2 ppm/° C. to 10 ppm/° C.
Moreover, it can be important to select the first layer 12 such that it has a sufficiently high glass transition temperature (GTT). Subsequent processing steps may involve heating the partially-formed structure 1 to high temperatures. For example, the structure 1 may be heated during processing of subsequent conductive layers (such as RDL layers) and/or during bonding to temperatures greater than 150° C., greater than 200° C., or greater than 250° C. Some polymers, epoxies, and other materials may soften significantly during such high temperature processing. It can be important to choose a material for the first layer 12 which can withstand high temperature processing and maintain its geometric profile and/or does not deform irreversibly during the various thermal processing steps. Thus, it can be advantageous to select a first layer 12 which has a high GTT, e.g., a GTT greater than 100° C., greater than 150° C., greater than 200° C., greater than 250° C., or greater than 300° C. In some embodiment, for a crosslinked material, the GTT of the first layer can be less than 100° C. provided that the Poisson ratio is greater than 0.4 and preferably close to 0.5, e.g., a Poisson ratio in a range of 0.25 to 0.8, and with a thermal decomposition temperature greater than 250° C., or greater than 300° C. In some embodiments, as explained herein, a polymer material can be used for the first layer 12 (and/or for additional protective layers such as the second layer 15 described below). The polymer material or matrix can have a melting point greater than 150° C., greater than 200° C., greater than 250° C., greater than 300° C., or greater than 350° C., e.g., greater than 280° C. in some embodiments.
Accordingly, it can be important to select a first layer 12 which is stiff and/or hard with a high Young's modulus, which has a coefficient of thermal expansion similar to that of the substrate (e.g., similar to that of silicon or glass in the case of silicon or glass substrates), and which has a glass transition temperature, or GTT, which exceeds the highest processing temperatures used to form the bonded structure 1. For example, in some embodiments, the first layer 12 can comprise silicon, inorganic oxide, inorganic nitride, inorganic carbide, or carbonate, for example, silicon oxide, silicon nitride, silicon carbide, diamond like carbon (DLC) or other types of semiconductor materials and non-semiconductor materials. In other embodiments, a polymer may be used. For example, the first layer 12 may comprise a polyimide or polyimide-amide. In some embodiments, the first layer 12 can comprise Torlon®. In some embodiments, as explained herein, the first layer 12 can comprise a base material (such as a polymer) that is filled with filler particles (such as oxide or nitride particles, carbonates, mica, treated or untreated kaolin, talc, or treated or untreated clay materials, for example, bentonite clay, etc.). The filler particles may assist in reducing the thermal expansion coefficient of layer 12 and rendering the CTE of layer 12 closer to that of the substrate 2. The filler particles may increase the hardness or stiffness of the layer 12. The filler content can vary between 10% to 90%, e.g., between 20% and 85%, or more particularly, between 30% and 80%. The filler particles may be sized in a range of 2 nm to less than 20 microns, e.g., between 50 nm and 5 microns. In one embodiment, the average size of the filler particulate is less than 30% of the gap 7 disposed between dies 3a and 3b. In other embodiments the average size of the filler particulate is less than 10% of the gap 7 between dies 3a and 3b, e.g., less than 2% of the gap 7 between dies 3a and 3b. In some embodiments, the average size of the filler particulate in the gap 7 is less than 30% of the final die thickness tf, e.g., at least some of the filler particles are less than 5% of the final thickness tf of the die. In some embodiments, the width or length of a particulate on or adjacent to the vertical side wall of dies 3a or 3b is less than 15% of the final thickness tf of the dies 3a or 3b. Because the dies 3a, 3b have already been thinned in the illustrated embodiment, these materials may be used with the first layer 12 without introducing excessive stresses or excessive costs.
In
Turning to
As shown in
In
The resulting bonded structure 1 can therefore include one or more second dies 4a, 4b directly bonded to one or more first dies 3a, 3b without intervening adhesives, which in turn are directly bonded to the substrate 2. In some embodiments, respective interconnects 10 of the first dies 3a, 3b and second dies 4a, 4b may also be directly bonded together. The interconnects 10 may comprise a through silicon via (TSV) formed in the dies 3-4 and contact pads at the active surfaces 6 of the dies. A first portion 13 of the first layer 12 may be disposed laterally between the first dies 3a, 3b. The first portion 13 of the first layer may be disposed on a side surface of the first dies 3a, 3b. A second portion 14 of the first layer 12 may be disposed vertically between the first die 3a and the second die 4a, and between the first die 3b and the second die 4b. The second portion 14 of the first layer 12 may be laterally disposed around the electrical interconnects 10 such that the electrical interconnects 10 are exposed through the layer 12. In some embodiments, the stacked dies 3, 4 may be packaged together in an integrated device package after assembly. In other embodiments, the two stacked dies 3, 4 may be singulated and packaged in separate integrated device packages.
Moreover, although not shown in
As with
Turning to
Turning to
In
Turning to
Turning to
As with
The first layer 12 shown in
In
Thus, it can be advantageous to select a second layer 15 which has a high GTT, e.g., a GTT greater than 100° C., greater than 150° C., greater than 200° C., greater than 250° C., or greater than 300° C. In some embodiment, for a crosslinked material, the GTT of the first layer can be less than 100° C. provided that the Poisson ratio is greater than 0.4 and preferably close to 0.5, e.g., a Poisson ratio in a range of 0.25 to 0.8, and with a thermal decomposition temperature greater than 250° C., or greater than 300° C.
As explained above, it can be important to select a second layer 15 which is stiff and/or hard with a high Young's modulus, which has a coefficient of thermal expansion similar to that of the substrate (e.g., similar to that of silicon or glass in the case of silicon or glass substrates), and which has a glass transition temperature, or GTT, which exceeds the highest processing temperatures used to form the bonded structure 1. For example, in some embodiments, the second layer 15 can comprise silicon, inorganic oxide, inorganic nitride, inorganic carbide, or carbonate, for example, silicon oxide, silicon nitride, silicon carbide, diamond like carbon (DLC) or other types of semiconductor materials and non-semiconductor materials. In other embodiments, a polymer may be used. For example, the second layer 15 may comprise a polyimide or polyimide-amide. In some embodiments, the second layer 15 can comprise Torlon®. In some embodiments, as explained herein, the first layer 12 can comprise a base material (such as a polymer) that is filled with filler particles (such as oxide or nitride particles, or carbonates, or mica, treated or untreated kaolin, talc treated or clay materials for example untreated bentonite). The filler particles may assist in reducing the thermal expansion coefficient of layer 15 and rendering the CTE of layer 15 closer to that of the substrate 2 or first layer 12. The filler may increase the hardness or stiffness of the layer 12. The filler content in layer 12 can vary between 10% to 90%, e.g., between 20% and 85%, or more particularly, between 30% and 80%. The filler particles may be sized in a range of 2 nm to less than 20 microns, e.g., between 50 nm and 5 microns. In one embodiment, the size of a filler particulate is less than 30% of the gap 7 disposed between dies 3a and 3b. In other embodiments the size of a filler particulate is less than 10% of the gap 7 between dies 3a and 3b, e.g., less than 2% of the gap 7 between dies 3a and 3b. In some embodiments, the size of a filler particulate in the gap 7 is less than 30% of the final die thickness tf and preferably less than 5% of the final thickness tf of the die. In some embodiments, the width or length of a particulate adjacent to the vertical side wall dies 3a or 3b can be less than 15% of the final thickness tf of the dies 3a or 3b. Because the dies 3a, 3b have already been thinned in the illustrated embodiment, these materials may be used with the first layer 12 without introducing excessive stresses or excessive expense.
The second layer 15 may comprise a filler layer which fills spaces or gaps in the first layer 12 to facilitate planarization. The second filler layer 15 may comprise the types of particulates recited above for the first layer 12. The second layer 15 can have a thickness in a range of 4 to 120 microns, or more particularly, in a range of 8 microns to 45 microns. As shown, the second layer 15 comprises a third portion 16 adjacent the dies 3a, 3b, such as in the gaps 7 between dies where multiple dies are laterally arrayed as shown, and a fourth portion 17 over the dies 3a, 3b.
As with the embodiment of
In
Advantageously, the embodiment of
For example, in
Unlike the embodiment of
Beneficially, the additional protective layer 40 can provide a symmetric protective material adjacent the die(s), which can serve as an inter-die dielectric layer. In some arrangements without the additional layer 40, when the backside of the structure 1 is polished (e.g., by CMP), there may be dishing in the region between the dies 3a, 3b, e.g., dishing in the third portions 16 of the second layer 15. For example, the second layer 15 may comprise a material which is not as hard as the first or third layers. Polishing the third portions 16 of the second layer 15 may cause dishing which can negatively affect the stacking and bonding of the dies and/or can create voids or misalignments. Accordingly, providing the additional protective layer 40 can fill in the recessed regions of the third portion 16 of the second layer 15 (which may be hard) and can protect the second layer 15 from dishing and further protect the dies 3a, 3b. Furthermore, the symmetry of the protective material provides a balanced coefficient of thermal expansion (CTE) for the cavity between dies 3a, 3b on the substrate 2.
Thus, in
In
As shown in
To planarize the partially-formed structure, in
Turning to
In
Turning to
In
Turning to a block 74, after mounting, the first integrated device die can be thinned. For example, in some arrangements, the backside of the first die (which may be opposite the active or front side) can be etched, grinded, or polished to remove portions of the first die. Thinning the first die can enable the use of multiple device dies in a low-profile packaging arrangements. Moreover, as explained herein, in some embodiments, interconnects (e.g., TSVs) may be formed in the first die before thinning or after thinning. In the embodiments of
Turning to a block 78, after mounting, a protective material comprising a first layer can be provided on a surface of the first integrated device die. Beneficially, the first layer can protect the edges of the first die from chipping during planarization or other processing steps. The first layer can comprise a relatively hard material with a CTE which is close to that of the first die and which has a relatively high GTT. The first layer can be provided over the exposed back surface of the first die and over portions of the carrier between adjacent dies. As explained herein, in some embodiments, the protective material can include additional layers (such as portions of the second layer 15, the third layer 45, and the additional protective layer 40) disposed over the first die and/or in the space between adjacent dies.
In a block 79, at least a portion of the first layer can be planarized to remove a portion of the first integrated device die. For example, in some embodiments, a chemical mechanical polishing (CMP) technique can be used to remove some of the first layer, which can expose interconnects in some embodiments. In embodiments in which the protective material comprises multiple layers, the other layers may be partially or entirely removed during planarization. Advantageously, the protective material can protect the dies during the planarization process. As explained herein, additional device dies can be stacked on and connected to (e.g., directly bonded with) the first integrated device die.
Thus, the embodiments disclosed herein can advantageously enable the thinning of dies after singulation, at the packaging level. The use of the protective material including the first protective layer 12 can beneficially protect the dies, and in particular, the die edges, during polishing. The first protective layer 12 can lock in and seal the dies during processing. Moreover, the protective material can further include the second filler material between gaps of the first layer 12 which can beneficially facilitate planarization of the structure. In some embodiments, a third filler material, and indeed any suitable number of filler materials, can be used to facilitate planarization of the structures. In some embodiments, the second filler material can include embedded filler particles to improve the mechanical and thermal properties of the filler material. In some embodiments, an additional protective layer 40 may be provided over the second layer 15 (or other layers) to provide a symmetric dielectric structure which resists dishing and improves overall yield. Thinning after mounting singulated dies on a substrate can also facilitate subsequent stacking and bonding of dies.
Advantageously, the methods disclosed herein can use dies with any suitable initial thickness, and adjacent dies may have different thicknesses. In addition, the etch times of the dies (e.g., silicon dies) can be reduced since the amount of etching may be less than in other processes. Moreover, the time for polishing, plating, and providing the conductive interconnects may also be reduced since the dies may be thinned prior to forming the interconnects in some embodiments.
In one embodiment, a method for forming a bonded structure is disclosed. The method can comprise mounting a first singulated integrated device die to a carrier. The method can comprise thinning the first integrated device die after mounting. The method can comprise providing a protective material comprising a first layer on an exposed surface of the first integrated device die.
In another embodiment, a bonded structure is disclosed. The bonded structure can include a carrier and a first integrated device die having a lower surface mounted to an upper surface of the carrier. The first integrated device die can comprise an upper surface opposite the lower surface and a side surface between the upper and lower surfaces of the first integrated device die. The bonded structure can comprise a protective material comprising a first layer having a first portion disposed on the side surface of the first integrated device die, the first layer being harder than side surface of the first integrated device die.
In another embodiment, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. The method can comprise, after mounting, providing a protective material comprising a first layer on a surface of the first integrated device die. The method can comprise planarizing at least a portion of the first layer to remove a portion of the first integrated device die.
For purposes of summarizing the disclosed embodiments and the advantages achieved over the prior art, certain objects and advantages have been described herein. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
All of these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment(s) disclosed. Although this certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the disclosed implementations. Thus, it is intended that the scope of the subject matter herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.
This application is a continuation of U.S. patent application Ser. No. 17/131,329 (U.S. Pat. No. 11,658,173), filed Dec. 22, 2020, which is a continuation of U.S. patent application Ser. No. 16/270,466 (U.S. Pat. No. 10,879,226), filed Feb. 7, 2019, which is a continuation of U.S. patent application Ser. No. 15/159,649 (U.S. Pat. No. 10,204,893), filed May 19, 2016, the entire contents of each of which are hereby incorporated by reference herein.
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Morrison, Jim et al., “Samsung Galaxy S7 Edge Teardown,” Tech Insights (posted Apr. 24, 2016), includes description of hybrid bonded Sony IMX260 dual-pixel sensor, https://www.techinsights.com/blog/samsung-galaxy-s7-edge-teardown, downloaded Jul. 11, 2023, 9 pages. |
NASA SBIR/STTR Technologies, Proposal No. 09-1 S5.05-9060—Reliable Direct Bond Copper Ceramic Packages for High Temperature Power Electronics, Contract No. NNX10CE23P, PI: Ender Savrun, PhD, Sienna Technologies, Inc.—Woodinville, WA, 1 page. |
Onsemi AR0820 image, cross section of a CMOS image sensor product. The part in the image was shipped on Sep. 16, 2021. Applicant makes no representation that the part in the image is identical to the part identified in the separately submitted reference Bush, Nov. 8, 2018, ElectronicsWeekly.com (“Bush article”); however, the imaged part and the part shown in the Bush article share the part No. “Onsemi AR0820.”. |
Reiche et al., “The effect of a plasma pretreatment on the Si/Si bonding behaviour,” Electrochemical Society Proceedings, 1998, vol. 97-36, pp. 437-444. |
Sony IMX260 image, a first cross section of Sony product labeled IMX260, showing a hybrid bonded back side illuminated CMOS image sensor with a pad opening for a wire bond. The second image shows a second cross-section with peripheral probe and wire bond pads in the bonded structure. The part in the images was shipped in Apr. 2016. Applicant makes no representation that the part in the images is identical to the part identified in the separately submitted reference Morrison et al. (Tech Insights article dated Apr. 24, 2016), describing and showing a similar sensor product within the Samsung Galaxy S7; however the imaged part and the part shown in the Morrison et al. article share the part name “Sony IMX260 image.” |
Urteaga, M. et al., “THz bandwidth InP HBT technologies and heterogeneous integration with Si CMOS,” 2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2016, pp. 35-41, doi: 10.1109/BCTM.2016.7738973. |
Number | Date | Country | |
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20230130580 A1 | Apr 2023 | US |
Number | Date | Country | |
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Parent | 17131329 | Dec 2020 | US |
Child | 18145282 | US | |
Parent | 16270466 | Feb 2019 | US |
Child | 17131329 | US | |
Parent | 15159649 | May 2016 | US |
Child | 16270466 | US |